src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_gs_prog, /* must do before state base address */
  44    &brw_clip_prog, /* must do before state base address */
  45    &brw_sf_prog, /* must do before state base address */
  46    &brw_wm_prog, /* must do before state base address */
  47
  48    /* Once all the programs are done, we know how large urb entry
  49     * sizes need to be and can decide if we need to change the urb
  50     * layout.
  51     */
  52    &brw_curbe_offsets,
  53    &brw_recalculate_urb_fence,
  54
  55    &brw_cc_vp,
  56    &brw_cc_unit,
  57
  58    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  59     * table upload must be last.
  60     */
  61    &brw_vs_pull_constants,
  62    &brw_wm_pull_constants,
  63    &brw_renderbuffer_surfaces,
  64    &brw_texture_surfaces,
  65    &brw_vs_binding_table,
  66    &brw_wm_binding_table,
  67
  68    &brw_samplers,
  69
  70    /* These set up state for brw_psp_urb_cbs */
  71    &brw_wm_unit,
  72    &brw_sf_vp,
  73    &brw_sf_unit,
  74    &brw_vs_unit,                /* always required, enabled or not */
  75    &brw_clip_unit,
  76    &brw_gs_unit,
  77
  78    /* Command packets:
  79     */
  80    &brw_invariant_state,
  81    &brw_state_base_address,
  82
  83    &brw_binding_table_pointers,
  84    &brw_blend_constant_color,
  85
  86    &brw_depthbuffer,
  87
  88    &brw_polygon_stipple,
  89    &brw_polygon_stipple_offset,
  90
  91    &brw_line_stipple,
  92    &brw_aa_line_parameters,
  93
  94    &brw_psp_urb_cbs,
  95
  96    &brw_drawing_rect,
  97    &brw_indices,
  98    &brw_index_buffer,
  99    &brw_vertices,
 100
 101    &brw_constant_buffer
 102 };
 103
 104 static const struct brw_tracked_state *gen6_atoms[] =
 105 {
 106    &brw_vs_prog, /* must do before state base address */
 107    &brw_gs_prog, /* must do before state base address */
 108    &brw_wm_prog, /* must do before state base address */
 109
 110    &gen6_clip_vp,
 111    &gen6_sf_vp,
 112
 113    /* Command packets: */
 114
 115    /* must do before binding table pointers, cc state ptrs */
 116    &brw_state_base_address,
 117
 118    &brw_cc_vp,
 119    &gen6_viewport_state,        /* must do after *_vp stages */
 120
 121    &gen6_urb,
 122    &gen6_blend_state,           /* must do before cc unit */
 123    &gen6_color_calc_state,      /* must do before cc unit */
 124    &gen6_depth_stencil_state,   /* must do before cc unit */
 125    &gen6_cc_state_pointers,
 126
 127    &gen6_vs_push_constants, /* Before vs_state */
 128    &gen6_wm_push_constants, /* Before wm_state */
 129
 130    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 131     * table upload must be last.
 132     */
 133    &brw_vs_pull_constants,
 134    &brw_vs_ubo_surfaces,
 135    &brw_wm_pull_constants,
 136    &brw_wm_ubo_surfaces,
 137    &gen6_renderbuffer_surfaces,
 138    &brw_texture_surfaces,
 139    &gen6_sol_surface,
 140    &brw_vs_binding_table,
 141    &gen6_gs_binding_table,
 142    &brw_wm_binding_table,
 143
 144    &brw_samplers,
 145    &gen6_sampler_state,
 146    &gen6_multisample_state,
 147
 148    &gen6_vs_state,
 149    &gen6_gs_state,
 150    &gen6_clip_state,
 151    &gen6_sf_state,
 152    &gen6_wm_state,
 153
 154    &gen6_scissor_state,
 155
 156    &gen6_binding_table_pointers,
 157
 158    &brw_depthbuffer,
 159
 160    &brw_polygon_stipple,
 161    &brw_polygon_stipple_offset,
 162
 163    &brw_line_stipple,
 164    &brw_aa_line_parameters,
 165
 166    &brw_drawing_rect,
 167
 168    &brw_indices,
 169    &brw_index_buffer,
 170    &brw_vertices,
 171 };
 172
 173 static const struct brw_tracked_state *gen7_atoms[] =
 174 {
 175    &brw_vs_prog,
 176    &brw_wm_prog,
 177
 178    /* Command packets: */
 179
 180    /* must do before binding table pointers, cc state ptrs */
 181    &brw_state_base_address,
 182
 183    &brw_cc_vp,
 184    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 185    &gen7_sf_clip_viewport,
 186
 187    &gen7_urb,
 188    &gen6_blend_state,           /* must do before cc unit */
 189    &gen6_color_calc_state,      /* must do before cc unit */
 190    &gen6_depth_stencil_state,   /* must do before cc unit */
 191    &gen7_cc_state_pointer,
 192    &gen7_depth_stencil_state_pointer,
 193
 194    &gen6_vs_push_constants, /* Before vs_state */
 195    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 196
 197    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 198     * table upload must be last.
 199     */
 200    &brw_vs_pull_constants,
 201    &brw_vs_ubo_surfaces,
 202    &brw_wm_pull_constants,
 203    &brw_wm_ubo_surfaces,
 204    &gen6_renderbuffer_surfaces,
 205    &brw_texture_surfaces,
 206    &brw_vs_binding_table,
 207    &brw_wm_binding_table,
 208
 209    &gen7_samplers,
 210    &gen6_multisample_state,
 211
 212    &gen7_disable_stages,
 213    &gen7_vs_state,
 214    &gen7_sol_state,
 215    &gen7_clip_state,
 216    &gen7_sbe_state,
 217    &gen7_sf_state,
 218    &gen7_wm_state,
 219    &gen7_ps_state,
 220
 221    &gen6_scissor_state,
 222
 223    &gen7_depthbuffer,
 224
 225    &brw_polygon_stipple,
 226    &brw_polygon_stipple_offset,
 227
 228    &brw_line_stipple,
 229    &brw_aa_line_parameters,
 230
 231    &brw_drawing_rect,
 232
 233    &brw_indices,
 234    &brw_index_buffer,
 235    &brw_vertices,
 236
 237    &haswell_cut_index,
 238 };
 239
 240 static void
 241 brw_upload_initial_gpu_state(struct brw_context *brw)
 242 {
 243    struct intel_context *intel = &brw->intel;
 244
 245    /* On platforms with hardware contexts, we can set our initial GPU state
 246     * right away rather than doing it via state atoms.  This saves a small
 247     * amount of overhead on every draw call.
 248     */
 249    if (!intel->hw_ctx)
 250       return;
 251
 252    brw_upload_invariant_state(brw);
 253
 254    if (intel->gen >= 7) {
 255       gen7_allocate_push_constants(brw);
 256    }
 257 }
 258
 259 void brw_init_state( struct brw_context *brw )
 260 {
 261    const struct brw_tracked_state **atoms;
 262    int num_atoms;
 263
 264    brw_init_caches(brw);
 265
 266    if (brw->intel.gen >= 7) {
 267       atoms = gen7_atoms;
 268       num_atoms = ARRAY_SIZE(gen7_atoms);
 269    } else if (brw->intel.gen == 6) {
 270       atoms = gen6_atoms;
 271       num_atoms = ARRAY_SIZE(gen6_atoms);
 272    } else {
 273       atoms = gen4_atoms;
 274       num_atoms = ARRAY_SIZE(gen4_atoms);
 275    }
 276
 277    brw->atoms = atoms;
 278    brw->num_atoms = num_atoms;
 279
 280    while (num_atoms--) {
 281       assert((*atoms)->dirty.mesa |
 282              (*atoms)->dirty.brw |
 283              (*atoms)->dirty.cache);
 284       assert((*atoms)->emit);
 285       atoms++;
 286    }
 287
 288    brw_upload_initial_gpu_state(brw);
 289 }
 290
 291
 292 void brw_destroy_state( struct brw_context *brw )
 293 {
 294    brw_destroy_caches(brw);
 295 }
 296
 297 /***********************************************************************
 298  */
 299
 300 static bool
 301 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 302 {
 303    return ((a->mesa & b->mesa) |
 304            (a->brw & b->brw) |
 305            (a->cache & b->cache)) != 0;
 306 }
 307
 308 static void accumulate_state( struct brw_state_flags *a,
 309                               const struct brw_state_flags *b )
 310 {
 311    a->mesa |= b->mesa;
 312    a->brw |= b->brw;
 313    a->cache |= b->cache;
 314 }
 315
 316
 317 static void xor_states( struct brw_state_flags *result,
 318                              const struct brw_state_flags *a,
 319                               const struct brw_state_flags *b )
 320 {
 321    result->mesa = a->mesa ^ b->mesa;
 322    result->brw = a->brw ^ b->brw;
 323    result->cache = a->cache ^ b->cache;
 324 }
 325
 326 struct dirty_bit_map {
 327    uint32_t bit;
 328    char *name;
 329    uint32_t count;
 330 };
 331
 332 #define DEFINE_BIT(name) {name, #name, 0}
 333
 334 static struct dirty_bit_map mesa_bits[] = {
 335    DEFINE_BIT(_NEW_MODELVIEW),
 336    DEFINE_BIT(_NEW_PROJECTION),
 337    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 338    DEFINE_BIT(_NEW_COLOR),
 339    DEFINE_BIT(_NEW_DEPTH),
 340    DEFINE_BIT(_NEW_EVAL),
 341    DEFINE_BIT(_NEW_FOG),
 342    DEFINE_BIT(_NEW_HINT),
 343    DEFINE_BIT(_NEW_LIGHT),
 344    DEFINE_BIT(_NEW_LINE),
 345    DEFINE_BIT(_NEW_PIXEL),
 346    DEFINE_BIT(_NEW_POINT),
 347    DEFINE_BIT(_NEW_POLYGON),
 348    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 349    DEFINE_BIT(_NEW_SCISSOR),
 350    DEFINE_BIT(_NEW_STENCIL),
 351    DEFINE_BIT(_NEW_TEXTURE),
 352    DEFINE_BIT(_NEW_TRANSFORM),
 353    DEFINE_BIT(_NEW_VIEWPORT),
 354    DEFINE_BIT(_NEW_ARRAY),
 355    DEFINE_BIT(_NEW_RENDERMODE),
 356    DEFINE_BIT(_NEW_BUFFERS),
 357    DEFINE_BIT(_NEW_MULTISAMPLE),
 358    DEFINE_BIT(_NEW_TRACK_MATRIX),
 359    DEFINE_BIT(_NEW_PROGRAM),
 360    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 361    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 362    DEFINE_BIT(_NEW_FRAG_CLAMP),
 363    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 364    {0, 0, 0}
 365 };
 366
 367 static struct dirty_bit_map brw_bits[] = {
 368    DEFINE_BIT(BRW_NEW_URB_FENCE),
 369    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 370    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 371    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 372    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 373    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 374    DEFINE_BIT(BRW_NEW_CONTEXT),
 375    DEFINE_BIT(BRW_NEW_PSP),
 376    DEFINE_BIT(BRW_NEW_SURFACES),
 377    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 378    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 379    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 380    DEFINE_BIT(BRW_NEW_INDICES),
 381    DEFINE_BIT(BRW_NEW_VERTICES),
 382    DEFINE_BIT(BRW_NEW_BATCH),
 383    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 384    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 385    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 386    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 387    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 388    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 389    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 390    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 391    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 392    {0, 0, 0}
 393 };
 394
 395 static struct dirty_bit_map cache_bits[] = {
 396    DEFINE_BIT(CACHE_NEW_DEPTH_STENCIL_STATE),
 397    DEFINE_BIT(CACHE_NEW_COLOR_CALC_STATE),
 398    DEFINE_BIT(CACHE_NEW_CC_VP),
 399    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 400    DEFINE_BIT(CACHE_NEW_WM_PROG),
 401    DEFINE_BIT(CACHE_NEW_SAMPLER),
 402    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 403    DEFINE_BIT(CACHE_NEW_SF_PROG),
 404    DEFINE_BIT(CACHE_NEW_SF_VP),
 405    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 406    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 407    DEFINE_BIT(CACHE_NEW_VS_PROG),
 408    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 409    DEFINE_BIT(CACHE_NEW_GS_PROG),
 410    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 411    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 412    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 413    {0, 0, 0}
 414 };
 415
 416
 417 static void
 418 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 419 {
 420    int i;
 421
 422    for (i = 0; i < 32; i++) {
 423       if (bit_map[i].bit == 0)
 424          return;
 425
 426       if (bit_map[i].bit & bits)
 427          bit_map[i].count++;
 428    }
 429 }
 430
 431 static void
 432 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 433 {
 434    int i;
 435
 436    for (i = 0; i < 32; i++) {
 437       if (bit_map[i].bit == 0)
 438          return;
 439
 440       fprintf(stderr, "0x%08x: %12d (%s)\n",
 441               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 442    }
 443 }
 444
 445 /***********************************************************************
 446  * Emit all state:
 447  */
 448 void brw_upload_state(struct brw_context *brw)
 449 {
 450    struct gl_context *ctx = &brw->intel.ctx;
 451    struct intel_context *intel = &brw->intel;
 452    struct brw_state_flags *state = &brw->state.dirty;
 453    int i;
 454    static int dirty_count = 0;
 455
 456    state->mesa |= brw->intel.NewGLState;
 457    brw->intel.NewGLState = 0;
 458
 459    state->brw |= ctx->NewDriverState;
 460    ctx->NewDriverState = 0;
 461
 462    if (brw->emit_state_always) {
 463       state->mesa |= ~0;
 464       state->brw |= ~0;
 465       state->cache |= ~0;
 466    }
 467
 468    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 469       brw->fragment_program = ctx->FragmentProgram._Current;
 470       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 471    }
 472
 473    if (brw->vertex_program != ctx->VertexProgram._Current) {
 474       brw->vertex_program = ctx->VertexProgram._Current;
 475       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 476    }
 477
 478    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 479       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 480       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 481    }
 482
 483    if ((state->mesa | state->cache | state->brw) == 0)
 484       return;
 485
 486    intel_check_front_buffer_rendering(intel);
 487
 488    if (unlikely(INTEL_DEBUG)) {
 489       /* Debug version which enforces various sanity checks on the
 490        * state flags which are generated and checked to help ensure
 491        * state atoms are ordered correctly in the list.
 492        */
 493       struct brw_state_flags examined, prev;
 494       memset(&examined, 0, sizeof(examined));
 495       prev = *state;
 496
 497       for (i = 0; i < brw->num_atoms; i++) {
 498          const struct brw_tracked_state *atom = brw->atoms[i];
 499          struct brw_state_flags generated;
 500
 501          if (check_state(state, &atom->dirty)) {
 502             atom->emit(brw);
 503          }
 504
 505          accumulate_state(&examined, &atom->dirty);
 506
 507          /* generated = (prev ^ state)
 508           * if (examined & generated)
 509           *     fail;
 510           */
 511          xor_states(&generated, &prev, state);
 512          assert(!check_state(&examined, &generated));
 513          prev = *state;
 514       }
 515    }
 516    else {
 517       for (i = 0; i < brw->num_atoms; i++) {
 518          const struct brw_tracked_state *atom = brw->atoms[i];
 519
 520          if (check_state(state, &atom->dirty)) {
 521             atom->emit(brw);
 522          }
 523       }
 524    }
 525
 526    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 527       brw_update_dirty_count(mesa_bits, state->mesa);
 528       brw_update_dirty_count(brw_bits, state->brw);
 529       brw_update_dirty_count(cache_bits, state->cache);
 530       if (dirty_count++ % 1000 == 0) {
 531          brw_print_dirty_count(mesa_bits);
 532          brw_print_dirty_count(brw_bits);
 533          brw_print_dirty_count(cache_bits);
 534          fprintf(stderr, "\n");
 535       }
 536    }
 537
 538    memset(state, 0, sizeof(*state));
 539 }