src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog, /* must do before GS prog, state base address. */
  51    &brw_gs_prog, /* must do before state base address */
  52    &brw_clip_prog, /* must do before state base address */
  53    &brw_sf_prog, /* must do before state base address */
  54    &brw_wm_prog, /* must do before state base address */
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
  67    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
  68
  69    &brw_vs_surfaces,            /* must do before unit */
  70    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
  71    &brw_wm_surfaces,            /* must do before samplers and unit */
  72    &brw_wm_binding_table,
  73    &brw_wm_samplers,
  74
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invarient_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_check_fallback,
 111
 112    &brw_wm_input_sizes,
 113    &brw_vs_prog, /* must do before state base address */
 114    &brw_gs_prog, /* must do before state base address */
 115    &brw_wm_prog, /* must do before state base address */
 116
 117    &gen6_clip_vp,
 118    &gen6_sf_vp,
 119
 120    /* Command packets: */
 121    &brw_invarient_state,
 122
 123    /* must do before binding table pointers, cc state ptrs */
 124    &brw_state_base_address,
 125
 126    &brw_cc_vp,
 127    &gen6_viewport_state,        /* must do after *_vp stages */
 128
 129    &gen6_urb,
 130    &gen6_blend_state,           /* must do before cc unit */
 131    &gen6_color_calc_state,      /* must do before cc unit */
 132    &gen6_depth_stencil_state,   /* must do before cc unit */
 133    &gen6_cc_state_pointers,
 134
 135    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 136    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 137    &gen6_vs_constants, /* Before vs_state */
 138    &gen6_wm_constants, /* Before wm_state */
 139
 140    &brw_vs_surfaces,            /* must do before unit */
 141    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 142    &brw_wm_surfaces,            /* must do before samplers and unit */
 143    &brw_wm_binding_table,
 144
 145    &brw_wm_samplers,
 146    &gen6_sampler_state,
 147
 148    &gen6_vs_state,
 149    &gen6_gs_state,
 150    &gen6_clip_state,
 151    &gen6_sf_state,
 152    &gen6_wm_state,
 153
 154    &gen6_scissor_state,
 155
 156    &gen6_binding_table_pointers,
 157
 158    &brw_depthbuffer,
 159
 160    &brw_polygon_stipple,
 161    &brw_polygon_stipple_offset,
 162
 163    &brw_line_stipple,
 164    &brw_aa_line_parameters,
 165
 166    &brw_drawing_rect,
 167
 168    &brw_indices,
 169    &brw_index_buffer,
 170    &brw_vertices,
 171 };
 172
 173 const struct brw_tracked_state *gen7_atoms[] =
 174 {
 175    &brw_check_fallback,
 176
 177    &brw_wm_input_sizes,
 178    &brw_vs_prog,
 179    &brw_gs_prog,
 180    &brw_wm_prog,
 181
 182    /* Command packets: */
 183    &brw_invarient_state,
 184
 185    /* must do before binding table pointers, cc state ptrs */
 186    &brw_state_base_address,
 187
 188    &brw_cc_vp,
 189    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 190    &gen7_sf_clip_viewport,
 191
 192    &gen7_urb,
 193    &gen6_blend_state,           /* must do before cc unit */
 194    &gen6_color_calc_state,      /* must do before cc unit */
 195    &gen6_depth_stencil_state,   /* must do before cc unit */
 196    &gen7_blend_state_pointer,
 197    &gen7_cc_state_pointer,
 198    &gen7_depth_stencil_state_pointer,
 199
 200    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 201    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 202    &gen6_vs_constants, /* Before vs_state */
 203    &gen6_wm_constants, /* Before wm_surfaces and constant_buffer */
 204
 205    &brw_vs_surfaces,            /* must do before unit */
 206    &gen7_wm_constant_surface,   /* must do before wm surfaces/bind bo */
 207    &gen7_wm_surfaces,           /* must do before samplers and unit */
 208    &brw_wm_binding_table,
 209
 210    &gen7_samplers,
 211
 212    &gen7_disable_stages,
 213    &gen7_vs_state,
 214    &gen7_clip_state,
 215    &gen7_sbe_state,
 216    &gen7_sf_state,
 217    &gen7_wm_state,
 218    &gen7_ps_state,
 219
 220    &gen6_scissor_state,
 221
 222    &gen7_depthbuffer,
 223
 224    &brw_polygon_stipple,
 225    &brw_polygon_stipple_offset,
 226
 227    &brw_line_stipple,
 228    &brw_aa_line_parameters,
 229
 230    &brw_drawing_rect,
 231
 232    &brw_indices,
 233    &brw_index_buffer,
 234    &brw_vertices,
 235 };
 236
 237
 238 void brw_init_state( struct brw_context *brw )
 239 {
 240    const struct brw_tracked_state **atoms;
 241    int num_atoms;
 242
 243    brw_init_caches(brw);
 244
 245    if (brw->intel.gen >= 7) {
 246       atoms = gen7_atoms;
 247       num_atoms = ARRAY_SIZE(gen7_atoms);
 248    } else if (brw->intel.gen == 6) {
 249       atoms = gen6_atoms;
 250       num_atoms = ARRAY_SIZE(gen6_atoms);
 251    } else {
 252       atoms = gen4_atoms;
 253       num_atoms = ARRAY_SIZE(gen4_atoms);
 254    }
 255
 256    while (num_atoms--) {
 257       assert((*atoms)->dirty.mesa |
 258              (*atoms)->dirty.brw |
 259              (*atoms)->dirty.cache);
 260
 261       if ((*atoms)->prepare)
 262          brw->prepare_atoms[brw->num_prepare_atoms++] = **atoms;
 263       if ((*atoms)->emit)
 264          brw->emit_atoms[brw->num_emit_atoms++] = **atoms;
 265       atoms++;
 266    }
 267    assert(brw->num_emit_atoms <= ARRAY_SIZE(brw->emit_atoms));
 268    assert(brw->num_prepare_atoms <= ARRAY_SIZE(brw->prepare_atoms));
 269 }
 270
 271
 272 void brw_destroy_state( struct brw_context *brw )
 273 {
 274    brw_destroy_caches(brw);
 275 }
 276
 277 /***********************************************************************
 278  */
 279
 280 static GLuint check_state( const struct brw_state_flags *a,
 281                            const struct brw_state_flags *b )
 282 {
 283    return ((a->mesa & b->mesa) |
 284            (a->brw & b->brw) |
 285            (a->cache & b->cache)) != 0;
 286 }
 287
 288 static void accumulate_state( struct brw_state_flags *a,
 289                               const struct brw_state_flags *b )
 290 {
 291    a->mesa |= b->mesa;
 292    a->brw |= b->brw;
 293    a->cache |= b->cache;
 294 }
 295
 296
 297 static void xor_states( struct brw_state_flags *result,
 298                              const struct brw_state_flags *a,
 299                               const struct brw_state_flags *b )
 300 {
 301    result->mesa = a->mesa ^ b->mesa;
 302    result->brw = a->brw ^ b->brw;
 303    result->cache = a->cache ^ b->cache;
 304 }
 305
 306 struct dirty_bit_map {
 307    uint32_t bit;
 308    char *name;
 309    uint32_t count;
 310 };
 311
 312 #define DEFINE_BIT(name) {name, #name, 0}
 313
 314 static struct dirty_bit_map mesa_bits[] = {
 315    DEFINE_BIT(_NEW_MODELVIEW),
 316    DEFINE_BIT(_NEW_PROJECTION),
 317    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 318    DEFINE_BIT(_NEW_COLOR),
 319    DEFINE_BIT(_NEW_DEPTH),
 320    DEFINE_BIT(_NEW_EVAL),
 321    DEFINE_BIT(_NEW_FOG),
 322    DEFINE_BIT(_NEW_HINT),
 323    DEFINE_BIT(_NEW_LIGHT),
 324    DEFINE_BIT(_NEW_LINE),
 325    DEFINE_BIT(_NEW_PIXEL),
 326    DEFINE_BIT(_NEW_POINT),
 327    DEFINE_BIT(_NEW_POLYGON),
 328    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 329    DEFINE_BIT(_NEW_SCISSOR),
 330    DEFINE_BIT(_NEW_STENCIL),
 331    DEFINE_BIT(_NEW_TEXTURE),
 332    DEFINE_BIT(_NEW_TRANSFORM),
 333    DEFINE_BIT(_NEW_VIEWPORT),
 334    DEFINE_BIT(_NEW_PACKUNPACK),
 335    DEFINE_BIT(_NEW_ARRAY),
 336    DEFINE_BIT(_NEW_RENDERMODE),
 337    DEFINE_BIT(_NEW_BUFFERS),
 338    DEFINE_BIT(_NEW_MULTISAMPLE),
 339    DEFINE_BIT(_NEW_TRACK_MATRIX),
 340    DEFINE_BIT(_NEW_PROGRAM),
 341    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 342    {0, 0, 0}
 343 };
 344
 345 static struct dirty_bit_map brw_bits[] = {
 346    DEFINE_BIT(BRW_NEW_URB_FENCE),
 347    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 348    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 349    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 350    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 351    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 352    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 353    DEFINE_BIT(BRW_NEW_CONTEXT),
 354    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 355    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 356    DEFINE_BIT(BRW_NEW_PSP),
 357    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 358    DEFINE_BIT(BRW_NEW_INDICES),
 359    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 360    DEFINE_BIT(BRW_NEW_VERTICES),
 361    DEFINE_BIT(BRW_NEW_BATCH),
 362    DEFINE_BIT(BRW_NEW_NR_WM_SURFACES),
 363    DEFINE_BIT(BRW_NEW_NR_VS_SURFACES),
 364    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 365    DEFINE_BIT(BRW_NEW_WM_CONSTBUF),
 366    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 367    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 368    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 369    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 370    {0, 0, 0}
 371 };
 372
 373 static struct dirty_bit_map cache_bits[] = {
 374    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 375    DEFINE_BIT(CACHE_NEW_CC_VP),
 376    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 377    DEFINE_BIT(CACHE_NEW_WM_PROG),
 378    DEFINE_BIT(CACHE_NEW_SAMPLER),
 379    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 380    DEFINE_BIT(CACHE_NEW_SF_PROG),
 381    DEFINE_BIT(CACHE_NEW_SF_VP),
 382    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 383    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 384    DEFINE_BIT(CACHE_NEW_VS_PROG),
 385    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 386    DEFINE_BIT(CACHE_NEW_GS_PROG),
 387    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 388    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 389    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 390    {0, 0, 0}
 391 };
 392
 393
 394 static void
 395 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 396 {
 397    int i;
 398
 399    for (i = 0; i < 32; i++) {
 400       if (bit_map[i].bit == 0)
 401          return;
 402
 403       if (bit_map[i].bit & bits)
 404          bit_map[i].count++;
 405    }
 406 }
 407
 408 static void
 409 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 410 {
 411    int i;
 412
 413    for (i = 0; i < 32; i++) {
 414       if (bit_map[i].bit == 0)
 415          return;
 416
 417       fprintf(stderr, "0x%08x: %12d (%s)\n",
 418               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 419    }
 420 }
 421
 422 /***********************************************************************
 423  * Emit all state:
 424  */
 425 void brw_validate_state( struct brw_context *brw )
 426 {
 427    struct gl_context *ctx = &brw->intel.ctx;
 428    struct intel_context *intel = &brw->intel;
 429    struct brw_state_flags *state = &brw->state.dirty;
 430    const struct brw_tracked_state *atoms = brw->prepare_atoms;
 431    int num_atoms = brw->num_prepare_atoms;
 432    GLuint i;
 433
 434    state->mesa |= brw->intel.NewGLState;
 435    brw->intel.NewGLState = 0;
 436
 437    if (brw->emit_state_always) {
 438       state->mesa |= ~0;
 439       state->brw |= ~0;
 440       state->cache |= ~0;
 441    }
 442
 443    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 444       brw->fragment_program = ctx->FragmentProgram._Current;
 445       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 446    }
 447
 448    if (brw->vertex_program != ctx->VertexProgram._Current) {
 449       brw->vertex_program = ctx->VertexProgram._Current;
 450       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 451    }
 452
 453    if ((state->mesa | state->cache | state->brw) == 0)
 454       return;
 455
 456    brw->intel.Fallback = false; /* boolean, not bitfield */
 457
 458    /* do prepare stage for all atoms */
 459    for (i = 0; i < num_atoms; i++) {
 460       const struct brw_tracked_state *atom = &atoms[i];
 461
 462       if (check_state(state, &atom->dirty)) {
 463          atom->prepare(brw);
 464
 465          if (brw->intel.Fallback)
 466             break;
 467       }
 468    }
 469
 470    intel_check_front_buffer_rendering(intel);
 471
 472    /* Make sure that the textures which are referenced by the current
 473     * brw fragment program are actually present/valid.
 474     * If this fails, we can experience GPU lock-ups.
 475     */
 476    {
 477       const struct brw_fragment_program *fp;
 478       fp = brw_fragment_program_const(brw->fragment_program);
 479       if (fp) {
 480          assert((fp->tex_units_used & ctx->Texture._EnabledUnits)
 481                 == fp->tex_units_used);
 482       }
 483    }
 484 }
 485
 486
 487 void brw_upload_state(struct brw_context *brw)
 488 {
 489    struct brw_state_flags *state = &brw->state.dirty;
 490    const struct brw_tracked_state *atoms = brw->emit_atoms;
 491    int num_atoms = brw->num_emit_atoms;
 492    int i;
 493    static int dirty_count = 0;
 494
 495    if (unlikely(INTEL_DEBUG)) {
 496       /* Debug version which enforces various sanity checks on the
 497        * state flags which are generated and checked to help ensure
 498        * state atoms are ordered correctly in the list.
 499        */
 500       struct brw_state_flags examined, prev;
 501       memset(&examined, 0, sizeof(examined));
 502       prev = *state;
 503
 504       for (i = 0; i < num_atoms; i++) {
 505          const struct brw_tracked_state *atom = &atoms[i];
 506          struct brw_state_flags generated;
 507
 508          if (brw->intel.Fallback)
 509             break;
 510
 511          if (check_state(state, &atom->dirty)) {
 512             atom->emit(brw);
 513          }
 514
 515          accumulate_state(&examined, &atom->dirty);
 516
 517          /* generated = (prev ^ state)
 518           * if (examined & generated)
 519           *     fail;
 520           */
 521          xor_states(&generated, &prev, state);
 522          assert(!check_state(&examined, &generated));
 523          prev = *state;
 524       }
 525    }
 526    else {
 527       for (i = 0; i < num_atoms; i++) {
 528          const struct brw_tracked_state *atom = &atoms[i];
 529
 530          if (brw->intel.Fallback)
 531             break;
 532
 533          if (check_state(state, &atom->dirty)) {
 534             atom->emit(brw);
 535          }
 536       }
 537    }
 538
 539    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 540       brw_update_dirty_count(mesa_bits, state->mesa);
 541       brw_update_dirty_count(brw_bits, state->brw);
 542       brw_update_dirty_count(cache_bits, state->cache);
 543       if (dirty_count++ % 1000 == 0) {
 544          brw_print_dirty_count(mesa_bits, state->mesa);
 545          brw_print_dirty_count(brw_bits, state->brw);
 546          brw_print_dirty_count(cache_bits, state->cache);
 547          fprintf(stderr, "\n");
 548       }
 549    }
 550
 551    if (!brw->intel.Fallback)
 552       memset(state, 0, sizeof(*state));
 553 }