src/mesa/drivers/dri/i965/brw_structs.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #ifndef BRW_STRUCTS_H
  34 #define BRW_STRUCTS_H
  35
  36 struct brw_urb_fence
  37 {
  38    struct
  39    {
  40       unsigned length:8;
  41       unsigned vs_realloc:1;
  42       unsigned gs_realloc:1;
  43       unsigned clp_realloc:1;
  44       unsigned sf_realloc:1;
  45       unsigned vfe_realloc:1;
  46       unsigned cs_realloc:1;
  47       unsigned pad:2;
  48       unsigned opcode:16;
  49    } header;
  50
  51    struct
  52    {
  53       unsigned vs_fence:10;
  54       unsigned gs_fence:10;
  55       unsigned clp_fence:10;
  56       unsigned pad:2;
  57    } bits0;
  58
  59    struct
  60    {
  61       unsigned sf_fence:10;
  62       unsigned vf_fence:10;
  63       unsigned cs_fence:11;
  64       unsigned pad:1;
  65    } bits1;
  66 };
  67
  68 /* State structs for the various fixed function units:
  69  */
  70
  71
  72 struct thread0
  73 {
  74    unsigned pad0:1;
  75    unsigned grf_reg_count:3;
  76    unsigned pad1:2;
  77    unsigned kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
  78 };
  79
  80 struct thread1
  81 {
  82    unsigned ext_halt_exception_enable:1;
  83    unsigned sw_exception_enable:1;
  84    unsigned mask_stack_exception_enable:1;
  85    unsigned timeout_exception_enable:1;
  86    unsigned illegal_op_exception_enable:1;
  87    unsigned pad0:3;
  88    unsigned depth_coef_urb_read_offset:6;       /* WM only */
  89    unsigned pad1:2;
  90    unsigned floating_point_mode:1;
  91    unsigned thread_priority:1;
  92    unsigned binding_table_entry_count:8;
  93    unsigned pad3:5;
  94    unsigned single_program_flow:1;
  95 };
  96
  97 struct thread2
  98 {
  99    unsigned per_thread_scratch_space:4;
 100    unsigned pad0:6;
 101    unsigned scratch_space_base_pointer:22;
 102 };
 103
 104
 105 struct thread3
 106 {
 107    unsigned dispatch_grf_start_reg:4;
 108    unsigned urb_entry_read_offset:6;
 109    unsigned pad0:1;
 110    unsigned urb_entry_read_length:6;
 111    unsigned pad1:1;
 112    unsigned const_urb_entry_read_offset:6;
 113    unsigned pad2:1;
 114    unsigned const_urb_entry_read_length:6;
 115    unsigned pad3:1;
 116 };
 117
 118
 119
 120 struct brw_clip_unit_state
 121 {
 122    struct thread0 thread0;
 123    struct
 124    {
 125       unsigned pad0:7;
 126       unsigned sw_exception_enable:1;
 127       unsigned pad1:3;
 128       unsigned mask_stack_exception_enable:1;
 129       unsigned pad2:1;
 130       unsigned illegal_op_exception_enable:1;
 131       unsigned pad3:2;
 132       unsigned floating_point_mode:1;
 133       unsigned thread_priority:1;
 134       unsigned binding_table_entry_count:8;
 135       unsigned pad4:5;
 136       unsigned single_program_flow:1;
 137    } thread1;
 138
 139    struct thread2 thread2;
 140    struct thread3 thread3;
 141
 142    struct
 143    {
 144       unsigned pad0:9;
 145       unsigned gs_output_stats:1; /* not always */
 146       unsigned stats_enable:1;
 147       unsigned nr_urb_entries:7;
 148       unsigned pad1:1;
 149       unsigned urb_entry_allocation_size:5;
 150       unsigned pad2:1;
 151       unsigned max_threads:5;   /* may be less */
 152       unsigned pad3:2;
 153    } thread4;
 154
 155    struct
 156    {
 157       unsigned pad0:13;
 158       unsigned clip_mode:3;
 159       unsigned userclip_enable_flags:8;
 160       unsigned userclip_must_clip:1;
 161       unsigned negative_w_clip_test:1;
 162       unsigned guard_band_enable:1;
 163       unsigned viewport_z_clip_enable:1;
 164       unsigned viewport_xy_clip_enable:1;
 165       unsigned vertex_position_space:1;
 166       unsigned api_mode:1;
 167       unsigned pad2:1;
 168    } clip5;
 169
 170    struct
 171    {
 172       unsigned pad0:5;
 173       unsigned clipper_viewport_state_ptr:27;
 174    } clip6;
 175
 176
 177    float viewport_xmin;
 178    float viewport_xmax;
 179    float viewport_ymin;
 180    float viewport_ymax;
 181 };
 182
 183 struct gen6_blend_state
 184 {
 185    struct {
 186       unsigned dest_blend_factor:5;
 187       unsigned source_blend_factor:5;
 188       unsigned pad3:1;
 189       unsigned blend_func:3;
 190       unsigned pad2:1;
 191       unsigned ia_dest_blend_factor:5;
 192       unsigned ia_source_blend_factor:5;
 193       unsigned pad1:1;
 194       unsigned ia_blend_func:3;
 195       unsigned pad0:1;
 196       unsigned ia_blend_enable:1;
 197       unsigned blend_enable:1;
 198    } blend0;
 199
 200    struct {
 201       unsigned post_blend_clamp_enable:1;
 202       unsigned pre_blend_clamp_enable:1;
 203       unsigned clamp_range:2;
 204       unsigned pad0:4;
 205       unsigned x_dither_offset:2;
 206       unsigned y_dither_offset:2;
 207       unsigned dither_enable:1;
 208       unsigned alpha_test_func:3;
 209       unsigned alpha_test_enable:1;
 210       unsigned pad1:1;
 211       unsigned logic_op_func:4;
 212       unsigned logic_op_enable:1;
 213       unsigned pad2:1;
 214       unsigned write_disable_b:1;
 215       unsigned write_disable_g:1;
 216       unsigned write_disable_r:1;
 217       unsigned write_disable_a:1;
 218       unsigned pad3:1;
 219       unsigned alpha_to_coverage_dither:1;
 220       unsigned alpha_to_one:1;
 221       unsigned alpha_to_coverage:1;
 222    } blend1;
 223 };
 224
 225 struct gen6_color_calc_state
 226 {
 227    struct {
 228       unsigned alpha_test_format:1;
 229       unsigned pad0:14;
 230       unsigned round_disable:1;
 231       unsigned bf_stencil_ref:8;
 232       unsigned stencil_ref:8;
 233    } cc0;
 234
 235    union {
 236       float alpha_ref_f;
 237       struct {
 238          unsigned ui:8;
 239          unsigned pad0:24;
 240       } alpha_ref_fi;
 241    } cc1;
 242
 243    float constant_r;
 244    float constant_g;
 245    float constant_b;
 246    float constant_a;
 247 };
 248
 249 struct gen6_depth_stencil_state
 250 {
 251    struct {
 252       unsigned pad0:3;
 253       unsigned bf_stencil_pass_depth_pass_op:3;
 254       unsigned bf_stencil_pass_depth_fail_op:3;
 255       unsigned bf_stencil_fail_op:3;
 256       unsigned bf_stencil_func:3;
 257       unsigned bf_stencil_enable:1;
 258       unsigned pad1:2;
 259       unsigned stencil_write_enable:1;
 260       unsigned stencil_pass_depth_pass_op:3;
 261       unsigned stencil_pass_depth_fail_op:3;
 262       unsigned stencil_fail_op:3;
 263       unsigned stencil_func:3;
 264       unsigned stencil_enable:1;
 265    } ds0;
 266
 267    struct {
 268       unsigned bf_stencil_write_mask:8;
 269       unsigned bf_stencil_test_mask:8;
 270       unsigned stencil_write_mask:8;
 271       unsigned stencil_test_mask:8;
 272    } ds1;
 273
 274    struct {
 275       unsigned pad0:26;
 276       unsigned depth_write_enable:1;
 277       unsigned depth_test_func:3;
 278       unsigned pad1:1;
 279       unsigned depth_test_enable:1;
 280    } ds2;
 281 };
 282
 283 struct brw_cc_unit_state
 284 {
 285    struct
 286    {
 287       unsigned pad0:3;
 288       unsigned bf_stencil_pass_depth_pass_op:3;
 289       unsigned bf_stencil_pass_depth_fail_op:3;
 290       unsigned bf_stencil_fail_op:3;
 291       unsigned bf_stencil_func:3;
 292       unsigned bf_stencil_enable:1;
 293       unsigned pad1:2;
 294       unsigned stencil_write_enable:1;
 295       unsigned stencil_pass_depth_pass_op:3;
 296       unsigned stencil_pass_depth_fail_op:3;
 297       unsigned stencil_fail_op:3;
 298       unsigned stencil_func:3;
 299       unsigned stencil_enable:1;
 300    } cc0;
 301
 302
 303    struct
 304    {
 305       unsigned bf_stencil_ref:8;
 306       unsigned stencil_write_mask:8;
 307       unsigned stencil_test_mask:8;
 308       unsigned stencil_ref:8;
 309    } cc1;
 310
 311
 312    struct
 313    {
 314       unsigned logicop_enable:1;
 315       unsigned pad0:10;
 316       unsigned depth_write_enable:1;
 317       unsigned depth_test_function:3;
 318       unsigned depth_test:1;
 319       unsigned bf_stencil_write_mask:8;
 320       unsigned bf_stencil_test_mask:8;
 321    } cc2;
 322
 323
 324    struct
 325    {
 326       unsigned pad0:8;
 327       unsigned alpha_test_func:3;
 328       unsigned alpha_test:1;
 329       unsigned blend_enable:1;
 330       unsigned ia_blend_enable:1;
 331       unsigned pad1:1;
 332       unsigned alpha_test_format:1;
 333       unsigned pad2:16;
 334    } cc3;
 335
 336    struct
 337    {
 338       unsigned pad0:5;
 339       unsigned cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 340    } cc4;
 341
 342    struct
 343    {
 344       unsigned pad0:2;
 345       unsigned ia_dest_blend_factor:5;
 346       unsigned ia_src_blend_factor:5;
 347       unsigned ia_blend_function:3;
 348       unsigned statistics_enable:1;
 349       unsigned logicop_func:4;
 350       unsigned pad1:11;
 351       unsigned dither_enable:1;
 352    } cc5;
 353
 354    struct
 355    {
 356       unsigned clamp_post_alpha_blend:1;
 357       unsigned clamp_pre_alpha_blend:1;
 358       unsigned clamp_range:2;
 359       unsigned pad0:11;
 360       unsigned y_dither_offset:2;
 361       unsigned x_dither_offset:2;
 362       unsigned dest_blend_factor:5;
 363       unsigned src_blend_factor:5;
 364       unsigned blend_function:3;
 365    } cc6;
 366
 367    struct {
 368       union {
 369          float f;
 370          uint8_t ub[4];
 371       } alpha_ref;
 372    } cc7;
 373 };
 374
 375 struct brw_sf_unit_state
 376 {
 377    struct thread0 thread0;
 378    struct thread1 thread1;
 379    struct thread2 thread2;
 380    struct thread3 thread3;
 381
 382    struct
 383    {
 384       unsigned pad0:10;
 385       unsigned stats_enable:1;
 386       unsigned nr_urb_entries:7;
 387       unsigned pad1:1;
 388       unsigned urb_entry_allocation_size:5;
 389       unsigned pad2:1;
 390       unsigned max_threads:6;
 391       unsigned pad3:1;
 392    } thread4;
 393
 394    struct
 395    {
 396       unsigned front_winding:1;
 397       unsigned viewport_transform:1;
 398       unsigned pad0:3;
 399       unsigned sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 400    } sf5;
 401
 402    struct
 403    {
 404       unsigned pad0:9;
 405       unsigned dest_org_vbias:4;
 406       unsigned dest_org_hbias:4;
 407       unsigned scissor:1;
 408       unsigned disable_2x2_trifilter:1;
 409       unsigned disable_zero_pix_trifilter:1;
 410       unsigned point_rast_rule:2;
 411       unsigned line_endcap_aa_region_width:2;
 412       unsigned line_width:4;
 413       unsigned fast_scissor_disable:1;
 414       unsigned cull_mode:2;
 415       unsigned aa_enable:1;
 416    } sf6;
 417
 418    struct
 419    {
 420       unsigned point_size:11;
 421       unsigned use_point_size_state:1;
 422       unsigned subpixel_precision:1;
 423       unsigned sprite_point:1;
 424       unsigned pad0:10;
 425       unsigned aa_line_distance_mode:1;
 426       unsigned trifan_pv:2;
 427       unsigned linestrip_pv:2;
 428       unsigned tristrip_pv:2;
 429       unsigned line_last_pixel_enable:1;
 430    } sf7;
 431
 432 };
 433
 434 struct gen6_scissor_rect
 435 {
 436    unsigned xmin:16;
 437    unsigned ymin:16;
 438    unsigned xmax:16;
 439    unsigned ymax:16;
 440 };
 441
 442 struct brw_gs_unit_state
 443 {
 444    struct thread0 thread0;
 445    struct thread1 thread1;
 446    struct thread2 thread2;
 447    struct thread3 thread3;
 448
 449    struct
 450    {
 451       unsigned pad0:8;
 452       unsigned rendering_enable:1; /* for Ironlake */
 453       unsigned pad4:1;
 454       unsigned stats_enable:1;
 455       unsigned nr_urb_entries:7;
 456       unsigned pad1:1;
 457       unsigned urb_entry_allocation_size:5;
 458       unsigned pad2:1;
 459       unsigned max_threads:5;
 460       unsigned pad3:2;
 461    } thread4;
 462
 463    struct
 464    {
 465       unsigned sampler_count:3;
 466       unsigned pad0:2;
 467       unsigned sampler_state_pointer:27;
 468    } gs5;
 469
 470
 471    struct
 472    {
 473       unsigned max_vp_index:4;
 474       unsigned pad0:12;
 475       unsigned svbi_post_inc_value:10;
 476       unsigned pad1:1;
 477       unsigned svbi_post_inc_enable:1;
 478       unsigned svbi_payload:1;
 479       unsigned discard_adjaceny:1;
 480       unsigned reorder_enable:1;
 481       unsigned pad2:1;
 482    } gs6;
 483 };
 484
 485
 486 struct brw_vs_unit_state
 487 {
 488    struct thread0 thread0;
 489    struct thread1 thread1;
 490    struct thread2 thread2;
 491    struct thread3 thread3;
 492
 493    struct
 494    {
 495       unsigned pad0:10;
 496       unsigned stats_enable:1;
 497       unsigned nr_urb_entries:7;
 498       unsigned pad1:1;
 499       unsigned urb_entry_allocation_size:5;
 500       unsigned pad2:1;
 501       unsigned max_threads:6;
 502       unsigned pad3:1;
 503    } thread4;
 504
 505    struct
 506    {
 507       unsigned sampler_count:3;
 508       unsigned pad0:2;
 509       unsigned sampler_state_pointer:27;
 510    } vs5;
 511
 512    struct
 513    {
 514       unsigned vs_enable:1;
 515       unsigned vert_cache_disable:1;
 516       unsigned pad0:30;
 517    } vs6;
 518 };
 519
 520
 521 struct brw_wm_unit_state
 522 {
 523    struct thread0 thread0;
 524    struct thread1 thread1;
 525    struct thread2 thread2;
 526    struct thread3 thread3;
 527
 528    struct {
 529       unsigned stats_enable:1;
 530       unsigned depth_buffer_clear:1;
 531       unsigned sampler_count:3;
 532       unsigned sampler_state_pointer:27;
 533    } wm4;
 534
 535    struct
 536    {
 537       unsigned enable_8_pix:1;
 538       unsigned enable_16_pix:1;
 539       unsigned enable_32_pix:1;
 540       unsigned enable_con_32_pix:1;
 541       unsigned enable_con_64_pix:1;
 542       unsigned pad0:1;
 543
 544       /* These next four bits are for Ironlake+ */
 545       unsigned fast_span_coverage_enable:1;
 546       unsigned depth_buffer_clear:1;
 547       unsigned depth_buffer_resolve_enable:1;
 548       unsigned hierarchical_depth_buffer_resolve_enable:1;
 549
 550       unsigned legacy_global_depth_bias:1;
 551       unsigned line_stipple:1;
 552       unsigned depth_offset:1;
 553       unsigned polygon_stipple:1;
 554       unsigned line_aa_region_width:2;
 555       unsigned line_endcap_aa_region_width:2;
 556       unsigned early_depth_test:1;
 557       unsigned thread_dispatch_enable:1;
 558       unsigned program_uses_depth:1;
 559       unsigned program_computes_depth:1;
 560       unsigned program_uses_killpixel:1;
 561       unsigned legacy_line_rast: 1;
 562       unsigned transposed_urb_read_enable:1;
 563       unsigned max_threads:7;
 564    } wm5;
 565
 566    float global_depth_offset_constant;
 567    float global_depth_offset_scale;
 568
 569    /* for Ironlake only */
 570    struct {
 571       unsigned pad0:1;
 572       unsigned grf_reg_count_1:3;
 573       unsigned pad1:2;
 574       unsigned kernel_start_pointer_1:26;
 575    } wm8;
 576
 577    struct {
 578       unsigned pad0:1;
 579       unsigned grf_reg_count_2:3;
 580       unsigned pad1:2;
 581       unsigned kernel_start_pointer_2:26;
 582    } wm9;
 583
 584    struct {
 585       unsigned pad0:1;
 586       unsigned grf_reg_count_3:3;
 587       unsigned pad1:2;
 588       unsigned kernel_start_pointer_3:26;
 589    } wm10;
 590 };
 591
 592 struct gen5_sampler_default_color {
 593    uint8_t ub[4];
 594    float f[4];
 595    uint16_t hf[4];
 596    uint16_t us[4];
 597    int16_t s[4];
 598    uint8_t b[4];
 599 };
 600
 601 struct brw_clipper_viewport
 602 {
 603    float xmin;
 604    float xmax;
 605    float ymin;
 606    float ymax;
 607 };
 608
 609 struct brw_cc_viewport
 610 {
 611    float min_depth;
 612    float max_depth;
 613 };
 614
 615 struct brw_sf_viewport
 616 {
 617    struct {
 618       float m00;
 619       float m11;
 620       float m22;
 621       float m30;
 622       float m31;
 623       float m32;
 624    } viewport;
 625
 626    /* scissor coordinates are inclusive */
 627    struct {
 628       int16_t xmin;
 629       int16_t ymin;
 630       int16_t xmax;
 631       int16_t ymax;
 632    } scissor;
 633 };
 634
 635 struct gen6_sf_viewport {
 636    float m00;
 637    float m11;
 638    float m22;
 639    float m30;
 640    float m31;
 641    float m32;
 642
 643    unsigned pad0[2];
 644 };
 645
 646 struct gen7_sf_clip_viewport {
 647    struct {
 648       float m00;
 649       float m11;
 650       float m22;
 651       float m30;
 652       float m31;
 653       float m32;
 654    } viewport;
 655
 656    unsigned pad0[2];
 657
 658    struct {
 659       float xmin;
 660       float xmax;
 661       float ymin;
 662       float ymax;
 663    } guardband;
 664
 665    float pad1[4];
 666 };
 667
 668 #endif