2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
37 /** Number of general purpose registers (VS, WM, etc) */
38 #define BRW_MAX_GRF 128
40 /** Number of message register file registers */
41 #define BRW_MAX_MRF 16
64 GLuint notify_enable
:1;
66 GLuint wc_flush_enable
:1;
67 GLuint depth_stall_enable
:1;
75 GLuint dest_addr_type
:1;
84 struct brw_3d_primitive
95 GLuint verts_per_instance
;
96 GLuint start_vert_location
;
97 GLuint instance_count
;
98 GLuint start_instance_location
;
99 GLuint base_vert_location
;
102 /* These seem to be passed around as function args, so it works out
103 * better to keep them as #defines:
105 #define BRW_FLUSH_READ_CACHE 0x1
106 #define BRW_FLUSH_STATE_CACHE 0x2
107 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
108 #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8
117 struct brw_vf_statistics
119 GLuint statistics_enable
:1;
126 struct brw_binding_table_pointers
128 struct header header
;
137 struct brw_blend_constant_color
139 struct header header
;
140 GLfloat blend_constant_color
[4];
144 struct brw_depthbuffer
146 union header_union header
;
153 GLuint software_tiled_rendering_mode
:2;
154 GLuint depth_offset_disable
:1;
156 GLuint tiled_surface
:1;
158 GLuint surface_type
:3;
163 GLuint dword2_base_addr
;
168 GLuint mipmap_layout
:1;
179 GLuint min_array_element
:11;
186 struct brw_depthbuffer_g4x
188 union header_union header
;
195 GLuint software_tiled_rendering_mode
:2;
196 GLuint depth_offset_disable
:1;
198 GLuint tiled_surface
:1;
200 GLuint surface_type
:3;
205 GLuint dword2_base_addr
;
210 GLuint mipmap_layout
:1;
221 GLuint min_array_element
:11;
233 } dword5
; /* NEW in Integrated Graphics Device */
238 struct header header
;
250 struct brw_global_depth_offset_clamp
252 struct header header
;
253 GLfloat depth_offset_clamp
;
256 struct brw_indexbuffer
262 GLuint index_format
:2;
263 GLuint cut_index_enable
:1;
275 /* NEW in Integrated Graphics Device */
276 struct brw_aa_line_parameters
278 struct header header
;
281 GLuint aa_coverage_slope
:8;
283 GLuint aa_coverage_bias
:8;
288 GLuint aa_coverage_endcap_slope
:8;
290 GLuint aa_coverage_endcap_bias
:8;
295 struct brw_line_stipple
297 struct header header
;
307 GLuint repeat_count
:9;
309 GLuint inverse_repeat_count
:16;
314 struct brw_pipelined_state_pointers
316 struct header header
;
320 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
327 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
334 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
340 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
346 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
352 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE. KW: check me! */
357 struct brw_polygon_stipple_offset
359 struct header header
;
371 struct brw_polygon_stipple
373 struct header header
;
379 struct brw_pipeline_select
383 GLuint pipeline_select
:1;
390 struct brw_pipe_control
395 GLuint notify_enable
:1;
396 GLuint texture_cache_flush_enable
:1;
397 GLuint indirect_state_pointers_disable
:1;
398 GLuint instruction_state_cache_flush_enable
:1;
399 GLuint write_cache_flush_enable
:1;
400 GLuint depth_stall_enable
:1;
401 GLuint post_sync_operation
:2;
409 GLuint dest_addr_type
:1;
425 GLuint clp_realloc
:1;
427 GLuint vfe_realloc
:1;
450 struct brw_cs_urb_state
452 struct header header
;
456 GLuint nr_urb_entries
:3;
458 GLuint urb_entry_size
:5;
463 struct brw_constant_buffer
475 GLuint buffer_length
:6;
476 GLuint buffer_address
:26;
480 struct brw_state_base_address
482 struct header header
;
486 GLuint modify_enable
:1;
488 GLuint general_state_address
:27;
493 GLuint modify_enable
:1;
495 GLuint surface_state_address
:27;
500 GLuint modify_enable
:1;
502 GLuint indirect_object_state_address
:27;
507 GLuint modify_enable
:1;
509 GLuint general_state_upper_bound
:20;
514 GLuint modify_enable
:1;
516 GLuint indirect_object_state_upper_bound
:20;
520 struct brw_state_prefetch
522 struct header header
;
526 GLuint prefetch_count
:3;
528 GLuint prefetch_pointer
:26;
532 struct brw_system_instruction_pointer
534 struct header header
;
539 GLuint system_instruction_pointer
:28;
546 /* State structs for the various fixed function units:
553 GLuint grf_reg_count
:3;
555 GLuint kernel_start_pointer
:26; /* Offset from GENERAL_STATE_BASE */
560 GLuint ext_halt_exception_enable
:1;
561 GLuint sw_exception_enable
:1;
562 GLuint mask_stack_exception_enable
:1;
563 GLuint timeout_exception_enable
:1;
564 GLuint illegal_op_exception_enable
:1;
566 GLuint depth_coef_urb_read_offset
:6; /* WM only */
568 GLuint floating_point_mode
:1;
569 GLuint thread_priority
:1;
570 GLuint binding_table_entry_count
:8;
572 GLuint single_program_flow
:1;
577 GLuint per_thread_scratch_space
:4;
579 GLuint scratch_space_base_pointer
:22;
585 GLuint dispatch_grf_start_reg
:4;
586 GLuint urb_entry_read_offset
:6;
588 GLuint urb_entry_read_length
:6;
590 GLuint const_urb_entry_read_offset
:6;
592 GLuint const_urb_entry_read_length
:6;
598 struct brw_clip_unit_state
600 struct thread0 thread0
;
604 GLuint sw_exception_enable
:1;
606 GLuint mask_stack_exception_enable
:1;
608 GLuint illegal_op_exception_enable
:1;
610 GLuint floating_point_mode
:1;
611 GLuint thread_priority
:1;
612 GLuint binding_table_entry_count
:8;
614 GLuint single_program_flow
:1;
617 struct thread2 thread2
;
618 struct thread3 thread3
;
623 GLuint gs_output_stats
:1; /* not always */
624 GLuint stats_enable
:1;
625 GLuint nr_urb_entries
:7;
627 GLuint urb_entry_allocation_size
:5;
629 GLuint max_threads
:5; /* may be less */
637 GLuint userclip_enable_flags
:8;
638 GLuint userclip_must_clip
:1;
639 GLuint negative_w_clip_test
:1;
640 GLuint guard_band_enable
:1;
641 GLuint viewport_z_clip_enable
:1;
642 GLuint viewport_xy_clip_enable
:1;
643 GLuint vertex_position_space
:1;
651 GLuint clipper_viewport_state_ptr
:27;
655 GLfloat viewport_xmin
;
656 GLfloat viewport_xmax
;
657 GLfloat viewport_ymin
;
658 GLfloat viewport_ymax
;
661 struct gen6_blend_state
664 GLuint dest_blend_factor
:5;
665 GLuint source_blend_factor
:5;
669 GLuint ia_dest_blend_factor
:5;
670 GLuint ia_source_blend_factor
:5;
672 GLuint ia_blend_func
:3;
674 GLuint ia_blend_enable
:1;
675 GLuint blend_enable
:1;
679 GLuint post_blend_clamp_enable
:1;
680 GLuint pre_blend_clamp_enable
:1;
681 GLuint clamp_range
:2;
683 GLuint x_dither_offset
:2;
684 GLuint y_dither_offset
:2;
685 GLuint dither_enable
:1;
686 GLuint alpha_test_func
:3;
687 GLuint alpha_test_enable
:1;
689 GLuint logic_op_func
:4;
690 GLuint logic_op_enable
:1;
692 GLuint write_disable_b
:1;
693 GLuint write_disable_g
:1;
694 GLuint write_disable_r
:1;
695 GLuint write_disable_a
:1;
697 GLuint alpha_to_coverage_dither
:1;
698 GLuint alpha_to_one
:1;
699 GLuint alpha_to_coverage
:1;
703 struct gen6_color_calc_state
706 GLuint alpha_test_format
:1;
708 GLuint round_disable
:1;
709 GLuint bf_stencil_ref
:8;
710 GLuint stencil_ref
:8;
727 struct gen6_depth_stencil_state
731 GLuint bf_stencil_pass_depth_pass_op
:3;
732 GLuint bf_stencil_pass_depth_fail_op
:3;
733 GLuint bf_stencil_fail_op
:3;
734 GLuint bf_stencil_func
:3;
735 GLuint bf_stencil_enable
:1;
737 GLuint stencil_write_enable
:1;
738 GLuint stencil_pass_depth_pass_op
:3;
739 GLuint stencil_pass_depth_fail_op
:3;
740 GLuint stencil_fail_op
:3;
741 GLuint stencil_func
:3;
742 GLuint stencil_enable
:1;
746 GLuint bf_stencil_write_mask
:8;
747 GLuint bf_stencil_test_mask
:8;
748 GLuint stencil_write_mask
:8;
749 GLuint stencil_test_mask
:8;
754 GLuint depth_write_enable
:1;
755 GLuint depth_test_func
:3;
757 GLuint depth_test_enable
:1;
761 struct brw_cc_unit_state
766 GLuint bf_stencil_pass_depth_pass_op
:3;
767 GLuint bf_stencil_pass_depth_fail_op
:3;
768 GLuint bf_stencil_fail_op
:3;
769 GLuint bf_stencil_func
:3;
770 GLuint bf_stencil_enable
:1;
772 GLuint stencil_write_enable
:1;
773 GLuint stencil_pass_depth_pass_op
:3;
774 GLuint stencil_pass_depth_fail_op
:3;
775 GLuint stencil_fail_op
:3;
776 GLuint stencil_func
:3;
777 GLuint stencil_enable
:1;
783 GLuint bf_stencil_ref
:8;
784 GLuint stencil_write_mask
:8;
785 GLuint stencil_test_mask
:8;
786 GLuint stencil_ref
:8;
792 GLuint logicop_enable
:1;
794 GLuint depth_write_enable
:1;
795 GLuint depth_test_function
:3;
797 GLuint bf_stencil_write_mask
:8;
798 GLuint bf_stencil_test_mask
:8;
805 GLuint alpha_test_func
:3;
807 GLuint blend_enable
:1;
808 GLuint ia_blend_enable
:1;
810 GLuint alpha_test_format
:1;
817 GLuint cc_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
823 GLuint ia_dest_blend_factor
:5;
824 GLuint ia_src_blend_factor
:5;
825 GLuint ia_blend_function
:3;
826 GLuint statistics_enable
:1;
827 GLuint logicop_func
:4;
829 GLuint dither_enable
:1;
834 GLuint clamp_post_alpha_blend
:1;
835 GLuint clamp_pre_alpha_blend
:1;
836 GLuint clamp_range
:2;
838 GLuint y_dither_offset
:2;
839 GLuint x_dither_offset
:2;
840 GLuint dest_blend_factor
:5;
841 GLuint src_blend_factor
:5;
842 GLuint blend_function
:3;
853 struct brw_sf_unit_state
855 struct thread0 thread0
;
856 struct thread1 thread1
;
857 struct thread2 thread2
;
858 struct thread3 thread3
;
863 GLuint stats_enable
:1;
864 GLuint nr_urb_entries
:7;
866 GLuint urb_entry_allocation_size
:5;
868 GLuint max_threads
:6;
874 GLuint front_winding
:1;
875 GLuint viewport_transform
:1;
877 GLuint sf_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
883 GLuint dest_org_vbias
:4;
884 GLuint dest_org_hbias
:4;
886 GLuint disable_2x2_trifilter
:1;
887 GLuint disable_zero_pix_trifilter
:1;
888 GLuint point_rast_rule
:2;
889 GLuint line_endcap_aa_region_width
:2;
891 GLuint fast_scissor_disable
:1;
898 GLuint point_size
:11;
899 GLuint use_point_size_state
:1;
900 GLuint subpixel_precision
:1;
901 GLuint sprite_point
:1;
903 GLuint aa_line_distance_mode
:1;
905 GLuint linestrip_pv
:2;
906 GLuint tristrip_pv
:2;
907 GLuint line_last_pixel_enable
:1;
912 struct gen6_scissor_rect
920 struct brw_gs_unit_state
922 struct thread0 thread0
;
923 struct thread1 thread1
;
924 struct thread2 thread2
;
925 struct thread3 thread3
;
930 GLuint rendering_enable
:1; /* for Ironlake */
932 GLuint stats_enable
:1;
933 GLuint nr_urb_entries
:7;
935 GLuint urb_entry_allocation_size
:5;
937 GLuint max_threads
:5;
943 GLuint sampler_count
:3;
945 GLuint sampler_state_pointer
:27;
951 GLuint max_vp_index
:4;
953 GLuint svbi_post_inc_value
:10;
955 GLuint svbi_post_inc_enable
:1;
956 GLuint svbi_payload
:1;
957 GLuint discard_adjaceny
:1;
958 GLuint reorder_enable
:1;
964 struct brw_vs_unit_state
966 struct thread0 thread0
;
967 struct thread1 thread1
;
968 struct thread2 thread2
;
969 struct thread3 thread3
;
974 GLuint stats_enable
:1;
975 GLuint nr_urb_entries
:7;
977 GLuint urb_entry_allocation_size
:5;
979 GLuint max_threads
:6;
985 GLuint sampler_count
:3;
987 GLuint sampler_state_pointer
:27;
993 GLuint vert_cache_disable
:1;
999 struct brw_wm_unit_state
1001 struct thread0 thread0
;
1002 struct thread1 thread1
;
1003 struct thread2 thread2
;
1004 struct thread3 thread3
;
1007 GLuint stats_enable
:1;
1008 GLuint depth_buffer_clear
:1;
1009 GLuint sampler_count
:3;
1010 GLuint sampler_state_pointer
:27;
1015 GLuint enable_8_pix
:1;
1016 GLuint enable_16_pix
:1;
1017 GLuint enable_32_pix
:1;
1018 GLuint enable_con_32_pix
:1;
1019 GLuint enable_con_64_pix
:1;
1022 /* These next four bits are for Ironlake+ */
1023 GLuint fast_span_coverage_enable
:1;
1024 GLuint depth_buffer_clear
:1;
1025 GLuint depth_buffer_resolve_enable
:1;
1026 GLuint hierarchical_depth_buffer_resolve_enable
:1;
1028 GLuint legacy_global_depth_bias
:1;
1029 GLuint line_stipple
:1;
1030 GLuint depth_offset
:1;
1031 GLuint polygon_stipple
:1;
1032 GLuint line_aa_region_width
:2;
1033 GLuint line_endcap_aa_region_width
:2;
1034 GLuint early_depth_test
:1;
1035 GLuint thread_dispatch_enable
:1;
1036 GLuint program_uses_depth
:1;
1037 GLuint program_computes_depth
:1;
1038 GLuint program_uses_killpixel
:1;
1039 GLuint legacy_line_rast
: 1;
1040 GLuint transposed_urb_read_enable
:1;
1041 GLuint max_threads
:7;
1044 GLfloat global_depth_offset_constant
;
1045 GLfloat global_depth_offset_scale
;
1047 /* for Ironlake only */
1050 GLuint grf_reg_count_1
:3;
1052 GLuint kernel_start_pointer_1
:26;
1057 GLuint grf_reg_count_2
:3;
1059 GLuint kernel_start_pointer_2
:26;
1064 GLuint grf_reg_count_3
:3;
1066 GLuint kernel_start_pointer_3
:26;
1070 struct brw_sampler_default_color
{
1074 struct gen5_sampler_default_color
{
1083 struct brw_sampler_state
1088 GLuint shadow_function
:3;
1090 GLuint min_filter
:3;
1091 GLuint mag_filter
:3;
1092 GLuint mip_filter
:2;
1093 GLuint base_level
:5;
1094 GLuint min_mag_neq
:1;
1095 GLuint lod_preclamp
:1;
1096 GLuint default_color_mode
:1;
1103 GLuint r_wrap_mode
:3;
1104 GLuint t_wrap_mode
:3;
1105 GLuint s_wrap_mode
:3;
1106 GLuint cube_control_mode
:1;
1116 GLuint default_color_pointer
:27;
1121 GLuint non_normalized_coord
:1;
1123 GLuint address_round
:6;
1125 GLuint chroma_key_mode
:1;
1126 GLuint chroma_key_index
:2;
1127 GLuint chroma_key_enable
:1;
1128 GLuint monochrome_filter_width
:3;
1129 GLuint monochrome_filter_height
:3;
1134 struct brw_clipper_viewport
1142 struct brw_cc_viewport
1148 struct brw_sf_viewport
1159 /* scissor coordinates are inclusive */
1168 struct gen6_sf_viewport
{
1177 /* Documented in the subsystem/shared-functions/sampler chapter...
1179 struct brw_surface_state
1182 GLuint cube_pos_z
:1;
1183 GLuint cube_neg_z
:1;
1184 GLuint cube_pos_y
:1;
1185 GLuint cube_neg_y
:1;
1186 GLuint cube_pos_x
:1;
1187 GLuint cube_neg_x
:1;
1189 /* Required on gen6 for surfaces accessed through render cache messages.
1191 GLuint render_cache_read_write
:1;
1192 /* Ironlake and newer: instead of replicating one of the texels */
1193 GLuint cube_corner_average
:1;
1194 GLuint mipmap_layout_mode
:1;
1195 GLuint vert_line_stride_ofs
:1;
1196 GLuint vert_line_stride
:1;
1197 GLuint color_blend
:1;
1198 GLuint writedisable_blue
:1;
1199 GLuint writedisable_green
:1;
1200 GLuint writedisable_red
:1;
1201 GLuint writedisable_alpha
:1;
1202 GLuint surface_format
:9; /**< BRW_SURFACEFORMAT_x */
1203 GLuint data_return_format
:1;
1205 GLuint surface_type
:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */
1221 GLuint tiled_surface
:1;
1228 GLuint multisample_position_palette_index
:3;
1230 GLuint num_multisamples
:3;
1232 GLuint render_target_view_extent
:9;
1233 GLuint min_array_elt
:11;
1239 GLuint cache_control
:2;
1245 } ss5
; /* New in G4X */
1251 struct brw_vertex_buffer_state
1256 GLuint access_type
:1;
1263 GLuint instance_data_step_rate
; /* not included for sequential/random vertices? */
1267 #define BRW_VBP_MAX 17
1269 struct brw_vb_array_state
{
1270 struct header header
;
1271 struct brw_vertex_buffer_state vb
[BRW_VBP_MAX
];
1275 struct brw_vertex_element_state
1279 GLuint src_offset
:11;
1281 GLuint src_format
:9;
1284 GLuint vertex_buffer_index
:5;
1289 GLuint dst_offset
:8;
1291 GLuint vfcomponent3
:4;
1292 GLuint vfcomponent2
:4;
1293 GLuint vfcomponent1
:4;
1294 GLuint vfcomponent0
:4;
1298 #define BRW_VEP_MAX 18
1300 struct brw_vertex_element_packet
{
1301 struct header header
;
1302 struct brw_vertex_element_state ve
[BRW_VEP_MAX
]; /* note: less than _TNL_ATTRIB_MAX */
1306 struct brw_urb_immediate
{
1309 GLuint swizzle_control
:2;
1314 GLuint response_length
:4;
1315 GLuint msg_length
:4;
1316 GLuint msg_target
:4;
1318 GLuint end_of_thread
:1;
1321 /* Instruction format for the execution units:
1324 struct brw_instruction
1330 GLuint access_mode
:1;
1331 GLuint mask_control
:1;
1332 GLuint dependency_control
:2;
1333 GLuint compression_control
:2; /* gen6: quater control */
1334 GLuint thread_control
:2;
1335 GLuint predicate_control
:4;
1336 GLuint predicate_inverse
:1;
1337 GLuint execution_size
:3;
1338 GLuint destreg__conditionalmod
:4; /* destreg - send, conditionalmod - others */
1339 GLuint acc_wr_control
:1;
1340 GLuint cmpt_control
:1;
1341 GLuint debug_control
:1;
1348 GLuint dest_reg_file
:2;
1349 GLuint dest_reg_type
:3;
1350 GLuint src0_reg_file
:2;
1351 GLuint src0_reg_type
:3;
1352 GLuint src1_reg_file
:2;
1353 GLuint src1_reg_type
:3;
1355 GLuint dest_subreg_nr
:5;
1356 GLuint dest_reg_nr
:8;
1357 GLuint dest_horiz_stride
:2;
1358 GLuint dest_address_mode
:1;
1363 GLuint dest_reg_file
:2;
1364 GLuint dest_reg_type
:3;
1365 GLuint src0_reg_file
:2;
1366 GLuint src0_reg_type
:3;
1367 GLuint src1_reg_file
:2; /* 0x00000c00 */
1368 GLuint src1_reg_type
:3; /* 0x00007000 */
1370 GLint dest_indirect_offset
:10; /* offset against the deref'd address reg */
1371 GLuint dest_subreg_nr
:3; /* subnr for the address reg a0.x */
1372 GLuint dest_horiz_stride
:2;
1373 GLuint dest_address_mode
:1;
1378 GLuint dest_reg_file
:2;
1379 GLuint dest_reg_type
:3;
1380 GLuint src0_reg_file
:2;
1381 GLuint src0_reg_type
:3;
1382 GLuint src1_reg_file
:2;
1383 GLuint src1_reg_type
:3;
1385 GLuint dest_writemask
:4;
1386 GLuint dest_subreg_nr
:1;
1387 GLuint dest_reg_nr
:8;
1388 GLuint dest_horiz_stride
:2;
1389 GLuint dest_address_mode
:1;
1394 GLuint dest_reg_file
:2;
1395 GLuint dest_reg_type
:3;
1396 GLuint src0_reg_file
:2;
1397 GLuint src0_reg_type
:3;
1399 GLuint dest_writemask
:4;
1400 GLint dest_indirect_offset
:6;
1401 GLuint dest_subreg_nr
:3;
1402 GLuint dest_horiz_stride
:2;
1403 GLuint dest_address_mode
:1;
1407 GLuint dest_reg_file
:2;
1408 GLuint dest_reg_type
:3;
1409 GLuint src0_reg_file
:2;
1410 GLuint src0_reg_type
:3;
1411 GLuint src1_reg_file
:2;
1412 GLuint src1_reg_type
:3;
1415 GLint jump_count
:16;
1423 GLuint src0_subreg_nr
:5;
1424 GLuint src0_reg_nr
:8;
1426 GLuint src0_negate
:1;
1427 GLuint src0_address_mode
:1;
1428 GLuint src0_horiz_stride
:2;
1429 GLuint src0_width
:3;
1430 GLuint src0_vert_stride
:4;
1431 GLuint flag_reg_nr
:1;
1437 GLint src0_indirect_offset
:10;
1438 GLuint src0_subreg_nr
:3;
1440 GLuint src0_negate
:1;
1441 GLuint src0_address_mode
:1;
1442 GLuint src0_horiz_stride
:2;
1443 GLuint src0_width
:3;
1444 GLuint src0_vert_stride
:4;
1445 GLuint flag_reg_nr
:1;
1451 GLuint src0_swz_x
:2;
1452 GLuint src0_swz_y
:2;
1453 GLuint src0_subreg_nr
:1;
1454 GLuint src0_reg_nr
:8;
1456 GLuint src0_negate
:1;
1457 GLuint src0_address_mode
:1;
1458 GLuint src0_swz_z
:2;
1459 GLuint src0_swz_w
:2;
1461 GLuint src0_vert_stride
:4;
1462 GLuint flag_reg_nr
:1;
1468 GLuint src0_swz_x
:2;
1469 GLuint src0_swz_y
:2;
1470 GLint src0_indirect_offset
:6;
1471 GLuint src0_subreg_nr
:3;
1473 GLuint src0_negate
:1;
1474 GLuint src0_address_mode
:1;
1475 GLuint src0_swz_z
:2;
1476 GLuint src0_swz_w
:2;
1478 GLuint src0_vert_stride
:4;
1479 GLuint flag_reg_nr
:1;
1486 GLuint end_of_thread
:1;
1489 } send_gen5
; /* for Ironlake only */
1497 GLuint src1_subreg_nr
:5;
1498 GLuint src1_reg_nr
:8;
1500 GLuint src1_negate
:1;
1501 GLuint src1_address_mode
:1;
1502 GLuint src1_horiz_stride
:2;
1503 GLuint src1_width
:3;
1504 GLuint src1_vert_stride
:4;
1510 GLuint src1_swz_x
:2;
1511 GLuint src1_swz_y
:2;
1512 GLuint src1_subreg_nr
:1;
1513 GLuint src1_reg_nr
:8;
1515 GLuint src1_negate
:1;
1516 GLuint src1_address_mode
:1;
1517 GLuint src1_swz_z
:2;
1518 GLuint src1_swz_w
:2;
1520 GLuint src1_vert_stride
:4;
1526 GLint src1_indirect_offset
:10;
1527 GLuint src1_subreg_nr
:3;
1529 GLuint src1_negate
:1;
1530 GLuint src1_address_mode
:1;
1531 GLuint src1_horiz_stride
:2;
1532 GLuint src1_width
:3;
1533 GLuint src1_vert_stride
:4;
1534 GLuint flag_reg_nr
:1;
1540 GLuint src1_swz_x
:2;
1541 GLuint src1_swz_y
:2;
1542 GLint src1_indirect_offset
:6;
1543 GLuint src1_subreg_nr
:3;
1545 GLuint src1_negate
:1;
1547 GLuint src1_swz_z
:2;
1548 GLuint src1_swz_w
:2;
1550 GLuint src1_vert_stride
:4;
1551 GLuint flag_reg_nr
:1;
1558 GLint jump_count
:16; /* note: signed */
1565 /* Signed jump distance to the ip to jump to if all channels
1566 * are disabled after the break or continue. It should point
1567 * to the end of the innermost control flow block, as that's
1568 * where some channel could get re-enabled.
1572 /* Signed jump distance to the location to resume execution
1573 * of this channel if it's enabled for the break or continue.
1585 GLuint response_length
:4;
1586 GLuint msg_length
:4;
1587 GLuint msg_target
:4;
1589 GLuint end_of_thread
:1;
1600 GLuint header_present
:1;
1601 GLuint response_length
:5;
1602 GLuint msg_length
:4;
1604 GLuint end_of_thread
:1;
1608 GLuint binding_table_index
:8;
1610 GLuint return_format
:2;
1612 GLuint response_length
:4;
1613 GLuint msg_length
:4;
1614 GLuint msg_target
:4;
1616 GLuint end_of_thread
:1;
1620 GLuint binding_table_index
:8;
1623 GLuint response_length
:4;
1624 GLuint msg_length
:4;
1625 GLuint msg_target
:4;
1627 GLuint end_of_thread
:1;
1631 GLuint binding_table_index
:8;
1636 GLuint header_present
:1;
1637 GLuint response_length
:5;
1638 GLuint msg_length
:4;
1640 GLuint end_of_thread
:1;
1643 struct brw_urb_immediate urb
;
1648 GLuint swizzle_control
:2;
1654 GLuint header_present
:1;
1655 GLuint response_length
:5;
1656 GLuint msg_length
:4;
1658 GLuint end_of_thread
:1;
1662 GLuint binding_table_index
:8;
1663 GLuint msg_control
:4;
1665 GLuint target_cache
:2;
1666 GLuint response_length
:4;
1667 GLuint msg_length
:4;
1668 GLuint msg_target
:4;
1670 GLuint end_of_thread
:1;
1674 GLuint binding_table_index
:8;
1675 GLuint msg_control
:3;
1677 GLuint target_cache
:2;
1678 GLuint response_length
:4;
1679 GLuint msg_length
:4;
1680 GLuint msg_target
:4;
1682 GLuint end_of_thread
:1;
1686 GLuint binding_table_index
:8;
1687 GLuint msg_control
:3;
1689 GLuint target_cache
:2;
1691 GLuint header_present
:1;
1692 GLuint response_length
:5;
1693 GLuint msg_length
:4;
1695 GLuint end_of_thread
:1;
1699 GLuint binding_table_index
:8;
1700 GLuint msg_control
:3;
1701 GLuint pixel_scoreboard_clear
:1;
1703 GLuint send_commit_msg
:1;
1704 GLuint response_length
:4;
1705 GLuint msg_length
:4;
1706 GLuint msg_target
:4;
1708 GLuint end_of_thread
:1;
1712 GLuint binding_table_index
:8;
1713 GLuint msg_control
:3;
1714 GLuint pixel_scoreboard_clear
:1;
1716 GLuint send_commit_msg
:1;
1718 GLuint header_present
:1;
1719 GLuint response_length
:5;
1720 GLuint msg_length
:4;
1722 GLuint end_of_thread
:1;
1725 /* Sandybridge DP for sample cache, constant cache, render cache */
1727 GLuint binding_table_index
:8;
1728 GLuint msg_control
:5;
1731 GLuint header_present
:1;
1732 GLuint response_length
:5;
1733 GLuint msg_length
:4;
1735 GLuint end_of_thread
:1;
1736 } dp_sampler_const_cache
;
1739 GLuint binding_table_index
:8;
1740 GLuint msg_control
:3;
1741 GLuint slot_group_select
:1;
1742 GLuint pixel_scoreboard_clear
:1;
1744 GLuint send_commit_msg
:1;
1746 GLuint header_present
:1;
1747 GLuint response_length
:5;
1748 GLuint msg_length
:4;
1750 GLuint end_of_thread
:1;
1754 GLuint function_control
:16;
1755 GLuint response_length
:4;
1756 GLuint msg_length
:4;
1757 GLuint msg_target
:4;
1759 GLuint end_of_thread
:1;
1762 /* Of this struct, only end_of_thread is not present for gen6. */
1764 GLuint function_control
:19;
1765 GLuint header_present
:1;
1766 GLuint response_length
:5;
1767 GLuint msg_length
:4;
1769 GLuint end_of_thread
:1;