src/mesa/drivers/dri/i965/brw_structs.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #ifndef BRW_STRUCTS_H
  34 #define BRW_STRUCTS_H
  35
  36 struct brw_urb_fence
  37 {
  38    struct
  39    {
  40       unsigned length:8;
  41       unsigned vs_realloc:1;
  42       unsigned gs_realloc:1;
  43       unsigned clp_realloc:1;
  44       unsigned sf_realloc:1;
  45       unsigned vfe_realloc:1;
  46       unsigned cs_realloc:1;
  47       unsigned pad:2;
  48       unsigned opcode:16;
  49    } header;
  50
  51    struct
  52    {
  53       unsigned vs_fence:10;
  54       unsigned gs_fence:10;
  55       unsigned clp_fence:10;
  56       unsigned pad:2;
  57    } bits0;
  58
  59    struct
  60    {
  61       unsigned sf_fence:10;
  62       unsigned vf_fence:10;
  63       unsigned cs_fence:11;
  64       unsigned pad:1;
  65    } bits1;
  66 };
  67
  68 /* State structs for the various fixed function units:
  69  */
  70
  71
  72 struct thread0
  73 {
  74    unsigned pad0:1;
  75    unsigned grf_reg_count:3;
  76    unsigned pad1:2;
  77    unsigned kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
  78 };
  79
  80 struct thread1
  81 {
  82    unsigned ext_halt_exception_enable:1;
  83    unsigned sw_exception_enable:1;
  84    unsigned mask_stack_exception_enable:1;
  85    unsigned timeout_exception_enable:1;
  86    unsigned illegal_op_exception_enable:1;
  87    unsigned pad0:3;
  88    unsigned depth_coef_urb_read_offset:6;       /* WM only */
  89    unsigned pad1:2;
  90    unsigned floating_point_mode:1;
  91    unsigned thread_priority:1;
  92    unsigned binding_table_entry_count:8;
  93    unsigned pad3:5;
  94    unsigned single_program_flow:1;
  95 };
  96
  97 struct thread2
  98 {
  99    unsigned per_thread_scratch_space:4;
 100    unsigned pad0:6;
 101    unsigned scratch_space_base_pointer:22;
 102 };
 103
 104
 105 struct thread3
 106 {
 107    unsigned dispatch_grf_start_reg:4;
 108    unsigned urb_entry_read_offset:6;
 109    unsigned pad0:1;
 110    unsigned urb_entry_read_length:6;
 111    unsigned pad1:1;
 112    unsigned const_urb_entry_read_offset:6;
 113    unsigned pad2:1;
 114    unsigned const_urb_entry_read_length:6;
 115    unsigned pad3:1;
 116 };
 117
 118
 119
 120 struct brw_clip_unit_state
 121 {
 122    struct thread0 thread0;
 123    struct
 124    {
 125       unsigned pad0:7;
 126       unsigned sw_exception_enable:1;
 127       unsigned pad1:3;
 128       unsigned mask_stack_exception_enable:1;
 129       unsigned pad2:1;
 130       unsigned illegal_op_exception_enable:1;
 131       unsigned pad3:2;
 132       unsigned floating_point_mode:1;
 133       unsigned thread_priority:1;
 134       unsigned binding_table_entry_count:8;
 135       unsigned pad4:5;
 136       unsigned single_program_flow:1;
 137    } thread1;
 138
 139    struct thread2 thread2;
 140    struct thread3 thread3;
 141
 142    struct
 143    {
 144       unsigned pad0:9;
 145       unsigned gs_output_stats:1; /* not always */
 146       unsigned stats_enable:1;
 147       unsigned nr_urb_entries:7;
 148       unsigned pad1:1;
 149       unsigned urb_entry_allocation_size:5;
 150       unsigned pad2:1;
 151       unsigned max_threads:5;   /* may be less */
 152       unsigned pad3:2;
 153    } thread4;
 154
 155    struct
 156    {
 157       unsigned pad0:13;
 158       unsigned clip_mode:3;
 159       unsigned userclip_enable_flags:8;
 160       unsigned userclip_must_clip:1;
 161       unsigned negative_w_clip_test:1;
 162       unsigned guard_band_enable:1;
 163       unsigned viewport_z_clip_enable:1;
 164       unsigned viewport_xy_clip_enable:1;
 165       unsigned vertex_position_space:1;
 166       unsigned api_mode:1;
 167       unsigned pad2:1;
 168    } clip5;
 169
 170    struct
 171    {
 172       unsigned pad0:5;
 173       unsigned clipper_viewport_state_ptr:27;
 174    } clip6;
 175
 176
 177    float viewport_xmin;
 178    float viewport_xmax;
 179    float viewport_ymin;
 180    float viewport_ymax;
 181 };
 182
 183 struct brw_wm_unit_state
 184 {
 185    struct thread0 thread0;
 186    struct thread1 thread1;
 187    struct thread2 thread2;
 188    struct thread3 thread3;
 189
 190    struct {
 191       unsigned stats_enable:1;
 192       unsigned depth_buffer_clear:1;
 193       unsigned sampler_count:3;
 194       unsigned sampler_state_pointer:27;
 195    } wm4;
 196
 197    struct
 198    {
 199       unsigned enable_8_pix:1;
 200       unsigned enable_16_pix:1;
 201       unsigned enable_32_pix:1;
 202       unsigned enable_con_32_pix:1;
 203       unsigned enable_con_64_pix:1;
 204       unsigned pad0:1;
 205
 206       /* These next four bits are for Ironlake+ */
 207       unsigned fast_span_coverage_enable:1;
 208       unsigned depth_buffer_clear:1;
 209       unsigned depth_buffer_resolve_enable:1;
 210       unsigned hierarchical_depth_buffer_resolve_enable:1;
 211
 212       unsigned legacy_global_depth_bias:1;
 213       unsigned line_stipple:1;
 214       unsigned depth_offset:1;
 215       unsigned polygon_stipple:1;
 216       unsigned line_aa_region_width:2;
 217       unsigned line_endcap_aa_region_width:2;
 218       unsigned early_depth_test:1;
 219       unsigned thread_dispatch_enable:1;
 220       unsigned program_uses_depth:1;
 221       unsigned program_computes_depth:1;
 222       unsigned program_uses_killpixel:1;
 223       unsigned legacy_line_rast: 1;
 224       unsigned transposed_urb_read_enable:1;
 225       unsigned max_threads:7;
 226    } wm5;
 227
 228    float global_depth_offset_constant;
 229    float global_depth_offset_scale;
 230
 231    /* for Ironlake only */
 232    struct {
 233       unsigned pad0:1;
 234       unsigned grf_reg_count_1:3;
 235       unsigned pad1:2;
 236       unsigned kernel_start_pointer_1:26;
 237    } wm8;
 238
 239    struct {
 240       unsigned pad0:1;
 241       unsigned grf_reg_count_2:3;
 242       unsigned pad1:2;
 243       unsigned kernel_start_pointer_2:26;
 244    } wm9;
 245
 246    struct {
 247       unsigned pad0:1;
 248       unsigned grf_reg_count_3:3;
 249       unsigned pad1:2;
 250       unsigned kernel_start_pointer_3:26;
 251    } wm10;
 252 };
 253
 254 struct gen5_sampler_default_color {
 255    uint8_t ub[4];
 256    float f[4];
 257    uint16_t hf[4];
 258    uint16_t us[4];
 259    int16_t s[4];
 260    uint8_t b[4];
 261 };
 262
 263 #endif