2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
37 /** Number of general purpose registers (VS, WM, etc) */
38 #define BRW_MAX_GRF 128
40 /** Number of message register file registers */
41 #define BRW_MAX_MRF 16
43 /* These seem to be passed around as function args, so it works out
44 * better to keep them as #defines:
46 #define BRW_FLUSH_READ_CACHE 0x1
47 #define BRW_FLUSH_STATE_CACHE 0x2
48 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
49 #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8
83 /* State structs for the various fixed function units:
90 GLuint grf_reg_count
:3;
92 GLuint kernel_start_pointer
:26; /* Offset from GENERAL_STATE_BASE */
97 GLuint ext_halt_exception_enable
:1;
98 GLuint sw_exception_enable
:1;
99 GLuint mask_stack_exception_enable
:1;
100 GLuint timeout_exception_enable
:1;
101 GLuint illegal_op_exception_enable
:1;
103 GLuint depth_coef_urb_read_offset
:6; /* WM only */
105 GLuint floating_point_mode
:1;
106 GLuint thread_priority
:1;
107 GLuint binding_table_entry_count
:8;
109 GLuint single_program_flow
:1;
114 GLuint per_thread_scratch_space
:4;
116 GLuint scratch_space_base_pointer
:22;
122 GLuint dispatch_grf_start_reg
:4;
123 GLuint urb_entry_read_offset
:6;
125 GLuint urb_entry_read_length
:6;
127 GLuint const_urb_entry_read_offset
:6;
129 GLuint const_urb_entry_read_length
:6;
135 struct brw_clip_unit_state
137 struct thread0 thread0
;
141 GLuint sw_exception_enable
:1;
143 GLuint mask_stack_exception_enable
:1;
145 GLuint illegal_op_exception_enable
:1;
147 GLuint floating_point_mode
:1;
148 GLuint thread_priority
:1;
149 GLuint binding_table_entry_count
:8;
151 GLuint single_program_flow
:1;
154 struct thread2 thread2
;
155 struct thread3 thread3
;
160 GLuint gs_output_stats
:1; /* not always */
161 GLuint stats_enable
:1;
162 GLuint nr_urb_entries
:7;
164 GLuint urb_entry_allocation_size
:5;
166 GLuint max_threads
:5; /* may be less */
174 GLuint userclip_enable_flags
:8;
175 GLuint userclip_must_clip
:1;
176 GLuint negative_w_clip_test
:1;
177 GLuint guard_band_enable
:1;
178 GLuint viewport_z_clip_enable
:1;
179 GLuint viewport_xy_clip_enable
:1;
180 GLuint vertex_position_space
:1;
188 GLuint clipper_viewport_state_ptr
:27;
192 GLfloat viewport_xmin
;
193 GLfloat viewport_xmax
;
194 GLfloat viewport_ymin
;
195 GLfloat viewport_ymax
;
198 struct gen6_blend_state
201 GLuint dest_blend_factor
:5;
202 GLuint source_blend_factor
:5;
206 GLuint ia_dest_blend_factor
:5;
207 GLuint ia_source_blend_factor
:5;
209 GLuint ia_blend_func
:3;
211 GLuint ia_blend_enable
:1;
212 GLuint blend_enable
:1;
216 GLuint post_blend_clamp_enable
:1;
217 GLuint pre_blend_clamp_enable
:1;
218 GLuint clamp_range
:2;
220 GLuint x_dither_offset
:2;
221 GLuint y_dither_offset
:2;
222 GLuint dither_enable
:1;
223 GLuint alpha_test_func
:3;
224 GLuint alpha_test_enable
:1;
226 GLuint logic_op_func
:4;
227 GLuint logic_op_enable
:1;
229 GLuint write_disable_b
:1;
230 GLuint write_disable_g
:1;
231 GLuint write_disable_r
:1;
232 GLuint write_disable_a
:1;
234 GLuint alpha_to_coverage_dither
:1;
235 GLuint alpha_to_one
:1;
236 GLuint alpha_to_coverage
:1;
240 struct gen6_color_calc_state
243 GLuint alpha_test_format
:1;
245 GLuint round_disable
:1;
246 GLuint bf_stencil_ref
:8;
247 GLuint stencil_ref
:8;
264 struct gen6_depth_stencil_state
268 GLuint bf_stencil_pass_depth_pass_op
:3;
269 GLuint bf_stencil_pass_depth_fail_op
:3;
270 GLuint bf_stencil_fail_op
:3;
271 GLuint bf_stencil_func
:3;
272 GLuint bf_stencil_enable
:1;
274 GLuint stencil_write_enable
:1;
275 GLuint stencil_pass_depth_pass_op
:3;
276 GLuint stencil_pass_depth_fail_op
:3;
277 GLuint stencil_fail_op
:3;
278 GLuint stencil_func
:3;
279 GLuint stencil_enable
:1;
283 GLuint bf_stencil_write_mask
:8;
284 GLuint bf_stencil_test_mask
:8;
285 GLuint stencil_write_mask
:8;
286 GLuint stencil_test_mask
:8;
291 GLuint depth_write_enable
:1;
292 GLuint depth_test_func
:3;
294 GLuint depth_test_enable
:1;
298 struct brw_cc_unit_state
303 GLuint bf_stencil_pass_depth_pass_op
:3;
304 GLuint bf_stencil_pass_depth_fail_op
:3;
305 GLuint bf_stencil_fail_op
:3;
306 GLuint bf_stencil_func
:3;
307 GLuint bf_stencil_enable
:1;
309 GLuint stencil_write_enable
:1;
310 GLuint stencil_pass_depth_pass_op
:3;
311 GLuint stencil_pass_depth_fail_op
:3;
312 GLuint stencil_fail_op
:3;
313 GLuint stencil_func
:3;
314 GLuint stencil_enable
:1;
320 GLuint bf_stencil_ref
:8;
321 GLuint stencil_write_mask
:8;
322 GLuint stencil_test_mask
:8;
323 GLuint stencil_ref
:8;
329 GLuint logicop_enable
:1;
331 GLuint depth_write_enable
:1;
332 GLuint depth_test_function
:3;
334 GLuint bf_stencil_write_mask
:8;
335 GLuint bf_stencil_test_mask
:8;
342 GLuint alpha_test_func
:3;
344 GLuint blend_enable
:1;
345 GLuint ia_blend_enable
:1;
347 GLuint alpha_test_format
:1;
354 GLuint cc_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
360 GLuint ia_dest_blend_factor
:5;
361 GLuint ia_src_blend_factor
:5;
362 GLuint ia_blend_function
:3;
363 GLuint statistics_enable
:1;
364 GLuint logicop_func
:4;
366 GLuint dither_enable
:1;
371 GLuint clamp_post_alpha_blend
:1;
372 GLuint clamp_pre_alpha_blend
:1;
373 GLuint clamp_range
:2;
375 GLuint y_dither_offset
:2;
376 GLuint x_dither_offset
:2;
377 GLuint dest_blend_factor
:5;
378 GLuint src_blend_factor
:5;
379 GLuint blend_function
:3;
390 struct brw_sf_unit_state
392 struct thread0 thread0
;
393 struct thread1 thread1
;
394 struct thread2 thread2
;
395 struct thread3 thread3
;
400 GLuint stats_enable
:1;
401 GLuint nr_urb_entries
:7;
403 GLuint urb_entry_allocation_size
:5;
405 GLuint max_threads
:6;
411 GLuint front_winding
:1;
412 GLuint viewport_transform
:1;
414 GLuint sf_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
420 GLuint dest_org_vbias
:4;
421 GLuint dest_org_hbias
:4;
423 GLuint disable_2x2_trifilter
:1;
424 GLuint disable_zero_pix_trifilter
:1;
425 GLuint point_rast_rule
:2;
426 GLuint line_endcap_aa_region_width
:2;
428 GLuint fast_scissor_disable
:1;
435 GLuint point_size
:11;
436 GLuint use_point_size_state
:1;
437 GLuint subpixel_precision
:1;
438 GLuint sprite_point
:1;
440 GLuint aa_line_distance_mode
:1;
442 GLuint linestrip_pv
:2;
443 GLuint tristrip_pv
:2;
444 GLuint line_last_pixel_enable
:1;
449 struct gen6_scissor_rect
457 struct brw_gs_unit_state
459 struct thread0 thread0
;
460 struct thread1 thread1
;
461 struct thread2 thread2
;
462 struct thread3 thread3
;
467 GLuint rendering_enable
:1; /* for Ironlake */
469 GLuint stats_enable
:1;
470 GLuint nr_urb_entries
:7;
472 GLuint urb_entry_allocation_size
:5;
474 GLuint max_threads
:5;
480 GLuint sampler_count
:3;
482 GLuint sampler_state_pointer
:27;
488 GLuint max_vp_index
:4;
490 GLuint svbi_post_inc_value
:10;
492 GLuint svbi_post_inc_enable
:1;
493 GLuint svbi_payload
:1;
494 GLuint discard_adjaceny
:1;
495 GLuint reorder_enable
:1;
501 struct brw_vs_unit_state
503 struct thread0 thread0
;
504 struct thread1 thread1
;
505 struct thread2 thread2
;
506 struct thread3 thread3
;
511 GLuint stats_enable
:1;
512 GLuint nr_urb_entries
:7;
514 GLuint urb_entry_allocation_size
:5;
516 GLuint max_threads
:6;
522 GLuint sampler_count
:3;
524 GLuint sampler_state_pointer
:27;
530 GLuint vert_cache_disable
:1;
536 struct brw_wm_unit_state
538 struct thread0 thread0
;
539 struct thread1 thread1
;
540 struct thread2 thread2
;
541 struct thread3 thread3
;
544 GLuint stats_enable
:1;
545 GLuint depth_buffer_clear
:1;
546 GLuint sampler_count
:3;
547 GLuint sampler_state_pointer
:27;
552 GLuint enable_8_pix
:1;
553 GLuint enable_16_pix
:1;
554 GLuint enable_32_pix
:1;
555 GLuint enable_con_32_pix
:1;
556 GLuint enable_con_64_pix
:1;
559 /* These next four bits are for Ironlake+ */
560 GLuint fast_span_coverage_enable
:1;
561 GLuint depth_buffer_clear
:1;
562 GLuint depth_buffer_resolve_enable
:1;
563 GLuint hierarchical_depth_buffer_resolve_enable
:1;
565 GLuint legacy_global_depth_bias
:1;
566 GLuint line_stipple
:1;
567 GLuint depth_offset
:1;
568 GLuint polygon_stipple
:1;
569 GLuint line_aa_region_width
:2;
570 GLuint line_endcap_aa_region_width
:2;
571 GLuint early_depth_test
:1;
572 GLuint thread_dispatch_enable
:1;
573 GLuint program_uses_depth
:1;
574 GLuint program_computes_depth
:1;
575 GLuint program_uses_killpixel
:1;
576 GLuint legacy_line_rast
: 1;
577 GLuint transposed_urb_read_enable
:1;
578 GLuint max_threads
:7;
581 GLfloat global_depth_offset_constant
;
582 GLfloat global_depth_offset_scale
;
584 /* for Ironlake only */
587 GLuint grf_reg_count_1
:3;
589 GLuint kernel_start_pointer_1
:26;
594 GLuint grf_reg_count_2
:3;
596 GLuint kernel_start_pointer_2
:26;
601 GLuint grf_reg_count_3
:3;
603 GLuint kernel_start_pointer_3
:26;
607 struct brw_sampler_default_color
{
611 struct gen5_sampler_default_color
{
620 struct brw_sampler_state
625 GLuint shadow_function
:3;
631 GLuint min_mag_neq
:1;
632 GLuint lod_preclamp
:1;
633 GLuint default_color_mode
:1;
640 GLuint r_wrap_mode
:3;
641 GLuint t_wrap_mode
:3;
642 GLuint s_wrap_mode
:3;
643 GLuint cube_control_mode
:1;
653 GLuint default_color_pointer
:27;
658 GLuint non_normalized_coord
:1;
660 GLuint address_round
:6;
662 GLuint chroma_key_mode
:1;
663 GLuint chroma_key_index
:2;
664 GLuint chroma_key_enable
:1;
665 GLuint monochrome_filter_width
:3;
666 GLuint monochrome_filter_height
:3;
670 struct gen7_sampler_state
674 GLuint aniso_algorithm
:1;
681 GLuint lod_preclamp
:1;
682 GLuint default_color_mode
:1;
689 GLuint cube_control_mode
:1;
690 GLuint shadow_function
:3;
699 GLuint default_color_pointer
:27;
704 GLuint r_wrap_mode
:3;
705 GLuint t_wrap_mode
:3;
706 GLuint s_wrap_mode
:3;
708 GLuint non_normalized_coord
:1;
709 GLuint trilinear_quality
:2;
710 GLuint address_round
:6;
712 GLuint chroma_key_mode
:1;
713 GLuint chroma_key_index
:2;
714 GLuint chroma_key_enable
:1;
719 struct brw_clipper_viewport
727 struct brw_cc_viewport
733 struct brw_sf_viewport
744 /* scissor coordinates are inclusive */
753 struct gen6_sf_viewport
{
762 struct gen7_sf_clip_viewport
{
784 /* volume 5c Shared Functions - 1.13.4.1.2 */
785 struct gen7_surface_state
795 GLuint render_cache_read_write
:1;
797 GLuint surface_array_spacing
:1;
798 GLuint vert_line_stride_ofs
:1;
799 GLuint vert_line_stride
:1;
801 GLuint tiled_surface
:1;
802 GLuint horizontal_alignment
:1;
803 GLuint vertical_alignment
:2;
804 GLuint surface_format
:9; /**< BRW_SURFACEFORMAT_x */
807 GLuint surface_type
:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */
828 GLuint multisample_position_palette_index
:3;
829 GLuint num_multisamples
:3;
830 GLuint multisampled_surface_storage_format
:1;
831 GLuint render_target_view_extent
:11;
832 GLuint min_array_elt
:11;
847 GLuint pad
; /* Multisample Control Surface stuff */
851 GLuint resource_min_lod
:12;
853 GLuint alpha_clear_color
:1;
854 GLuint blue_clear_color
:1;
855 GLuint green_clear_color
:1;
856 GLuint red_clear_color
:1;
861 struct brw_vertex_element_state
865 GLuint src_offset
:11;
870 GLuint vertex_buffer_index
:5;
877 GLuint vfcomponent3
:4;
878 GLuint vfcomponent2
:4;
879 GLuint vfcomponent1
:4;
880 GLuint vfcomponent0
:4;
884 #define BRW_VEP_MAX 18
886 struct brw_urb_immediate
{
889 GLuint swizzle_control
:2;
894 GLuint response_length
:4;
898 GLuint end_of_thread
:1;
901 /* Instruction format for the execution units:
904 struct brw_instruction
910 GLuint access_mode
:1;
911 GLuint mask_control
:1;
912 GLuint dependency_control
:2;
913 GLuint compression_control
:2; /* gen6: quater control */
914 GLuint thread_control
:2;
915 GLuint predicate_control
:4;
916 GLuint predicate_inverse
:1;
917 GLuint execution_size
:3;
919 * Conditional Modifier for most instructions. On Gen6+, this is also
920 * used for the SEND instruction's Message Target/SFID.
922 GLuint destreg__conditionalmod
:4;
923 GLuint acc_wr_control
:1;
924 GLuint cmpt_control
:1;
925 GLuint debug_control
:1;
932 GLuint dest_reg_file
:2;
933 GLuint dest_reg_type
:3;
934 GLuint src0_reg_file
:2;
935 GLuint src0_reg_type
:3;
936 GLuint src1_reg_file
:2;
937 GLuint src1_reg_type
:3;
939 GLuint dest_subreg_nr
:5;
940 GLuint dest_reg_nr
:8;
941 GLuint dest_horiz_stride
:2;
942 GLuint dest_address_mode
:1;
947 GLuint dest_reg_file
:2;
948 GLuint dest_reg_type
:3;
949 GLuint src0_reg_file
:2;
950 GLuint src0_reg_type
:3;
951 GLuint src1_reg_file
:2; /* 0x00000c00 */
952 GLuint src1_reg_type
:3; /* 0x00007000 */
954 GLint dest_indirect_offset
:10; /* offset against the deref'd address reg */
955 GLuint dest_subreg_nr
:3; /* subnr for the address reg a0.x */
956 GLuint dest_horiz_stride
:2;
957 GLuint dest_address_mode
:1;
962 GLuint dest_reg_file
:2;
963 GLuint dest_reg_type
:3;
964 GLuint src0_reg_file
:2;
965 GLuint src0_reg_type
:3;
966 GLuint src1_reg_file
:2;
967 GLuint src1_reg_type
:3;
969 GLuint dest_writemask
:4;
970 GLuint dest_subreg_nr
:1;
971 GLuint dest_reg_nr
:8;
972 GLuint dest_horiz_stride
:2;
973 GLuint dest_address_mode
:1;
978 GLuint dest_reg_file
:2;
979 GLuint dest_reg_type
:3;
980 GLuint src0_reg_file
:2;
981 GLuint src0_reg_type
:3;
983 GLuint dest_writemask
:4;
984 GLint dest_indirect_offset
:6;
985 GLuint dest_subreg_nr
:3;
986 GLuint dest_horiz_stride
:2;
987 GLuint dest_address_mode
:1;
991 GLuint dest_reg_file
:2;
992 GLuint dest_reg_type
:3;
993 GLuint src0_reg_file
:2;
994 GLuint src0_reg_type
:3;
995 GLuint src1_reg_file
:2;
996 GLuint src1_reg_type
:3;
1007 GLuint src0_subreg_nr
:5;
1008 GLuint src0_reg_nr
:8;
1010 GLuint src0_negate
:1;
1011 GLuint src0_address_mode
:1;
1012 GLuint src0_horiz_stride
:2;
1013 GLuint src0_width
:3;
1014 GLuint src0_vert_stride
:4;
1015 GLuint flag_reg_nr
:1;
1021 GLint src0_indirect_offset
:10;
1022 GLuint src0_subreg_nr
:3;
1024 GLuint src0_negate
:1;
1025 GLuint src0_address_mode
:1;
1026 GLuint src0_horiz_stride
:2;
1027 GLuint src0_width
:3;
1028 GLuint src0_vert_stride
:4;
1029 GLuint flag_reg_nr
:1;
1035 GLuint src0_swz_x
:2;
1036 GLuint src0_swz_y
:2;
1037 GLuint src0_subreg_nr
:1;
1038 GLuint src0_reg_nr
:8;
1040 GLuint src0_negate
:1;
1041 GLuint src0_address_mode
:1;
1042 GLuint src0_swz_z
:2;
1043 GLuint src0_swz_w
:2;
1045 GLuint src0_vert_stride
:4;
1046 GLuint flag_reg_nr
:1;
1052 GLuint src0_swz_x
:2;
1053 GLuint src0_swz_y
:2;
1054 GLint src0_indirect_offset
:6;
1055 GLuint src0_subreg_nr
:3;
1057 GLuint src0_negate
:1;
1058 GLuint src0_address_mode
:1;
1059 GLuint src0_swz_z
:2;
1060 GLuint src0_swz_w
:2;
1062 GLuint src0_vert_stride
:4;
1063 GLuint flag_reg_nr
:1;
1067 /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
1069 * Does not apply to Gen6+. The SFID/message target moved to bits
1070 * 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
1075 GLuint end_of_thread
:1;
1078 } send_gen5
; /* for Ironlake only */
1086 GLuint src1_subreg_nr
:5;
1087 GLuint src1_reg_nr
:8;
1089 GLuint src1_negate
:1;
1090 GLuint src1_address_mode
:1;
1091 GLuint src1_horiz_stride
:2;
1092 GLuint src1_width
:3;
1093 GLuint src1_vert_stride
:4;
1099 GLuint src1_swz_x
:2;
1100 GLuint src1_swz_y
:2;
1101 GLuint src1_subreg_nr
:1;
1102 GLuint src1_reg_nr
:8;
1104 GLuint src1_negate
:1;
1105 GLuint src1_address_mode
:1;
1106 GLuint src1_swz_z
:2;
1107 GLuint src1_swz_w
:2;
1109 GLuint src1_vert_stride
:4;
1115 GLint src1_indirect_offset
:10;
1116 GLuint src1_subreg_nr
:3;
1118 GLuint src1_negate
:1;
1119 GLuint src1_address_mode
:1;
1120 GLuint src1_horiz_stride
:2;
1121 GLuint src1_width
:3;
1122 GLuint src1_vert_stride
:4;
1123 GLuint flag_reg_nr
:1;
1129 GLuint src1_swz_x
:2;
1130 GLuint src1_swz_y
:2;
1131 GLint src1_indirect_offset
:6;
1132 GLuint src1_subreg_nr
:3;
1134 GLuint src1_negate
:1;
1136 GLuint src1_swz_z
:2;
1137 GLuint src1_swz_w
:2;
1139 GLuint src1_vert_stride
:4;
1140 GLuint flag_reg_nr
:1;
1147 GLint jump_count
:16; /* note: signed */
1152 /* This is also used for gen7 IF/ELSE instructions */
1155 /* Signed jump distance to the ip to jump to if all channels
1156 * are disabled after the break or continue. It should point
1157 * to the end of the innermost control flow block, as that's
1158 * where some channel could get re-enabled.
1162 /* Signed jump distance to the location to resume execution
1163 * of this channel if it's enabled for the break or continue.
1169 * \defgroup SEND instructions / Message Descriptors
1175 * Generic Message Descriptor for Gen4 SEND instructions. The structs
1176 * below expand function_control to something specific for their
1177 * message. Due to struct packing issues, they duplicate these bits.
1179 * See the G45 PRM, Volume 4, Table 14-15.
1182 GLuint function_control
:16;
1183 GLuint response_length
:4;
1184 GLuint msg_length
:4;
1185 GLuint msg_target
:4;
1187 GLuint end_of_thread
:1;
1191 * Generic Message Descriptor for Gen5-7 SEND instructions.
1193 * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15. (Sadly, most
1194 * of the information on the SEND instruction is missing from the public
1197 * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies.
1198 * According to the SEND instruction description:
1199 * "The MSb of the message description, the EOT field, always comes from
1200 * bit 127 of the instruction word"...which is bit 31 of this field.
1203 GLuint function_control
:19;
1204 GLuint header_present
:1;
1205 GLuint response_length
:5;
1206 GLuint msg_length
:4;
1208 GLuint end_of_thread
:1;
1211 /** G45 PRM, Volume 4, Section 6.1.1.1 */
1219 GLuint response_length
:4;
1220 GLuint msg_length
:4;
1221 GLuint msg_target
:4;
1223 GLuint end_of_thread
:1;
1226 /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */
1235 GLuint header_present
:1;
1236 GLuint response_length
:5;
1237 GLuint msg_length
:4;
1239 GLuint end_of_thread
:1;
1242 /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */
1244 GLuint binding_table_index
:8;
1246 GLuint return_format
:2;
1248 GLuint response_length
:4;
1249 GLuint msg_length
:4;
1250 GLuint msg_target
:4;
1252 GLuint end_of_thread
:1;
1255 /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */
1257 GLuint binding_table_index
:8;
1260 GLuint response_length
:4;
1261 GLuint msg_length
:4;
1262 GLuint msg_target
:4;
1264 GLuint end_of_thread
:1;
1267 /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */
1269 GLuint binding_table_index
:8;
1274 GLuint header_present
:1;
1275 GLuint response_length
:5;
1276 GLuint msg_length
:4;
1278 GLuint end_of_thread
:1;
1282 GLuint binding_table_index
:8;
1286 GLuint header_present
:1;
1287 GLuint response_length
:5;
1288 GLuint msg_length
:4;
1290 GLuint end_of_thread
:1;
1293 struct brw_urb_immediate urb
;
1298 GLuint swizzle_control
:2;
1304 GLuint header_present
:1;
1305 GLuint response_length
:5;
1306 GLuint msg_length
:4;
1308 GLuint end_of_thread
:1;
1314 GLuint swizzle_control
:1;
1316 GLuint per_slot_offset
:1;
1318 GLuint header_present
:1;
1319 GLuint response_length
:5;
1320 GLuint msg_length
:4;
1322 GLuint end_of_thread
:1;
1325 /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
1327 GLuint binding_table_index
:8;
1328 GLuint msg_control
:4;
1330 GLuint target_cache
:2;
1331 GLuint response_length
:4;
1332 GLuint msg_length
:4;
1333 GLuint msg_target
:4;
1335 GLuint end_of_thread
:1;
1338 /** G45 PRM, Volume 4, Section 5.10.1.1.2 */
1340 GLuint binding_table_index
:8;
1341 GLuint msg_control
:3;
1343 GLuint target_cache
:2;
1344 GLuint response_length
:4;
1345 GLuint msg_length
:4;
1346 GLuint msg_target
:4;
1348 GLuint end_of_thread
:1;
1351 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1353 GLuint binding_table_index
:8;
1354 GLuint msg_control
:3;
1356 GLuint target_cache
:2;
1358 GLuint header_present
:1;
1359 GLuint response_length
:5;
1360 GLuint msg_length
:4;
1362 GLuint end_of_thread
:1;
1365 /** G45 PRM, Volume 4, Section 5.10.1.1.2. For both Gen4 and G45. */
1367 GLuint binding_table_index
:8;
1368 GLuint msg_control
:3;
1369 GLuint last_render_target
:1;
1371 GLuint send_commit_msg
:1;
1372 GLuint response_length
:4;
1373 GLuint msg_length
:4;
1374 GLuint msg_target
:4;
1376 GLuint end_of_thread
:1;
1379 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1381 GLuint binding_table_index
:8;
1382 GLuint msg_control
:3;
1383 GLuint last_render_target
:1;
1385 GLuint send_commit_msg
:1;
1387 GLuint header_present
:1;
1388 GLuint response_length
:5;
1389 GLuint msg_length
:4;
1391 GLuint end_of_thread
:1;
1395 * Message for the Sandybridge Sampler Cache or Constant Cache Data Port.
1397 * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
1400 GLuint binding_table_index
:8;
1401 GLuint msg_control
:5;
1404 GLuint header_present
:1;
1405 GLuint response_length
:5;
1406 GLuint msg_length
:4;
1408 GLuint end_of_thread
:1;
1409 } gen6_dp_sampler_const_cache
;
1412 * Message for the Sandybridge Render Cache Data Port.
1414 * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1,
1415 * Section 3.9.2.1.1: Message Descriptor.
1417 * "Slot Group Select" and "Last Render Target" are part of the
1418 * 5-bit message control for Render Target Write messages. See
1419 * Section 3.9.9.2.1 of the same volume.
1422 GLuint binding_table_index
:8;
1423 GLuint msg_control
:3;
1424 GLuint slot_group_select
:1;
1425 GLuint last_render_target
:1;
1427 GLuint send_commit_msg
:1;
1429 GLuint header_present
:1;
1430 GLuint response_length
:5;
1431 GLuint msg_length
:4;
1433 GLuint end_of_thread
:1;
1437 * Message for any of the Gen7 Data Port caches.
1439 * Most fields are defined in BSpec volume 5c.2 Data Port / Messages /
1440 * Data Port Messages / Message Descriptor. Once again, "Slot Group
1441 * Select" and "Last Render Target" are part of the 6-bit message
1442 * control for Render Target Writes.
1445 GLuint binding_table_index
:8;
1446 GLuint msg_control
:3;
1447 GLuint slot_group_select
:1;
1448 GLuint last_render_target
:1;
1449 GLuint msg_control_pad
:1;
1452 GLuint header_present
:1;
1453 GLuint response_length
:5;
1454 GLuint msg_length
:4;
1456 GLuint end_of_thread
:1;