2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
37 /** Number of general purpose registers (VS, WM, etc) */
38 #define BRW_MAX_GRF 128
40 /** Number of message register file registers */
41 #define BRW_MAX_MRF 16
64 GLuint notify_enable
:1;
66 GLuint wc_flush_enable
:1;
67 GLuint depth_stall_enable
:1;
75 GLuint dest_addr_type
:1;
83 /* These seem to be passed around as function args, so it works out
84 * better to keep them as #defines:
86 #define BRW_FLUSH_READ_CACHE 0x1
87 #define BRW_FLUSH_STATE_CACHE 0x2
88 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
89 #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8
99 struct brw_binding_table_pointers
101 struct header header
;
110 struct brw_blend_constant_color
112 struct header header
;
113 GLfloat blend_constant_color
[4];
117 struct brw_depthbuffer
119 union header_union header
;
126 GLuint software_tiled_rendering_mode
:2;
127 GLuint depth_offset_disable
:1;
129 GLuint tiled_surface
:1;
131 GLuint surface_type
:3;
136 GLuint dword2_base_addr
;
141 GLuint mipmap_layout
:1;
152 GLuint min_array_element
:11;
159 struct brw_depthbuffer_g4x
161 union header_union header
;
168 GLuint software_tiled_rendering_mode
:2;
169 GLuint depth_offset_disable
:1;
171 GLuint tiled_surface
:1;
173 GLuint surface_type
:3;
178 GLuint dword2_base_addr
;
183 GLuint mipmap_layout
:1;
194 GLuint min_array_element
:11;
206 } dword5
; /* NEW in Integrated Graphics Device */
211 struct header header
;
220 struct brw_indexbuffer
226 GLuint index_format
:2;
227 GLuint cut_index_enable
:1;
239 /* NEW in Integrated Graphics Device */
240 struct brw_aa_line_parameters
242 struct header header
;
245 GLuint aa_coverage_slope
:8;
247 GLuint aa_coverage_bias
:8;
252 GLuint aa_coverage_endcap_slope
:8;
254 GLuint aa_coverage_endcap_bias
:8;
259 struct brw_line_stipple
261 struct header header
;
271 GLuint repeat_count
:9;
273 GLuint inverse_repeat_count
:16;
278 struct brw_pipelined_state_pointers
280 struct header header
;
284 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
291 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
298 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
304 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
310 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE */
316 GLuint offset
:27; /* Offset from GENERAL_STATE_BASE. KW: check me! */
321 struct brw_polygon_stipple_offset
323 struct header header
;
335 struct brw_polygon_stipple
337 struct header header
;
343 struct brw_pipeline_select
347 GLuint pipeline_select
:1;
354 struct brw_pipe_control
359 GLuint notify_enable
:1;
360 GLuint texture_cache_flush_enable
:1;
361 GLuint indirect_state_pointers_disable
:1;
362 GLuint instruction_state_cache_flush_enable
:1;
363 GLuint write_cache_flush_enable
:1;
364 GLuint depth_stall_enable
:1;
365 GLuint post_sync_operation
:2;
373 GLuint dest_addr_type
:1;
389 GLuint clp_realloc
:1;
391 GLuint vfe_realloc
:1;
414 struct brw_cs_urb_state
416 struct header header
;
420 GLuint nr_urb_entries
:3;
422 GLuint urb_entry_size
:5;
427 struct brw_constant_buffer
439 GLuint buffer_length
:6;
440 GLuint buffer_address
:26;
444 struct brw_state_base_address
446 struct header header
;
450 GLuint modify_enable
:1;
452 GLuint general_state_address
:27;
457 GLuint modify_enable
:1;
459 GLuint surface_state_address
:27;
464 GLuint modify_enable
:1;
466 GLuint indirect_object_state_address
:27;
471 GLuint modify_enable
:1;
473 GLuint general_state_upper_bound
:20;
478 GLuint modify_enable
:1;
480 GLuint indirect_object_state_upper_bound
:20;
484 struct brw_state_prefetch
486 struct header header
;
490 GLuint prefetch_count
:3;
492 GLuint prefetch_pointer
:26;
496 struct brw_system_instruction_pointer
498 struct header header
;
503 GLuint system_instruction_pointer
:28;
510 /* State structs for the various fixed function units:
517 GLuint grf_reg_count
:3;
519 GLuint kernel_start_pointer
:26; /* Offset from GENERAL_STATE_BASE */
524 GLuint ext_halt_exception_enable
:1;
525 GLuint sw_exception_enable
:1;
526 GLuint mask_stack_exception_enable
:1;
527 GLuint timeout_exception_enable
:1;
528 GLuint illegal_op_exception_enable
:1;
530 GLuint depth_coef_urb_read_offset
:6; /* WM only */
532 GLuint floating_point_mode
:1;
533 GLuint thread_priority
:1;
534 GLuint binding_table_entry_count
:8;
536 GLuint single_program_flow
:1;
541 GLuint per_thread_scratch_space
:4;
543 GLuint scratch_space_base_pointer
:22;
549 GLuint dispatch_grf_start_reg
:4;
550 GLuint urb_entry_read_offset
:6;
552 GLuint urb_entry_read_length
:6;
554 GLuint const_urb_entry_read_offset
:6;
556 GLuint const_urb_entry_read_length
:6;
562 struct brw_clip_unit_state
564 struct thread0 thread0
;
568 GLuint sw_exception_enable
:1;
570 GLuint mask_stack_exception_enable
:1;
572 GLuint illegal_op_exception_enable
:1;
574 GLuint floating_point_mode
:1;
575 GLuint thread_priority
:1;
576 GLuint binding_table_entry_count
:8;
578 GLuint single_program_flow
:1;
581 struct thread2 thread2
;
582 struct thread3 thread3
;
587 GLuint gs_output_stats
:1; /* not always */
588 GLuint stats_enable
:1;
589 GLuint nr_urb_entries
:7;
591 GLuint urb_entry_allocation_size
:5;
593 GLuint max_threads
:5; /* may be less */
601 GLuint userclip_enable_flags
:8;
602 GLuint userclip_must_clip
:1;
603 GLuint negative_w_clip_test
:1;
604 GLuint guard_band_enable
:1;
605 GLuint viewport_z_clip_enable
:1;
606 GLuint viewport_xy_clip_enable
:1;
607 GLuint vertex_position_space
:1;
615 GLuint clipper_viewport_state_ptr
:27;
619 GLfloat viewport_xmin
;
620 GLfloat viewport_xmax
;
621 GLfloat viewport_ymin
;
622 GLfloat viewport_ymax
;
625 struct gen6_blend_state
628 GLuint dest_blend_factor
:5;
629 GLuint source_blend_factor
:5;
633 GLuint ia_dest_blend_factor
:5;
634 GLuint ia_source_blend_factor
:5;
636 GLuint ia_blend_func
:3;
638 GLuint ia_blend_enable
:1;
639 GLuint blend_enable
:1;
643 GLuint post_blend_clamp_enable
:1;
644 GLuint pre_blend_clamp_enable
:1;
645 GLuint clamp_range
:2;
647 GLuint x_dither_offset
:2;
648 GLuint y_dither_offset
:2;
649 GLuint dither_enable
:1;
650 GLuint alpha_test_func
:3;
651 GLuint alpha_test_enable
:1;
653 GLuint logic_op_func
:4;
654 GLuint logic_op_enable
:1;
656 GLuint write_disable_b
:1;
657 GLuint write_disable_g
:1;
658 GLuint write_disable_r
:1;
659 GLuint write_disable_a
:1;
661 GLuint alpha_to_coverage_dither
:1;
662 GLuint alpha_to_one
:1;
663 GLuint alpha_to_coverage
:1;
667 struct gen6_color_calc_state
670 GLuint alpha_test_format
:1;
672 GLuint round_disable
:1;
673 GLuint bf_stencil_ref
:8;
674 GLuint stencil_ref
:8;
691 struct gen6_depth_stencil_state
695 GLuint bf_stencil_pass_depth_pass_op
:3;
696 GLuint bf_stencil_pass_depth_fail_op
:3;
697 GLuint bf_stencil_fail_op
:3;
698 GLuint bf_stencil_func
:3;
699 GLuint bf_stencil_enable
:1;
701 GLuint stencil_write_enable
:1;
702 GLuint stencil_pass_depth_pass_op
:3;
703 GLuint stencil_pass_depth_fail_op
:3;
704 GLuint stencil_fail_op
:3;
705 GLuint stencil_func
:3;
706 GLuint stencil_enable
:1;
710 GLuint bf_stencil_write_mask
:8;
711 GLuint bf_stencil_test_mask
:8;
712 GLuint stencil_write_mask
:8;
713 GLuint stencil_test_mask
:8;
718 GLuint depth_write_enable
:1;
719 GLuint depth_test_func
:3;
721 GLuint depth_test_enable
:1;
725 struct brw_cc_unit_state
730 GLuint bf_stencil_pass_depth_pass_op
:3;
731 GLuint bf_stencil_pass_depth_fail_op
:3;
732 GLuint bf_stencil_fail_op
:3;
733 GLuint bf_stencil_func
:3;
734 GLuint bf_stencil_enable
:1;
736 GLuint stencil_write_enable
:1;
737 GLuint stencil_pass_depth_pass_op
:3;
738 GLuint stencil_pass_depth_fail_op
:3;
739 GLuint stencil_fail_op
:3;
740 GLuint stencil_func
:3;
741 GLuint stencil_enable
:1;
747 GLuint bf_stencil_ref
:8;
748 GLuint stencil_write_mask
:8;
749 GLuint stencil_test_mask
:8;
750 GLuint stencil_ref
:8;
756 GLuint logicop_enable
:1;
758 GLuint depth_write_enable
:1;
759 GLuint depth_test_function
:3;
761 GLuint bf_stencil_write_mask
:8;
762 GLuint bf_stencil_test_mask
:8;
769 GLuint alpha_test_func
:3;
771 GLuint blend_enable
:1;
772 GLuint ia_blend_enable
:1;
774 GLuint alpha_test_format
:1;
781 GLuint cc_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
787 GLuint ia_dest_blend_factor
:5;
788 GLuint ia_src_blend_factor
:5;
789 GLuint ia_blend_function
:3;
790 GLuint statistics_enable
:1;
791 GLuint logicop_func
:4;
793 GLuint dither_enable
:1;
798 GLuint clamp_post_alpha_blend
:1;
799 GLuint clamp_pre_alpha_blend
:1;
800 GLuint clamp_range
:2;
802 GLuint y_dither_offset
:2;
803 GLuint x_dither_offset
:2;
804 GLuint dest_blend_factor
:5;
805 GLuint src_blend_factor
:5;
806 GLuint blend_function
:3;
817 struct brw_sf_unit_state
819 struct thread0 thread0
;
820 struct thread1 thread1
;
821 struct thread2 thread2
;
822 struct thread3 thread3
;
827 GLuint stats_enable
:1;
828 GLuint nr_urb_entries
:7;
830 GLuint urb_entry_allocation_size
:5;
832 GLuint max_threads
:6;
838 GLuint front_winding
:1;
839 GLuint viewport_transform
:1;
841 GLuint sf_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
847 GLuint dest_org_vbias
:4;
848 GLuint dest_org_hbias
:4;
850 GLuint disable_2x2_trifilter
:1;
851 GLuint disable_zero_pix_trifilter
:1;
852 GLuint point_rast_rule
:2;
853 GLuint line_endcap_aa_region_width
:2;
855 GLuint fast_scissor_disable
:1;
862 GLuint point_size
:11;
863 GLuint use_point_size_state
:1;
864 GLuint subpixel_precision
:1;
865 GLuint sprite_point
:1;
867 GLuint aa_line_distance_mode
:1;
869 GLuint linestrip_pv
:2;
870 GLuint tristrip_pv
:2;
871 GLuint line_last_pixel_enable
:1;
876 struct gen6_scissor_rect
884 struct brw_gs_unit_state
886 struct thread0 thread0
;
887 struct thread1 thread1
;
888 struct thread2 thread2
;
889 struct thread3 thread3
;
894 GLuint rendering_enable
:1; /* for Ironlake */
896 GLuint stats_enable
:1;
897 GLuint nr_urb_entries
:7;
899 GLuint urb_entry_allocation_size
:5;
901 GLuint max_threads
:5;
907 GLuint sampler_count
:3;
909 GLuint sampler_state_pointer
:27;
915 GLuint max_vp_index
:4;
917 GLuint svbi_post_inc_value
:10;
919 GLuint svbi_post_inc_enable
:1;
920 GLuint svbi_payload
:1;
921 GLuint discard_adjaceny
:1;
922 GLuint reorder_enable
:1;
928 struct brw_vs_unit_state
930 struct thread0 thread0
;
931 struct thread1 thread1
;
932 struct thread2 thread2
;
933 struct thread3 thread3
;
938 GLuint stats_enable
:1;
939 GLuint nr_urb_entries
:7;
941 GLuint urb_entry_allocation_size
:5;
943 GLuint max_threads
:6;
949 GLuint sampler_count
:3;
951 GLuint sampler_state_pointer
:27;
957 GLuint vert_cache_disable
:1;
963 struct brw_wm_unit_state
965 struct thread0 thread0
;
966 struct thread1 thread1
;
967 struct thread2 thread2
;
968 struct thread3 thread3
;
971 GLuint stats_enable
:1;
972 GLuint depth_buffer_clear
:1;
973 GLuint sampler_count
:3;
974 GLuint sampler_state_pointer
:27;
979 GLuint enable_8_pix
:1;
980 GLuint enable_16_pix
:1;
981 GLuint enable_32_pix
:1;
982 GLuint enable_con_32_pix
:1;
983 GLuint enable_con_64_pix
:1;
986 /* These next four bits are for Ironlake+ */
987 GLuint fast_span_coverage_enable
:1;
988 GLuint depth_buffer_clear
:1;
989 GLuint depth_buffer_resolve_enable
:1;
990 GLuint hierarchical_depth_buffer_resolve_enable
:1;
992 GLuint legacy_global_depth_bias
:1;
993 GLuint line_stipple
:1;
994 GLuint depth_offset
:1;
995 GLuint polygon_stipple
:1;
996 GLuint line_aa_region_width
:2;
997 GLuint line_endcap_aa_region_width
:2;
998 GLuint early_depth_test
:1;
999 GLuint thread_dispatch_enable
:1;
1000 GLuint program_uses_depth
:1;
1001 GLuint program_computes_depth
:1;
1002 GLuint program_uses_killpixel
:1;
1003 GLuint legacy_line_rast
: 1;
1004 GLuint transposed_urb_read_enable
:1;
1005 GLuint max_threads
:7;
1008 GLfloat global_depth_offset_constant
;
1009 GLfloat global_depth_offset_scale
;
1011 /* for Ironlake only */
1014 GLuint grf_reg_count_1
:3;
1016 GLuint kernel_start_pointer_1
:26;
1021 GLuint grf_reg_count_2
:3;
1023 GLuint kernel_start_pointer_2
:26;
1028 GLuint grf_reg_count_3
:3;
1030 GLuint kernel_start_pointer_3
:26;
1034 struct brw_sampler_default_color
{
1038 struct gen5_sampler_default_color
{
1047 struct brw_sampler_state
1052 GLuint shadow_function
:3;
1054 GLuint min_filter
:3;
1055 GLuint mag_filter
:3;
1056 GLuint mip_filter
:2;
1057 GLuint base_level
:5;
1058 GLuint min_mag_neq
:1;
1059 GLuint lod_preclamp
:1;
1060 GLuint default_color_mode
:1;
1067 GLuint r_wrap_mode
:3;
1068 GLuint t_wrap_mode
:3;
1069 GLuint s_wrap_mode
:3;
1070 GLuint cube_control_mode
:1;
1080 GLuint default_color_pointer
:27;
1085 GLuint non_normalized_coord
:1;
1087 GLuint address_round
:6;
1089 GLuint chroma_key_mode
:1;
1090 GLuint chroma_key_index
:2;
1091 GLuint chroma_key_enable
:1;
1092 GLuint monochrome_filter_width
:3;
1093 GLuint monochrome_filter_height
:3;
1097 struct gen7_sampler_state
1101 GLuint aniso_algorithm
:1;
1103 GLuint min_filter
:3;
1104 GLuint mag_filter
:3;
1105 GLuint mip_filter
:2;
1106 GLuint base_level
:5;
1108 GLuint lod_preclamp
:1;
1109 GLuint default_color_mode
:1;
1116 GLuint cube_control_mode
:1;
1117 GLuint shadow_function
:3;
1126 GLuint default_color_pointer
:27;
1131 GLuint r_wrap_mode
:3;
1132 GLuint t_wrap_mode
:3;
1133 GLuint s_wrap_mode
:3;
1135 GLuint non_normalized_coord
:1;
1136 GLuint trilinear_quality
:2;
1137 GLuint address_round
:6;
1139 GLuint chroma_key_mode
:1;
1140 GLuint chroma_key_index
:2;
1141 GLuint chroma_key_enable
:1;
1146 struct brw_clipper_viewport
1154 struct brw_cc_viewport
1160 struct brw_sf_viewport
1171 /* scissor coordinates are inclusive */
1180 struct gen6_sf_viewport
{
1189 struct gen7_sf_clip_viewport
{
1211 /* volume 5c Shared Functions - 1.13.4.1.2 */
1212 struct gen7_surface_state
1215 GLuint cube_pos_z
:1;
1216 GLuint cube_neg_z
:1;
1217 GLuint cube_pos_y
:1;
1218 GLuint cube_neg_y
:1;
1219 GLuint cube_pos_x
:1;
1220 GLuint cube_neg_x
:1;
1222 GLuint render_cache_read_write
:1;
1224 GLuint surface_array_spacing
:1;
1225 GLuint vert_line_stride_ofs
:1;
1226 GLuint vert_line_stride
:1;
1228 GLuint tiled_surface
:1;
1229 GLuint horizontal_alignment
:1;
1230 GLuint vertical_alignment
:2;
1231 GLuint surface_format
:9; /**< BRW_SURFACEFORMAT_x */
1234 GLuint surface_type
:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */
1255 GLuint multisample_position_palette_index
:3;
1256 GLuint num_multisamples
:3;
1257 GLuint multisampled_surface_storage_format
:1;
1258 GLuint render_target_view_extent
:11;
1259 GLuint min_array_elt
:11;
1274 GLuint pad
; /* Multisample Control Surface stuff */
1278 GLuint resource_min_lod
:12;
1280 GLuint alpha_clear_color
:1;
1281 GLuint blue_clear_color
:1;
1282 GLuint green_clear_color
:1;
1283 GLuint red_clear_color
:1;
1288 struct brw_vertex_element_state
1292 GLuint src_offset
:11;
1294 GLuint src_format
:9;
1297 GLuint vertex_buffer_index
:5;
1302 GLuint dst_offset
:8;
1304 GLuint vfcomponent3
:4;
1305 GLuint vfcomponent2
:4;
1306 GLuint vfcomponent1
:4;
1307 GLuint vfcomponent0
:4;
1311 #define BRW_VEP_MAX 18
1313 struct brw_vertex_element_packet
{
1314 struct header header
;
1315 struct brw_vertex_element_state ve
[BRW_VEP_MAX
]; /* note: less than _TNL_ATTRIB_MAX */
1319 struct brw_urb_immediate
{
1322 GLuint swizzle_control
:2;
1327 GLuint response_length
:4;
1328 GLuint msg_length
:4;
1329 GLuint msg_target
:4;
1331 GLuint end_of_thread
:1;
1334 /* Instruction format for the execution units:
1337 struct brw_instruction
1343 GLuint access_mode
:1;
1344 GLuint mask_control
:1;
1345 GLuint dependency_control
:2;
1346 GLuint compression_control
:2; /* gen6: quater control */
1347 GLuint thread_control
:2;
1348 GLuint predicate_control
:4;
1349 GLuint predicate_inverse
:1;
1350 GLuint execution_size
:3;
1351 GLuint destreg__conditionalmod
:4; /* destreg - send, conditionalmod - others */
1352 GLuint acc_wr_control
:1;
1353 GLuint cmpt_control
:1;
1354 GLuint debug_control
:1;
1361 GLuint dest_reg_file
:2;
1362 GLuint dest_reg_type
:3;
1363 GLuint src0_reg_file
:2;
1364 GLuint src0_reg_type
:3;
1365 GLuint src1_reg_file
:2;
1366 GLuint src1_reg_type
:3;
1368 GLuint dest_subreg_nr
:5;
1369 GLuint dest_reg_nr
:8;
1370 GLuint dest_horiz_stride
:2;
1371 GLuint dest_address_mode
:1;
1376 GLuint dest_reg_file
:2;
1377 GLuint dest_reg_type
:3;
1378 GLuint src0_reg_file
:2;
1379 GLuint src0_reg_type
:3;
1380 GLuint src1_reg_file
:2; /* 0x00000c00 */
1381 GLuint src1_reg_type
:3; /* 0x00007000 */
1383 GLint dest_indirect_offset
:10; /* offset against the deref'd address reg */
1384 GLuint dest_subreg_nr
:3; /* subnr for the address reg a0.x */
1385 GLuint dest_horiz_stride
:2;
1386 GLuint dest_address_mode
:1;
1391 GLuint dest_reg_file
:2;
1392 GLuint dest_reg_type
:3;
1393 GLuint src0_reg_file
:2;
1394 GLuint src0_reg_type
:3;
1395 GLuint src1_reg_file
:2;
1396 GLuint src1_reg_type
:3;
1398 GLuint dest_writemask
:4;
1399 GLuint dest_subreg_nr
:1;
1400 GLuint dest_reg_nr
:8;
1401 GLuint dest_horiz_stride
:2;
1402 GLuint dest_address_mode
:1;
1407 GLuint dest_reg_file
:2;
1408 GLuint dest_reg_type
:3;
1409 GLuint src0_reg_file
:2;
1410 GLuint src0_reg_type
:3;
1412 GLuint dest_writemask
:4;
1413 GLint dest_indirect_offset
:6;
1414 GLuint dest_subreg_nr
:3;
1415 GLuint dest_horiz_stride
:2;
1416 GLuint dest_address_mode
:1;
1420 GLuint dest_reg_file
:2;
1421 GLuint dest_reg_type
:3;
1422 GLuint src0_reg_file
:2;
1423 GLuint src0_reg_type
:3;
1424 GLuint src1_reg_file
:2;
1425 GLuint src1_reg_type
:3;
1428 GLint jump_count
:16;
1436 GLuint src0_subreg_nr
:5;
1437 GLuint src0_reg_nr
:8;
1439 GLuint src0_negate
:1;
1440 GLuint src0_address_mode
:1;
1441 GLuint src0_horiz_stride
:2;
1442 GLuint src0_width
:3;
1443 GLuint src0_vert_stride
:4;
1444 GLuint flag_reg_nr
:1;
1450 GLint src0_indirect_offset
:10;
1451 GLuint src0_subreg_nr
:3;
1453 GLuint src0_negate
:1;
1454 GLuint src0_address_mode
:1;
1455 GLuint src0_horiz_stride
:2;
1456 GLuint src0_width
:3;
1457 GLuint src0_vert_stride
:4;
1458 GLuint flag_reg_nr
:1;
1464 GLuint src0_swz_x
:2;
1465 GLuint src0_swz_y
:2;
1466 GLuint src0_subreg_nr
:1;
1467 GLuint src0_reg_nr
:8;
1469 GLuint src0_negate
:1;
1470 GLuint src0_address_mode
:1;
1471 GLuint src0_swz_z
:2;
1472 GLuint src0_swz_w
:2;
1474 GLuint src0_vert_stride
:4;
1475 GLuint flag_reg_nr
:1;
1481 GLuint src0_swz_x
:2;
1482 GLuint src0_swz_y
:2;
1483 GLint src0_indirect_offset
:6;
1484 GLuint src0_subreg_nr
:3;
1486 GLuint src0_negate
:1;
1487 GLuint src0_address_mode
:1;
1488 GLuint src0_swz_z
:2;
1489 GLuint src0_swz_w
:2;
1491 GLuint src0_vert_stride
:4;
1492 GLuint flag_reg_nr
:1;
1499 GLuint end_of_thread
:1;
1502 } send_gen5
; /* for Ironlake only */
1510 GLuint src1_subreg_nr
:5;
1511 GLuint src1_reg_nr
:8;
1513 GLuint src1_negate
:1;
1514 GLuint src1_address_mode
:1;
1515 GLuint src1_horiz_stride
:2;
1516 GLuint src1_width
:3;
1517 GLuint src1_vert_stride
:4;
1523 GLuint src1_swz_x
:2;
1524 GLuint src1_swz_y
:2;
1525 GLuint src1_subreg_nr
:1;
1526 GLuint src1_reg_nr
:8;
1528 GLuint src1_negate
:1;
1529 GLuint src1_address_mode
:1;
1530 GLuint src1_swz_z
:2;
1531 GLuint src1_swz_w
:2;
1533 GLuint src1_vert_stride
:4;
1539 GLint src1_indirect_offset
:10;
1540 GLuint src1_subreg_nr
:3;
1542 GLuint src1_negate
:1;
1543 GLuint src1_address_mode
:1;
1544 GLuint src1_horiz_stride
:2;
1545 GLuint src1_width
:3;
1546 GLuint src1_vert_stride
:4;
1547 GLuint flag_reg_nr
:1;
1553 GLuint src1_swz_x
:2;
1554 GLuint src1_swz_y
:2;
1555 GLint src1_indirect_offset
:6;
1556 GLuint src1_subreg_nr
:3;
1558 GLuint src1_negate
:1;
1560 GLuint src1_swz_z
:2;
1561 GLuint src1_swz_w
:2;
1563 GLuint src1_vert_stride
:4;
1564 GLuint flag_reg_nr
:1;
1571 GLint jump_count
:16; /* note: signed */
1576 /* This is also used for gen7 IF/ELSE instructions */
1579 /* Signed jump distance to the ip to jump to if all channels
1580 * are disabled after the break or continue. It should point
1581 * to the end of the innermost control flow block, as that's
1582 * where some channel could get re-enabled.
1586 /* Signed jump distance to the location to resume execution
1587 * of this channel if it's enabled for the break or continue.
1599 GLuint response_length
:4;
1600 GLuint msg_length
:4;
1601 GLuint msg_target
:4;
1603 GLuint end_of_thread
:1;
1614 GLuint header_present
:1;
1615 GLuint response_length
:5;
1616 GLuint msg_length
:4;
1618 GLuint end_of_thread
:1;
1622 GLuint binding_table_index
:8;
1624 GLuint return_format
:2;
1626 GLuint response_length
:4;
1627 GLuint msg_length
:4;
1628 GLuint msg_target
:4;
1630 GLuint end_of_thread
:1;
1634 GLuint binding_table_index
:8;
1637 GLuint response_length
:4;
1638 GLuint msg_length
:4;
1639 GLuint msg_target
:4;
1641 GLuint end_of_thread
:1;
1645 GLuint binding_table_index
:8;
1650 GLuint header_present
:1;
1651 GLuint response_length
:5;
1652 GLuint msg_length
:4;
1654 GLuint end_of_thread
:1;
1658 GLuint binding_table_index
:8;
1662 GLuint header_present
:1;
1663 GLuint response_length
:5;
1664 GLuint msg_length
:4;
1666 GLuint end_of_thread
:1;
1669 struct brw_urb_immediate urb
;
1674 GLuint swizzle_control
:2;
1680 GLuint header_present
:1;
1681 GLuint response_length
:5;
1682 GLuint msg_length
:4;
1684 GLuint end_of_thread
:1;
1690 GLuint swizzle_control
:1;
1692 GLuint per_slot_offset
:1;
1694 GLuint header_present
:1;
1695 GLuint response_length
:5;
1696 GLuint msg_length
:4;
1698 GLuint end_of_thread
:1;
1702 GLuint binding_table_index
:8;
1703 GLuint msg_control
:4;
1705 GLuint target_cache
:2;
1706 GLuint response_length
:4;
1707 GLuint msg_length
:4;
1708 GLuint msg_target
:4;
1710 GLuint end_of_thread
:1;
1714 GLuint binding_table_index
:8;
1715 GLuint msg_control
:3;
1717 GLuint target_cache
:2;
1718 GLuint response_length
:4;
1719 GLuint msg_length
:4;
1720 GLuint msg_target
:4;
1722 GLuint end_of_thread
:1;
1726 GLuint binding_table_index
:8;
1727 GLuint msg_control
:3;
1729 GLuint target_cache
:2;
1731 GLuint header_present
:1;
1732 GLuint response_length
:5;
1733 GLuint msg_length
:4;
1735 GLuint end_of_thread
:1;
1739 GLuint binding_table_index
:8;
1740 GLuint msg_control
:3;
1741 GLuint pixel_scoreboard_clear
:1;
1743 GLuint send_commit_msg
:1;
1744 GLuint response_length
:4;
1745 GLuint msg_length
:4;
1746 GLuint msg_target
:4;
1748 GLuint end_of_thread
:1;
1752 GLuint binding_table_index
:8;
1753 GLuint msg_control
:3;
1754 GLuint pixel_scoreboard_clear
:1;
1756 GLuint send_commit_msg
:1;
1758 GLuint header_present
:1;
1759 GLuint response_length
:5;
1760 GLuint msg_length
:4;
1762 GLuint end_of_thread
:1;
1765 /* Sandybridge DP for sample cache, constant cache, render cache */
1767 GLuint binding_table_index
:8;
1768 GLuint msg_control
:5;
1771 GLuint header_present
:1;
1772 GLuint response_length
:5;
1773 GLuint msg_length
:4;
1775 GLuint end_of_thread
:1;
1776 } dp_sampler_const_cache
;
1779 GLuint binding_table_index
:8;
1780 GLuint msg_control
:3;
1781 GLuint slot_group_select
:1;
1782 GLuint pixel_scoreboard_clear
:1;
1784 GLuint send_commit_msg
:1;
1786 GLuint header_present
:1;
1787 GLuint response_length
:5;
1788 GLuint msg_length
:4;
1790 GLuint end_of_thread
:1;
1793 /* See volume vol5c.2 sections 2.11.2.1.5 and 2.11.21.2.2. */
1795 GLuint binding_table_index
:8;
1796 GLuint msg_control
:3;
1797 GLuint slot_group_select
:1;
1798 GLuint pixel_scoreboard_clear
:1;
1802 GLuint header_present
:1;
1803 GLuint response_length
:5;
1804 GLuint msg_length
:4;
1806 GLuint end_of_thread
:1;
1810 GLuint function_control
:16;
1811 GLuint response_length
:4;
1812 GLuint msg_length
:4;
1813 GLuint msg_target
:4;
1815 GLuint end_of_thread
:1;
1818 /* Of this struct, only end_of_thread is not present for gen6. */
1820 GLuint function_control
:19;
1821 GLuint header_present
:1;
1822 GLuint response_length
:5;
1823 GLuint msg_length
:4;
1825 GLuint end_of_thread
:1;