src/mesa/drivers/dri/i965/brw_structs.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_STRUCTS_H
  34 #define BRW_STRUCTS_H
  35
  36 struct brw_urb_fence
  37 {
  38    struct
  39    {
  40       GLuint length:8;
  41       GLuint vs_realloc:1;
  42       GLuint gs_realloc:1;
  43       GLuint clp_realloc:1;
  44       GLuint sf_realloc:1;
  45       GLuint vfe_realloc:1;
  46       GLuint cs_realloc:1;
  47       GLuint pad:2;
  48       GLuint opcode:16;
  49    } header;
  50
  51    struct
  52    {
  53       GLuint vs_fence:10;
  54       GLuint gs_fence:10;
  55       GLuint clp_fence:10;
  56       GLuint pad:2;
  57    } bits0;
  58
  59    struct
  60    {
  61       GLuint sf_fence:10;
  62       GLuint vf_fence:10;
  63       GLuint cs_fence:11;
  64       GLuint pad:1;
  65    } bits1;
  66 };
  67
  68 /* State structs for the various fixed function units:
  69  */
  70
  71
  72 struct thread0
  73 {
  74    GLuint pad0:1;
  75    GLuint grf_reg_count:3;
  76    GLuint pad1:2;
  77    GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
  78 };
  79
  80 struct thread1
  81 {
  82    GLuint ext_halt_exception_enable:1;
  83    GLuint sw_exception_enable:1;
  84    GLuint mask_stack_exception_enable:1;
  85    GLuint timeout_exception_enable:1;
  86    GLuint illegal_op_exception_enable:1;
  87    GLuint pad0:3;
  88    GLuint depth_coef_urb_read_offset:6; /* WM only */
  89    GLuint pad1:2;
  90    GLuint floating_point_mode:1;
  91    GLuint thread_priority:1;
  92    GLuint binding_table_entry_count:8;
  93    GLuint pad3:5;
  94    GLuint single_program_flow:1;
  95 };
  96
  97 struct thread2
  98 {
  99    GLuint per_thread_scratch_space:4;
 100    GLuint pad0:6;
 101    GLuint scratch_space_base_pointer:22;
 102 };
 103
 104
 105 struct thread3
 106 {
 107    GLuint dispatch_grf_start_reg:4;
 108    GLuint urb_entry_read_offset:6;
 109    GLuint pad0:1;
 110    GLuint urb_entry_read_length:6;
 111    GLuint pad1:1;
 112    GLuint const_urb_entry_read_offset:6;
 113    GLuint pad2:1;
 114    GLuint const_urb_entry_read_length:6;
 115    GLuint pad3:1;
 116 };
 117
 118
 119
 120 struct brw_clip_unit_state
 121 {
 122    struct thread0 thread0;
 123    struct
 124    {
 125       GLuint pad0:7;
 126       GLuint sw_exception_enable:1;
 127       GLuint pad1:3;
 128       GLuint mask_stack_exception_enable:1;
 129       GLuint pad2:1;
 130       GLuint illegal_op_exception_enable:1;
 131       GLuint pad3:2;
 132       GLuint floating_point_mode:1;
 133       GLuint thread_priority:1;
 134       GLuint binding_table_entry_count:8;
 135       GLuint pad4:5;
 136       GLuint single_program_flow:1;
 137    } thread1;
 138
 139    struct thread2 thread2;
 140    struct thread3 thread3;
 141
 142    struct
 143    {
 144       GLuint pad0:9;
 145       GLuint gs_output_stats:1; /* not always */
 146       GLuint stats_enable:1;
 147       GLuint nr_urb_entries:7;
 148       GLuint pad1:1;
 149       GLuint urb_entry_allocation_size:5;
 150       GLuint pad2:1;
 151       GLuint max_threads:5;     /* may be less */
 152       GLuint pad3:2;
 153    } thread4;
 154
 155    struct
 156    {
 157       GLuint pad0:13;
 158       GLuint clip_mode:3;
 159       GLuint userclip_enable_flags:8;
 160       GLuint userclip_must_clip:1;
 161       GLuint negative_w_clip_test:1;
 162       GLuint guard_band_enable:1;
 163       GLuint viewport_z_clip_enable:1;
 164       GLuint viewport_xy_clip_enable:1;
 165       GLuint vertex_position_space:1;
 166       GLuint api_mode:1;
 167       GLuint pad2:1;
 168    } clip5;
 169
 170    struct
 171    {
 172       GLuint pad0:5;
 173       GLuint clipper_viewport_state_ptr:27;
 174    } clip6;
 175
 176
 177    GLfloat viewport_xmin;
 178    GLfloat viewport_xmax;
 179    GLfloat viewport_ymin;
 180    GLfloat viewport_ymax;
 181 };
 182
 183 struct gen6_blend_state
 184 {
 185    struct {
 186       GLuint dest_blend_factor:5;
 187       GLuint source_blend_factor:5;
 188       GLuint pad3:1;
 189       GLuint blend_func:3;
 190       GLuint pad2:1;
 191       GLuint ia_dest_blend_factor:5;
 192       GLuint ia_source_blend_factor:5;
 193       GLuint pad1:1;
 194       GLuint ia_blend_func:3;
 195       GLuint pad0:1;
 196       GLuint ia_blend_enable:1;
 197       GLuint blend_enable:1;
 198    } blend0;
 199
 200    struct {
 201       GLuint post_blend_clamp_enable:1;
 202       GLuint pre_blend_clamp_enable:1;
 203       GLuint clamp_range:2;
 204       GLuint pad0:4;
 205       GLuint x_dither_offset:2;
 206       GLuint y_dither_offset:2;
 207       GLuint dither_enable:1;
 208       GLuint alpha_test_func:3;
 209       GLuint alpha_test_enable:1;
 210       GLuint pad1:1;
 211       GLuint logic_op_func:4;
 212       GLuint logic_op_enable:1;
 213       GLuint pad2:1;
 214       GLuint write_disable_b:1;
 215       GLuint write_disable_g:1;
 216       GLuint write_disable_r:1;
 217       GLuint write_disable_a:1;
 218       GLuint pad3:1;
 219       GLuint alpha_to_coverage_dither:1;
 220       GLuint alpha_to_one:1;
 221       GLuint alpha_to_coverage:1;
 222    } blend1;
 223 };
 224
 225 struct gen6_color_calc_state
 226 {
 227    struct {
 228       GLuint alpha_test_format:1;
 229       GLuint pad0:14;
 230       GLuint round_disable:1;
 231       GLuint bf_stencil_ref:8;
 232       GLuint stencil_ref:8;
 233    } cc0;
 234
 235    union {
 236       GLfloat alpha_ref_f;
 237       struct {
 238          GLuint ui:8;
 239          GLuint pad0:24;
 240       } alpha_ref_fi;
 241    } cc1;
 242
 243    GLfloat constant_r;
 244    GLfloat constant_g;
 245    GLfloat constant_b;
 246    GLfloat constant_a;
 247 };
 248
 249 struct gen6_depth_stencil_state
 250 {
 251    struct {
 252       GLuint pad0:3;
 253       GLuint bf_stencil_pass_depth_pass_op:3;
 254       GLuint bf_stencil_pass_depth_fail_op:3;
 255       GLuint bf_stencil_fail_op:3;
 256       GLuint bf_stencil_func:3;
 257       GLuint bf_stencil_enable:1;
 258       GLuint pad1:2;
 259       GLuint stencil_write_enable:1;
 260       GLuint stencil_pass_depth_pass_op:3;
 261       GLuint stencil_pass_depth_fail_op:3;
 262       GLuint stencil_fail_op:3;
 263       GLuint stencil_func:3;
 264       GLuint stencil_enable:1;
 265    } ds0;
 266
 267    struct {
 268       GLuint bf_stencil_write_mask:8;
 269       GLuint bf_stencil_test_mask:8;
 270       GLuint stencil_write_mask:8;
 271       GLuint stencil_test_mask:8;
 272    } ds1;
 273
 274    struct {
 275       GLuint pad0:26;
 276       GLuint depth_write_enable:1;
 277       GLuint depth_test_func:3;
 278       GLuint pad1:1;
 279       GLuint depth_test_enable:1;
 280    } ds2;
 281 };
 282
 283 struct brw_cc_unit_state
 284 {
 285    struct
 286    {
 287       GLuint pad0:3;
 288       GLuint bf_stencil_pass_depth_pass_op:3;
 289       GLuint bf_stencil_pass_depth_fail_op:3;
 290       GLuint bf_stencil_fail_op:3;
 291       GLuint bf_stencil_func:3;
 292       GLuint bf_stencil_enable:1;
 293       GLuint pad1:2;
 294       GLuint stencil_write_enable:1;
 295       GLuint stencil_pass_depth_pass_op:3;
 296       GLuint stencil_pass_depth_fail_op:3;
 297       GLuint stencil_fail_op:3;
 298       GLuint stencil_func:3;
 299       GLuint stencil_enable:1;
 300    } cc0;
 301
 302
 303    struct
 304    {
 305       GLuint bf_stencil_ref:8;
 306       GLuint stencil_write_mask:8;
 307       GLuint stencil_test_mask:8;
 308       GLuint stencil_ref:8;
 309    } cc1;
 310
 311
 312    struct
 313    {
 314       GLuint logicop_enable:1;
 315       GLuint pad0:10;
 316       GLuint depth_write_enable:1;
 317       GLuint depth_test_function:3;
 318       GLuint depth_test:1;
 319       GLuint bf_stencil_write_mask:8;
 320       GLuint bf_stencil_test_mask:8;
 321    } cc2;
 322
 323
 324    struct
 325    {
 326       GLuint pad0:8;
 327       GLuint alpha_test_func:3;
 328       GLuint alpha_test:1;
 329       GLuint blend_enable:1;
 330       GLuint ia_blend_enable:1;
 331       GLuint pad1:1;
 332       GLuint alpha_test_format:1;
 333       GLuint pad2:16;
 334    } cc3;
 335
 336    struct
 337    {
 338       GLuint pad0:5;
 339       GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 340    } cc4;
 341
 342    struct
 343    {
 344       GLuint pad0:2;
 345       GLuint ia_dest_blend_factor:5;
 346       GLuint ia_src_blend_factor:5;
 347       GLuint ia_blend_function:3;
 348       GLuint statistics_enable:1;
 349       GLuint logicop_func:4;
 350       GLuint pad1:11;
 351       GLuint dither_enable:1;
 352    } cc5;
 353
 354    struct
 355    {
 356       GLuint clamp_post_alpha_blend:1;
 357       GLuint clamp_pre_alpha_blend:1;
 358       GLuint clamp_range:2;
 359       GLuint pad0:11;
 360       GLuint y_dither_offset:2;
 361       GLuint x_dither_offset:2;
 362       GLuint dest_blend_factor:5;
 363       GLuint src_blend_factor:5;
 364       GLuint blend_function:3;
 365    } cc6;
 366
 367    struct {
 368       union {
 369          GLfloat f;
 370          GLubyte ub[4];
 371       } alpha_ref;
 372    } cc7;
 373 };
 374
 375 struct brw_sf_unit_state
 376 {
 377    struct thread0 thread0;
 378    struct thread1 thread1;
 379    struct thread2 thread2;
 380    struct thread3 thread3;
 381
 382    struct
 383    {
 384       GLuint pad0:10;
 385       GLuint stats_enable:1;
 386       GLuint nr_urb_entries:7;
 387       GLuint pad1:1;
 388       GLuint urb_entry_allocation_size:5;
 389       GLuint pad2:1;
 390       GLuint max_threads:6;
 391       GLuint pad3:1;
 392    } thread4;
 393
 394    struct
 395    {
 396       GLuint front_winding:1;
 397       GLuint viewport_transform:1;
 398       GLuint pad0:3;
 399       GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 400    } sf5;
 401
 402    struct
 403    {
 404       GLuint pad0:9;
 405       GLuint dest_org_vbias:4;
 406       GLuint dest_org_hbias:4;
 407       GLuint scissor:1;
 408       GLuint disable_2x2_trifilter:1;
 409       GLuint disable_zero_pix_trifilter:1;
 410       GLuint point_rast_rule:2;
 411       GLuint line_endcap_aa_region_width:2;
 412       GLuint line_width:4;
 413       GLuint fast_scissor_disable:1;
 414       GLuint cull_mode:2;
 415       GLuint aa_enable:1;
 416    } sf6;
 417
 418    struct
 419    {
 420       GLuint point_size:11;
 421       GLuint use_point_size_state:1;
 422       GLuint subpixel_precision:1;
 423       GLuint sprite_point:1;
 424       GLuint pad0:10;
 425       GLuint aa_line_distance_mode:1;
 426       GLuint trifan_pv:2;
 427       GLuint linestrip_pv:2;
 428       GLuint tristrip_pv:2;
 429       GLuint line_last_pixel_enable:1;
 430    } sf7;
 431
 432 };
 433
 434 struct gen6_scissor_rect
 435 {
 436    GLuint xmin:16;
 437    GLuint ymin:16;
 438    GLuint xmax:16;
 439    GLuint ymax:16;
 440 };
 441
 442 struct brw_gs_unit_state
 443 {
 444    struct thread0 thread0;
 445    struct thread1 thread1;
 446    struct thread2 thread2;
 447    struct thread3 thread3;
 448
 449    struct
 450    {
 451       GLuint pad0:8;
 452       GLuint rendering_enable:1; /* for Ironlake */
 453       GLuint pad4:1;
 454       GLuint stats_enable:1;
 455       GLuint nr_urb_entries:7;
 456       GLuint pad1:1;
 457       GLuint urb_entry_allocation_size:5;
 458       GLuint pad2:1;
 459       GLuint max_threads:5;
 460       GLuint pad3:2;
 461    } thread4;
 462
 463    struct
 464    {
 465       GLuint sampler_count:3;
 466       GLuint pad0:2;
 467       GLuint sampler_state_pointer:27;
 468    } gs5;
 469
 470
 471    struct
 472    {
 473       GLuint max_vp_index:4;
 474       GLuint pad0:12;
 475       GLuint svbi_post_inc_value:10;
 476       GLuint pad1:1;
 477       GLuint svbi_post_inc_enable:1;
 478       GLuint svbi_payload:1;
 479       GLuint discard_adjaceny:1;
 480       GLuint reorder_enable:1;
 481       GLuint pad2:1;
 482    } gs6;
 483 };
 484
 485
 486 struct brw_vs_unit_state
 487 {
 488    struct thread0 thread0;
 489    struct thread1 thread1;
 490    struct thread2 thread2;
 491    struct thread3 thread3;
 492
 493    struct
 494    {
 495       GLuint pad0:10;
 496       GLuint stats_enable:1;
 497       GLuint nr_urb_entries:7;
 498       GLuint pad1:1;
 499       GLuint urb_entry_allocation_size:5;
 500       GLuint pad2:1;
 501       GLuint max_threads:6;
 502       GLuint pad3:1;
 503    } thread4;
 504
 505    struct
 506    {
 507       GLuint sampler_count:3;
 508       GLuint pad0:2;
 509       GLuint sampler_state_pointer:27;
 510    } vs5;
 511
 512    struct
 513    {
 514       GLuint vs_enable:1;
 515       GLuint vert_cache_disable:1;
 516       GLuint pad0:30;
 517    } vs6;
 518 };
 519
 520
 521 struct brw_wm_unit_state
 522 {
 523    struct thread0 thread0;
 524    struct thread1 thread1;
 525    struct thread2 thread2;
 526    struct thread3 thread3;
 527
 528    struct {
 529       GLuint stats_enable:1;
 530       GLuint depth_buffer_clear:1;
 531       GLuint sampler_count:3;
 532       GLuint sampler_state_pointer:27;
 533    } wm4;
 534
 535    struct
 536    {
 537       GLuint enable_8_pix:1;
 538       GLuint enable_16_pix:1;
 539       GLuint enable_32_pix:1;
 540       GLuint enable_con_32_pix:1;
 541       GLuint enable_con_64_pix:1;
 542       GLuint pad0:1;
 543
 544       /* These next four bits are for Ironlake+ */
 545       GLuint fast_span_coverage_enable:1;
 546       GLuint depth_buffer_clear:1;
 547       GLuint depth_buffer_resolve_enable:1;
 548       GLuint hierarchical_depth_buffer_resolve_enable:1;
 549
 550       GLuint legacy_global_depth_bias:1;
 551       GLuint line_stipple:1;
 552       GLuint depth_offset:1;
 553       GLuint polygon_stipple:1;
 554       GLuint line_aa_region_width:2;
 555       GLuint line_endcap_aa_region_width:2;
 556       GLuint early_depth_test:1;
 557       GLuint thread_dispatch_enable:1;
 558       GLuint program_uses_depth:1;
 559       GLuint program_computes_depth:1;
 560       GLuint program_uses_killpixel:1;
 561       GLuint legacy_line_rast: 1;
 562       GLuint transposed_urb_read_enable:1;
 563       GLuint max_threads:7;
 564    } wm5;
 565
 566    GLfloat global_depth_offset_constant;
 567    GLfloat global_depth_offset_scale;
 568
 569    /* for Ironlake only */
 570    struct {
 571       GLuint pad0:1;
 572       GLuint grf_reg_count_1:3;
 573       GLuint pad1:2;
 574       GLuint kernel_start_pointer_1:26;
 575    } wm8;
 576
 577    struct {
 578       GLuint pad0:1;
 579       GLuint grf_reg_count_2:3;
 580       GLuint pad1:2;
 581       GLuint kernel_start_pointer_2:26;
 582    } wm9;
 583
 584    struct {
 585       GLuint pad0:1;
 586       GLuint grf_reg_count_3:3;
 587       GLuint pad1:2;
 588       GLuint kernel_start_pointer_3:26;
 589    } wm10;
 590 };
 591
 592 struct brw_sampler_default_color {
 593    GLfloat color[4];
 594 };
 595
 596 struct gen5_sampler_default_color {
 597    uint8_t ub[4];
 598    float f[4];
 599    uint16_t hf[4];
 600    uint16_t us[4];
 601    int16_t s[4];
 602    uint8_t b[4];
 603 };
 604
 605 struct brw_sampler_state
 606 {
 607
 608    struct
 609    {
 610       GLuint shadow_function:3;
 611       GLuint lod_bias:11;
 612       GLuint min_filter:3;
 613       GLuint mag_filter:3;
 614       GLuint mip_filter:2;
 615       GLuint base_level:5;
 616       GLuint min_mag_neq:1;
 617       GLuint lod_preclamp:1;
 618       GLuint default_color_mode:1;
 619       GLuint pad0:1;
 620       GLuint disable:1;
 621    } ss0;
 622
 623    struct
 624    {
 625       GLuint r_wrap_mode:3;
 626       GLuint t_wrap_mode:3;
 627       GLuint s_wrap_mode:3;
 628       GLuint cube_control_mode:1;
 629       GLuint pad:2;
 630       GLuint max_lod:10;
 631       GLuint min_lod:10;
 632    } ss1;
 633
 634
 635    struct
 636    {
 637       GLuint pad:5;
 638       GLuint default_color_pointer:27;
 639    } ss2;
 640
 641    struct
 642    {
 643       GLuint non_normalized_coord:1;
 644       GLuint pad:12;
 645       GLuint address_round:6;
 646       GLuint max_aniso:3;
 647       GLuint chroma_key_mode:1;
 648       GLuint chroma_key_index:2;
 649       GLuint chroma_key_enable:1;
 650       GLuint monochrome_filter_width:3;
 651       GLuint monochrome_filter_height:3;
 652    } ss3;
 653 };
 654
 655 struct gen7_sampler_state
 656 {
 657    struct
 658    {
 659       GLuint aniso_algorithm:1;
 660       GLuint lod_bias:13;
 661       GLuint min_filter:3;
 662       GLuint mag_filter:3;
 663       GLuint mip_filter:2;
 664       GLuint base_level:5;
 665       GLuint pad1:1;
 666       GLuint lod_preclamp:1;
 667       GLuint default_color_mode:1;
 668       GLuint pad0:1;
 669       GLuint disable:1;
 670    } ss0;
 671
 672    struct
 673    {
 674       GLuint cube_control_mode:1;
 675       GLuint shadow_function:3;
 676       GLuint pad:4;
 677       GLuint max_lod:12;
 678       GLuint min_lod:12;
 679    } ss1;
 680
 681    struct
 682    {
 683       GLuint pad:5;
 684       GLuint default_color_pointer:27;
 685    } ss2;
 686
 687    struct
 688    {
 689       GLuint r_wrap_mode:3;
 690       GLuint t_wrap_mode:3;
 691       GLuint s_wrap_mode:3;
 692       GLuint pad:1;
 693       GLuint non_normalized_coord:1;
 694       GLuint trilinear_quality:2;
 695       GLuint address_round:6;
 696       GLuint max_aniso:3;
 697       GLuint chroma_key_mode:1;
 698       GLuint chroma_key_index:2;
 699       GLuint chroma_key_enable:1;
 700       GLuint pad0:6;
 701    } ss3;
 702 };
 703
 704 struct brw_clipper_viewport
 705 {
 706    GLfloat xmin;
 707    GLfloat xmax;
 708    GLfloat ymin;
 709    GLfloat ymax;
 710 };
 711
 712 struct brw_cc_viewport
 713 {
 714    GLfloat min_depth;
 715    GLfloat max_depth;
 716 };
 717
 718 struct brw_sf_viewport
 719 {
 720    struct {
 721       GLfloat m00;
 722       GLfloat m11;
 723       GLfloat m22;
 724       GLfloat m30;
 725       GLfloat m31;
 726       GLfloat m32;
 727    } viewport;
 728
 729    /* scissor coordinates are inclusive */
 730    struct {
 731       GLshort xmin;
 732       GLshort ymin;
 733       GLshort xmax;
 734       GLshort ymax;
 735    } scissor;
 736 };
 737
 738 struct gen6_sf_viewport {
 739    GLfloat m00;
 740    GLfloat m11;
 741    GLfloat m22;
 742    GLfloat m30;
 743    GLfloat m31;
 744    GLfloat m32;
 745 };
 746
 747 struct gen7_sf_clip_viewport {
 748    struct {
 749       GLfloat m00;
 750       GLfloat m11;
 751       GLfloat m22;
 752       GLfloat m30;
 753       GLfloat m31;
 754       GLfloat m32;
 755    } viewport;
 756
 757    GLuint pad0[2];
 758
 759    struct {
 760       GLfloat xmin;
 761       GLfloat xmax;
 762       GLfloat ymin;
 763       GLfloat ymax;
 764    } guardband;
 765
 766    GLfloat pad1[4];
 767 };
 768
 769 struct brw_urb_immediate {
 770    GLuint opcode:4;
 771    GLuint offset:6;
 772    GLuint swizzle_control:2;
 773    GLuint pad:1;
 774    GLuint allocate:1;
 775    GLuint used:1;
 776    GLuint complete:1;
 777    GLuint response_length:4;
 778    GLuint msg_length:4;
 779    GLuint msg_target:4;
 780    GLuint pad1:3;
 781    GLuint end_of_thread:1;
 782 };
 783
 784 /* Instruction format for the execution units:
 785  */
 786
 787 struct brw_instruction
 788 {
 789    struct
 790    {
 791       GLuint opcode:7;
 792       GLuint pad:1;
 793       GLuint access_mode:1;
 794       GLuint mask_control:1;
 795       GLuint dependency_control:2;
 796       GLuint compression_control:2; /* gen6: quarter control */
 797       GLuint thread_control:2;
 798       GLuint predicate_control:4;
 799       GLuint predicate_inverse:1;
 800       GLuint execution_size:3;
 801       /**
 802        * Conditional Modifier for most instructions.  On Gen6+, this is also
 803        * used for the SEND instruction's Message Target/SFID.
 804        */
 805       GLuint destreg__conditionalmod:4;
 806       GLuint acc_wr_control:1;
 807       GLuint cmpt_control:1;
 808       GLuint debug_control:1;
 809       GLuint saturate:1;
 810    } header;
 811
 812    union {
 813       struct
 814       {
 815          GLuint dest_reg_file:2;
 816          GLuint dest_reg_type:3;
 817          GLuint src0_reg_file:2;
 818          GLuint src0_reg_type:3;
 819          GLuint src1_reg_file:2;
 820          GLuint src1_reg_type:3;
 821          GLuint nibctrl:1; /* gen7+ */
 822          GLuint dest_subreg_nr:5;
 823          GLuint dest_reg_nr:8;
 824          GLuint dest_horiz_stride:2;
 825          GLuint dest_address_mode:1;
 826       } da1;
 827
 828       struct
 829       {
 830          GLuint dest_reg_file:2;
 831          GLuint dest_reg_type:3;
 832          GLuint src0_reg_file:2;
 833          GLuint src0_reg_type:3;
 834          GLuint src1_reg_file:2;        /* 0x00000c00 */
 835          GLuint src1_reg_type:3;        /* 0x00007000 */
 836          GLuint nibctrl:1; /* gen7+ */
 837          GLint dest_indirect_offset:10; /* offset against the deref'd address reg */
 838          GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
 839          GLuint dest_horiz_stride:2;
 840          GLuint dest_address_mode:1;
 841       } ia1;
 842
 843       struct
 844       {
 845          GLuint dest_reg_file:2;
 846          GLuint dest_reg_type:3;
 847          GLuint src0_reg_file:2;
 848          GLuint src0_reg_type:3;
 849          GLuint src1_reg_file:2;
 850          GLuint src1_reg_type:3;
 851          GLuint nibctrl:1; /* gen7+ */
 852          GLuint dest_writemask:4;
 853          GLuint dest_subreg_nr:1;
 854          GLuint dest_reg_nr:8;
 855          GLuint dest_horiz_stride:2;
 856          GLuint dest_address_mode:1;
 857       } da16;
 858
 859       struct
 860       {
 861          GLuint dest_reg_file:2;
 862          GLuint dest_reg_type:3;
 863          GLuint src0_reg_file:2;
 864          GLuint src0_reg_type:3;
 865          GLuint src1_reg_file:2;
 866          GLuint src1_reg_type:3;
 867          GLuint nibctrl:1; /* gen7+ */
 868          GLuint dest_writemask:4;
 869          GLint dest_indirect_offset:6;
 870          GLuint dest_subreg_nr:3;
 871          GLuint dest_horiz_stride:2;
 872          GLuint dest_address_mode:1;
 873       } ia16;
 874
 875       struct {
 876          GLuint dest_reg_file:2;
 877          GLuint dest_reg_type:3;
 878          GLuint src0_reg_file:2;
 879          GLuint src0_reg_type:3;
 880          GLuint src1_reg_file:2;
 881          GLuint src1_reg_type:3;
 882          GLuint pad:1;
 883
 884          GLint jump_count:16;
 885       } branch_gen6;
 886
 887       struct {
 888          GLuint dest_reg_file:1; /* gen6, not gen7+ */
 889          GLuint flag_subreg_num:1;
 890          GLuint flag_reg_nr:1; /* gen7+ */
 891          GLuint pad0:1;
 892          GLuint src0_abs:1;
 893          GLuint src0_negate:1;
 894          GLuint src1_abs:1;
 895          GLuint src1_negate:1;
 896          GLuint src2_abs:1;
 897          GLuint src2_negate:1;
 898          GLuint src_type:2; /* gen7+ */
 899          GLuint dst_type:2; /* gen7+ */
 900          GLuint pad1:1;
 901          GLuint nibctrl:1; /* gen7+ */
 902          GLuint pad2:1;
 903          GLuint dest_writemask:4;
 904          GLuint dest_subreg_nr:3;
 905          GLuint dest_reg_nr:8;
 906       } da3src;
 907
 908       uint32_t ud;
 909    } bits1;
 910
 911
 912    union {
 913       struct
 914       {
 915          GLuint src0_subreg_nr:5;
 916          GLuint src0_reg_nr:8;
 917          GLuint src0_abs:1;
 918          GLuint src0_negate:1;
 919          GLuint src0_address_mode:1;
 920          GLuint src0_horiz_stride:2;
 921          GLuint src0_width:3;
 922          GLuint src0_vert_stride:4;
 923          GLuint flag_subreg_nr:1;
 924          GLuint flag_reg_nr:1; /* gen7+ */
 925          GLuint pad:5;
 926       } da1;
 927
 928       struct
 929       {
 930          GLint src0_indirect_offset:10;
 931          GLuint src0_subreg_nr:3;
 932          GLuint src0_abs:1;
 933          GLuint src0_negate:1;
 934          GLuint src0_address_mode:1;
 935          GLuint src0_horiz_stride:2;
 936          GLuint src0_width:3;
 937          GLuint src0_vert_stride:4;
 938          GLuint flag_subreg_nr:1;
 939          GLuint flag_reg_nr:1; /* gen7+ */
 940          GLuint pad:5;
 941       } ia1;
 942
 943       struct
 944       {
 945          GLuint src0_swz_x:2;
 946          GLuint src0_swz_y:2;
 947          GLuint src0_subreg_nr:1;
 948          GLuint src0_reg_nr:8;
 949          GLuint src0_abs:1;
 950          GLuint src0_negate:1;
 951          GLuint src0_address_mode:1;
 952          GLuint src0_swz_z:2;
 953          GLuint src0_swz_w:2;
 954          GLuint pad0:1;
 955          GLuint src0_vert_stride:4;
 956          GLuint flag_subreg_nr:1;
 957          GLuint flag_reg_nr:1; /* gen7+ */
 958          GLuint pad1:5;
 959       } da16;
 960
 961       struct
 962       {
 963          GLuint src0_swz_x:2;
 964          GLuint src0_swz_y:2;
 965          GLint src0_indirect_offset:6;
 966          GLuint src0_subreg_nr:3;
 967          GLuint src0_abs:1;
 968          GLuint src0_negate:1;
 969          GLuint src0_address_mode:1;
 970          GLuint src0_swz_z:2;
 971          GLuint src0_swz_w:2;
 972          GLuint pad0:1;
 973          GLuint src0_vert_stride:4;
 974          GLuint flag_subreg_nr:1;
 975          GLuint flag_reg_nr:1; /* gen7+ */
 976          GLuint pad1:5;
 977       } ia16;
 978
 979       /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
 980        *
 981        * Does not apply to Gen6+.  The SFID/message target moved to bits
 982        * 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
 983        */
 984        struct
 985        {
 986            GLuint pad:26;
 987            GLuint end_of_thread:1;
 988            GLuint pad1:1;
 989            GLuint sfid:4;
 990        } send_gen5;  /* for Ironlake only */
 991
 992       struct {
 993          GLuint src0_rep_ctrl:1;
 994          GLuint src0_swizzle:8;
 995          GLuint src0_subreg_nr:3;
 996          GLuint src0_reg_nr:8;
 997          GLuint pad0:1;
 998          GLuint src1_rep_ctrl:1;
 999          GLuint src1_swizzle:8;
1000          GLuint src1_subreg_nr_low:2;
1001       } da3src;
1002
1003       uint32_t ud;
1004    } bits2;
1005
1006    union
1007    {
1008       struct
1009       {
1010          GLuint src1_subreg_nr:5;
1011          GLuint src1_reg_nr:8;
1012          GLuint src1_abs:1;
1013          GLuint src1_negate:1;
1014          GLuint src1_address_mode:1;
1015          GLuint src1_horiz_stride:2;
1016          GLuint src1_width:3;
1017          GLuint src1_vert_stride:4;
1018          GLuint pad0:7;
1019       } da1;
1020
1021       struct
1022       {
1023          GLuint src1_swz_x:2;
1024          GLuint src1_swz_y:2;
1025          GLuint src1_subreg_nr:1;
1026          GLuint src1_reg_nr:8;
1027          GLuint src1_abs:1;
1028          GLuint src1_negate:1;
1029          GLuint src1_address_mode:1;
1030          GLuint src1_swz_z:2;
1031          GLuint src1_swz_w:2;
1032          GLuint pad1:1;
1033          GLuint src1_vert_stride:4;
1034          GLuint pad2:7;
1035       } da16;
1036
1037       struct
1038       {
1039          GLint  src1_indirect_offset:10;
1040          GLuint src1_subreg_nr:3;
1041          GLuint src1_abs:1;
1042          GLuint src1_negate:1;
1043          GLuint src1_address_mode:1;
1044          GLuint src1_horiz_stride:2;
1045          GLuint src1_width:3;
1046          GLuint src1_vert_stride:4;
1047          GLuint pad1:7;
1048       } ia1;
1049
1050       struct
1051       {
1052          GLuint src1_swz_x:2;
1053          GLuint src1_swz_y:2;
1054          GLint  src1_indirect_offset:6;
1055          GLuint src1_subreg_nr:3;
1056          GLuint src1_abs:1;
1057          GLuint src1_negate:1;
1058          GLuint pad0:1;
1059          GLuint src1_swz_z:2;
1060          GLuint src1_swz_w:2;
1061          GLuint pad1:1;
1062          GLuint src1_vert_stride:4;
1063          GLuint pad2:7;
1064       } ia16;
1065
1066
1067       struct
1068       {
1069          GLint  jump_count:16;  /* note: signed */
1070          GLuint  pop_count:4;
1071          GLuint  pad0:12;
1072       } if_else;
1073
1074       /* This is also used for gen7 IF/ELSE instructions */
1075       struct
1076       {
1077          /* Signed jump distance to the ip to jump to if all channels
1078           * are disabled after the break or continue.  It should point
1079           * to the end of the innermost control flow block, as that's
1080           * where some channel could get re-enabled.
1081           */
1082          int jip:16;
1083
1084          /* Signed jump distance to the location to resume execution
1085           * of this channel if it's enabled for the break or continue.
1086           */
1087          int uip:16;
1088       } break_cont;
1089
1090       /**
1091        * \defgroup SEND instructions / Message Descriptors
1092        *
1093        * @{
1094        */
1095
1096       /**
1097        * Generic Message Descriptor for Gen4 SEND instructions.  The structs
1098        * below expand function_control to something specific for their
1099        * message.  Due to struct packing issues, they duplicate these bits.
1100        *
1101        * See the G45 PRM, Volume 4, Table 14-15.
1102        */
1103       struct {
1104          GLuint function_control:16;
1105          GLuint response_length:4;
1106          GLuint msg_length:4;
1107          GLuint msg_target:4;
1108          GLuint pad1:3;
1109          GLuint end_of_thread:1;
1110       } generic;
1111
1112       /**
1113        * Generic Message Descriptor for Gen5-7 SEND instructions.
1114        *
1115        * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15.  (Sadly, most
1116        * of the information on the SEND instruction is missing from the public
1117        * Ironlake PRM.)
1118        *
1119        * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies.
1120        * According to the SEND instruction description:
1121        * "The MSb of the message description, the EOT field, always comes from
1122        *  bit 127 of the instruction word"...which is bit 31 of this field.
1123        */
1124       struct {
1125          GLuint function_control:19;
1126          GLuint header_present:1;
1127          GLuint response_length:5;
1128          GLuint msg_length:4;
1129          GLuint pad1:2;
1130          GLuint end_of_thread:1;
1131       } generic_gen5;
1132
1133       /** G45 PRM, Volume 4, Section 6.1.1.1 */
1134       struct {
1135          GLuint function:4;
1136          GLuint int_type:1;
1137          GLuint precision:1;
1138          GLuint saturate:1;
1139          GLuint data_type:1;
1140          GLuint pad0:8;
1141          GLuint response_length:4;
1142          GLuint msg_length:4;
1143          GLuint msg_target:4;
1144          GLuint pad1:3;
1145          GLuint end_of_thread:1;
1146       } math;
1147
1148       /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */
1149       struct {
1150          GLuint function:4;
1151          GLuint int_type:1;
1152          GLuint precision:1;
1153          GLuint saturate:1;
1154          GLuint data_type:1;
1155          GLuint snapshot:1;
1156          GLuint pad0:10;
1157          GLuint header_present:1;
1158          GLuint response_length:5;
1159          GLuint msg_length:4;
1160          GLuint pad1:2;
1161          GLuint end_of_thread:1;
1162       } math_gen5;
1163
1164       /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */
1165       struct {
1166          GLuint binding_table_index:8;
1167          GLuint sampler:4;
1168          GLuint return_format:2;
1169          GLuint msg_type:2;
1170          GLuint response_length:4;
1171          GLuint msg_length:4;
1172          GLuint msg_target:4;
1173          GLuint pad1:3;
1174          GLuint end_of_thread:1;
1175       } sampler;
1176
1177       /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */
1178       struct {
1179          GLuint binding_table_index:8;
1180          GLuint sampler:4;
1181          GLuint msg_type:4;
1182          GLuint response_length:4;
1183          GLuint msg_length:4;
1184          GLuint msg_target:4;
1185          GLuint pad1:3;
1186          GLuint end_of_thread:1;
1187       } sampler_g4x;
1188
1189       /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */
1190       struct {
1191          GLuint binding_table_index:8;
1192          GLuint sampler:4;
1193          GLuint msg_type:4;
1194          GLuint simd_mode:2;
1195          GLuint pad0:1;
1196          GLuint header_present:1;
1197          GLuint response_length:5;
1198          GLuint msg_length:4;
1199          GLuint pad1:2;
1200          GLuint end_of_thread:1;
1201       } sampler_gen5;
1202
1203       struct {
1204          GLuint binding_table_index:8;
1205          GLuint sampler:4;
1206          GLuint msg_type:5;
1207          GLuint simd_mode:2;
1208          GLuint header_present:1;
1209          GLuint response_length:5;
1210          GLuint msg_length:4;
1211          GLuint pad1:2;
1212          GLuint end_of_thread:1;
1213       } sampler_gen7;
1214
1215       struct brw_urb_immediate urb;
1216
1217       struct {
1218          GLuint opcode:4;
1219          GLuint offset:6;
1220          GLuint swizzle_control:2;
1221          GLuint pad:1;
1222          GLuint allocate:1;
1223          GLuint used:1;
1224          GLuint complete:1;
1225          GLuint pad0:3;
1226          GLuint header_present:1;
1227          GLuint response_length:5;
1228          GLuint msg_length:4;
1229          GLuint pad1:2;
1230          GLuint end_of_thread:1;
1231       } urb_gen5;
1232
1233       struct {
1234          GLuint opcode:3;
1235          GLuint offset:11;
1236          GLuint swizzle_control:1;
1237          GLuint complete:1;
1238          GLuint per_slot_offset:1;
1239          GLuint pad0:2;
1240          GLuint header_present:1;
1241          GLuint response_length:5;
1242          GLuint msg_length:4;
1243          GLuint pad1:2;
1244          GLuint end_of_thread:1;
1245       } urb_gen7;
1246
1247       /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
1248       struct {
1249          GLuint binding_table_index:8;
1250          GLuint msg_control:4;
1251          GLuint msg_type:2;
1252          GLuint target_cache:2;
1253          GLuint response_length:4;
1254          GLuint msg_length:4;
1255          GLuint msg_target:4;
1256          GLuint pad1:3;
1257          GLuint end_of_thread:1;
1258       } dp_read;
1259
1260       /** G45 PRM, Volume 4, Section 5.10.1.1.2 */
1261       struct {
1262          GLuint binding_table_index:8;
1263          GLuint msg_control:3;
1264          GLuint msg_type:3;
1265          GLuint target_cache:2;
1266          GLuint response_length:4;
1267          GLuint msg_length:4;
1268          GLuint msg_target:4;
1269          GLuint pad1:3;
1270          GLuint end_of_thread:1;
1271       } dp_read_g4x;
1272
1273       /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1274       struct {
1275          GLuint binding_table_index:8;
1276          GLuint msg_control:3;
1277          GLuint msg_type:3;
1278          GLuint target_cache:2;
1279          GLuint pad0:3;
1280          GLuint header_present:1;
1281          GLuint response_length:5;
1282          GLuint msg_length:4;
1283          GLuint pad1:2;
1284          GLuint end_of_thread:1;
1285       } dp_read_gen5;
1286
1287       /** G45 PRM, Volume 4, Section 5.10.1.1.2.  For both Gen4 and G45. */
1288       struct {
1289          GLuint binding_table_index:8;
1290          GLuint msg_control:3;
1291          GLuint last_render_target:1;
1292          GLuint msg_type:3;
1293          GLuint send_commit_msg:1;
1294          GLuint response_length:4;
1295          GLuint msg_length:4;
1296          GLuint msg_target:4;
1297          GLuint pad1:3;
1298          GLuint end_of_thread:1;
1299       } dp_write;
1300
1301       /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1302       struct {
1303          GLuint binding_table_index:8;
1304          GLuint msg_control:3;
1305          GLuint last_render_target:1;
1306          GLuint msg_type:3;
1307          GLuint send_commit_msg:1;
1308          GLuint pad0:3;
1309          GLuint header_present:1;
1310          GLuint response_length:5;
1311          GLuint msg_length:4;
1312          GLuint pad1:2;
1313          GLuint end_of_thread:1;
1314       } dp_write_gen5;
1315
1316       /**
1317        * Message for the Sandybridge Sampler Cache or Constant Cache Data Port.
1318        *
1319        * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
1320        **/
1321       struct {
1322          GLuint binding_table_index:8;
1323          GLuint msg_control:5;
1324          GLuint msg_type:3;
1325          GLuint pad0:3;
1326          GLuint header_present:1;
1327          GLuint response_length:5;
1328          GLuint msg_length:4;
1329          GLuint pad1:2;
1330          GLuint end_of_thread:1;
1331       } gen6_dp_sampler_const_cache;
1332
1333       /**
1334        * Message for the Sandybridge Render Cache Data Port.
1335        *
1336        * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1,
1337        * Section 3.9.2.1.1: Message Descriptor.
1338        *
1339        * "Slot Group Select" and "Last Render Target" are part of the
1340        * 5-bit message control for Render Target Write messages.  See
1341        * Section 3.9.9.2.1 of the same volume.
1342        */
1343       struct {
1344          GLuint binding_table_index:8;
1345          GLuint msg_control:3;
1346          GLuint slot_group_select:1;
1347          GLuint last_render_target:1;
1348          GLuint msg_type:4;
1349          GLuint send_commit_msg:1;
1350          GLuint pad0:1;
1351          GLuint header_present:1;
1352          GLuint response_length:5;
1353          GLuint msg_length:4;
1354          GLuint pad1:2;
1355          GLuint end_of_thread:1;
1356       } gen6_dp;
1357
1358       /**
1359        * Message for any of the Gen7 Data Port caches.
1360        *
1361        * Most fields are defined in the Ivybridge PRM, Volume 4 Part 1,
1362        * section 3.9.2.1.1 "Message Descriptor".  Once again, "Slot Group
1363        * Select" and "Last Render Target" are part of the 6-bit message
1364        * control for Render Target Writes (section 3.9.11.2).
1365        */
1366       struct {
1367          GLuint binding_table_index:8;
1368          GLuint msg_control:3;
1369          GLuint slot_group_select:1;
1370          GLuint last_render_target:1;
1371          GLuint msg_control_pad:1;
1372          GLuint msg_type:4;
1373          GLuint pad1:1;
1374          GLuint header_present:1;
1375          GLuint response_length:5;
1376          GLuint msg_length:4;
1377          GLuint pad2:2;
1378          GLuint end_of_thread:1;
1379       } gen7_dp;
1380       /** @} */
1381
1382       struct {
1383          GLuint src1_subreg_nr_high:1;
1384          GLuint src1_reg_nr:8;
1385          GLuint pad0:1;
1386          GLuint src2_rep_ctrl:1;
1387          GLuint src2_swizzle:8;
1388          GLuint src2_subreg_nr:3;
1389          GLuint src2_reg_nr:8;
1390          GLuint pad1:2;
1391       } da3src;
1392
1393       GLint d;
1394       GLuint ud;
1395       float f;
1396    } bits3;
1397 };
1398
1399 struct brw_compact_instruction {
1400    struct {
1401       unsigned opcode:7;          /*  0- 6 */
1402       unsigned debug_control:1;   /*  7- 7 */
1403       unsigned control_index:5;   /*  8-12 */
1404       unsigned data_type_index:5; /* 13-17 */
1405       unsigned sub_reg_index:5;   /* 18-22 */
1406       unsigned acc_wr_control:1;  /* 23-23 */
1407       unsigned conditionalmod:4;  /* 24-27 */
1408       unsigned flag_subreg_nr:1;     /* 28-28 */
1409       unsigned cmpt_ctrl:1;       /* 29-29 */
1410       unsigned src0_index:2;      /* 30-31 */
1411    } dw0;
1412
1413    struct {
1414       unsigned src0_index:3;  /* 32-24 */
1415       unsigned src1_index:5;  /* 35-39 */
1416       unsigned dst_reg_nr:8;  /* 40-47 */
1417       unsigned src0_reg_nr:8; /* 48-55 */
1418       unsigned src1_reg_nr:8; /* 56-63 */
1419    } dw1;
1420 };
1421
1422 #endif