2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
68 /* State structs for the various fixed function units:
75 GLuint grf_reg_count
:3;
77 GLuint kernel_start_pointer
:26; /* Offset from GENERAL_STATE_BASE */
82 GLuint ext_halt_exception_enable
:1;
83 GLuint sw_exception_enable
:1;
84 GLuint mask_stack_exception_enable
:1;
85 GLuint timeout_exception_enable
:1;
86 GLuint illegal_op_exception_enable
:1;
88 GLuint depth_coef_urb_read_offset
:6; /* WM only */
90 GLuint floating_point_mode
:1;
91 GLuint thread_priority
:1;
92 GLuint binding_table_entry_count
:8;
94 GLuint single_program_flow
:1;
99 GLuint per_thread_scratch_space
:4;
101 GLuint scratch_space_base_pointer
:22;
107 GLuint dispatch_grf_start_reg
:4;
108 GLuint urb_entry_read_offset
:6;
110 GLuint urb_entry_read_length
:6;
112 GLuint const_urb_entry_read_offset
:6;
114 GLuint const_urb_entry_read_length
:6;
120 struct brw_clip_unit_state
122 struct thread0 thread0
;
126 GLuint sw_exception_enable
:1;
128 GLuint mask_stack_exception_enable
:1;
130 GLuint illegal_op_exception_enable
:1;
132 GLuint floating_point_mode
:1;
133 GLuint thread_priority
:1;
134 GLuint binding_table_entry_count
:8;
136 GLuint single_program_flow
:1;
139 struct thread2 thread2
;
140 struct thread3 thread3
;
145 GLuint gs_output_stats
:1; /* not always */
146 GLuint stats_enable
:1;
147 GLuint nr_urb_entries
:7;
149 GLuint urb_entry_allocation_size
:5;
151 GLuint max_threads
:5; /* may be less */
159 GLuint userclip_enable_flags
:8;
160 GLuint userclip_must_clip
:1;
161 GLuint negative_w_clip_test
:1;
162 GLuint guard_band_enable
:1;
163 GLuint viewport_z_clip_enable
:1;
164 GLuint viewport_xy_clip_enable
:1;
165 GLuint vertex_position_space
:1;
173 GLuint clipper_viewport_state_ptr
:27;
177 GLfloat viewport_xmin
;
178 GLfloat viewport_xmax
;
179 GLfloat viewport_ymin
;
180 GLfloat viewport_ymax
;
183 struct gen6_blend_state
186 GLuint dest_blend_factor
:5;
187 GLuint source_blend_factor
:5;
191 GLuint ia_dest_blend_factor
:5;
192 GLuint ia_source_blend_factor
:5;
194 GLuint ia_blend_func
:3;
196 GLuint ia_blend_enable
:1;
197 GLuint blend_enable
:1;
201 GLuint post_blend_clamp_enable
:1;
202 GLuint pre_blend_clamp_enable
:1;
203 GLuint clamp_range
:2;
205 GLuint x_dither_offset
:2;
206 GLuint y_dither_offset
:2;
207 GLuint dither_enable
:1;
208 GLuint alpha_test_func
:3;
209 GLuint alpha_test_enable
:1;
211 GLuint logic_op_func
:4;
212 GLuint logic_op_enable
:1;
214 GLuint write_disable_b
:1;
215 GLuint write_disable_g
:1;
216 GLuint write_disable_r
:1;
217 GLuint write_disable_a
:1;
219 GLuint alpha_to_coverage_dither
:1;
220 GLuint alpha_to_one
:1;
221 GLuint alpha_to_coverage
:1;
225 struct gen6_color_calc_state
228 GLuint alpha_test_format
:1;
230 GLuint round_disable
:1;
231 GLuint bf_stencil_ref
:8;
232 GLuint stencil_ref
:8;
249 struct gen6_depth_stencil_state
253 GLuint bf_stencil_pass_depth_pass_op
:3;
254 GLuint bf_stencil_pass_depth_fail_op
:3;
255 GLuint bf_stencil_fail_op
:3;
256 GLuint bf_stencil_func
:3;
257 GLuint bf_stencil_enable
:1;
259 GLuint stencil_write_enable
:1;
260 GLuint stencil_pass_depth_pass_op
:3;
261 GLuint stencil_pass_depth_fail_op
:3;
262 GLuint stencil_fail_op
:3;
263 GLuint stencil_func
:3;
264 GLuint stencil_enable
:1;
268 GLuint bf_stencil_write_mask
:8;
269 GLuint bf_stencil_test_mask
:8;
270 GLuint stencil_write_mask
:8;
271 GLuint stencil_test_mask
:8;
276 GLuint depth_write_enable
:1;
277 GLuint depth_test_func
:3;
279 GLuint depth_test_enable
:1;
283 struct brw_cc_unit_state
288 GLuint bf_stencil_pass_depth_pass_op
:3;
289 GLuint bf_stencil_pass_depth_fail_op
:3;
290 GLuint bf_stencil_fail_op
:3;
291 GLuint bf_stencil_func
:3;
292 GLuint bf_stencil_enable
:1;
294 GLuint stencil_write_enable
:1;
295 GLuint stencil_pass_depth_pass_op
:3;
296 GLuint stencil_pass_depth_fail_op
:3;
297 GLuint stencil_fail_op
:3;
298 GLuint stencil_func
:3;
299 GLuint stencil_enable
:1;
305 GLuint bf_stencil_ref
:8;
306 GLuint stencil_write_mask
:8;
307 GLuint stencil_test_mask
:8;
308 GLuint stencil_ref
:8;
314 GLuint logicop_enable
:1;
316 GLuint depth_write_enable
:1;
317 GLuint depth_test_function
:3;
319 GLuint bf_stencil_write_mask
:8;
320 GLuint bf_stencil_test_mask
:8;
327 GLuint alpha_test_func
:3;
329 GLuint blend_enable
:1;
330 GLuint ia_blend_enable
:1;
332 GLuint alpha_test_format
:1;
339 GLuint cc_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
345 GLuint ia_dest_blend_factor
:5;
346 GLuint ia_src_blend_factor
:5;
347 GLuint ia_blend_function
:3;
348 GLuint statistics_enable
:1;
349 GLuint logicop_func
:4;
351 GLuint dither_enable
:1;
356 GLuint clamp_post_alpha_blend
:1;
357 GLuint clamp_pre_alpha_blend
:1;
358 GLuint clamp_range
:2;
360 GLuint y_dither_offset
:2;
361 GLuint x_dither_offset
:2;
362 GLuint dest_blend_factor
:5;
363 GLuint src_blend_factor
:5;
364 GLuint blend_function
:3;
375 struct brw_sf_unit_state
377 struct thread0 thread0
;
378 struct thread1 thread1
;
379 struct thread2 thread2
;
380 struct thread3 thread3
;
385 GLuint stats_enable
:1;
386 GLuint nr_urb_entries
:7;
388 GLuint urb_entry_allocation_size
:5;
390 GLuint max_threads
:6;
396 GLuint front_winding
:1;
397 GLuint viewport_transform
:1;
399 GLuint sf_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
405 GLuint dest_org_vbias
:4;
406 GLuint dest_org_hbias
:4;
408 GLuint disable_2x2_trifilter
:1;
409 GLuint disable_zero_pix_trifilter
:1;
410 GLuint point_rast_rule
:2;
411 GLuint line_endcap_aa_region_width
:2;
413 GLuint fast_scissor_disable
:1;
420 GLuint point_size
:11;
421 GLuint use_point_size_state
:1;
422 GLuint subpixel_precision
:1;
423 GLuint sprite_point
:1;
425 GLuint aa_line_distance_mode
:1;
427 GLuint linestrip_pv
:2;
428 GLuint tristrip_pv
:2;
429 GLuint line_last_pixel_enable
:1;
434 struct gen6_scissor_rect
442 struct brw_gs_unit_state
444 struct thread0 thread0
;
445 struct thread1 thread1
;
446 struct thread2 thread2
;
447 struct thread3 thread3
;
452 GLuint rendering_enable
:1; /* for Ironlake */
454 GLuint stats_enable
:1;
455 GLuint nr_urb_entries
:7;
457 GLuint urb_entry_allocation_size
:5;
459 GLuint max_threads
:5;
465 GLuint sampler_count
:3;
467 GLuint sampler_state_pointer
:27;
473 GLuint max_vp_index
:4;
475 GLuint svbi_post_inc_value
:10;
477 GLuint svbi_post_inc_enable
:1;
478 GLuint svbi_payload
:1;
479 GLuint discard_adjaceny
:1;
480 GLuint reorder_enable
:1;
486 struct brw_vs_unit_state
488 struct thread0 thread0
;
489 struct thread1 thread1
;
490 struct thread2 thread2
;
491 struct thread3 thread3
;
496 GLuint stats_enable
:1;
497 GLuint nr_urb_entries
:7;
499 GLuint urb_entry_allocation_size
:5;
501 GLuint max_threads
:6;
507 GLuint sampler_count
:3;
509 GLuint sampler_state_pointer
:27;
515 GLuint vert_cache_disable
:1;
521 struct brw_wm_unit_state
523 struct thread0 thread0
;
524 struct thread1 thread1
;
525 struct thread2 thread2
;
526 struct thread3 thread3
;
529 GLuint stats_enable
:1;
530 GLuint depth_buffer_clear
:1;
531 GLuint sampler_count
:3;
532 GLuint sampler_state_pointer
:27;
537 GLuint enable_8_pix
:1;
538 GLuint enable_16_pix
:1;
539 GLuint enable_32_pix
:1;
540 GLuint enable_con_32_pix
:1;
541 GLuint enable_con_64_pix
:1;
544 /* These next four bits are for Ironlake+ */
545 GLuint fast_span_coverage_enable
:1;
546 GLuint depth_buffer_clear
:1;
547 GLuint depth_buffer_resolve_enable
:1;
548 GLuint hierarchical_depth_buffer_resolve_enable
:1;
550 GLuint legacy_global_depth_bias
:1;
551 GLuint line_stipple
:1;
552 GLuint depth_offset
:1;
553 GLuint polygon_stipple
:1;
554 GLuint line_aa_region_width
:2;
555 GLuint line_endcap_aa_region_width
:2;
556 GLuint early_depth_test
:1;
557 GLuint thread_dispatch_enable
:1;
558 GLuint program_uses_depth
:1;
559 GLuint program_computes_depth
:1;
560 GLuint program_uses_killpixel
:1;
561 GLuint legacy_line_rast
: 1;
562 GLuint transposed_urb_read_enable
:1;
563 GLuint max_threads
:7;
566 GLfloat global_depth_offset_constant
;
567 GLfloat global_depth_offset_scale
;
569 /* for Ironlake only */
572 GLuint grf_reg_count_1
:3;
574 GLuint kernel_start_pointer_1
:26;
579 GLuint grf_reg_count_2
:3;
581 GLuint kernel_start_pointer_2
:26;
586 GLuint grf_reg_count_3
:3;
588 GLuint kernel_start_pointer_3
:26;
592 struct brw_sampler_default_color
{
596 struct gen5_sampler_default_color
{
605 struct brw_sampler_state
610 GLuint shadow_function
:3;
616 GLuint min_mag_neq
:1;
617 GLuint lod_preclamp
:1;
618 GLuint default_color_mode
:1;
625 GLuint r_wrap_mode
:3;
626 GLuint t_wrap_mode
:3;
627 GLuint s_wrap_mode
:3;
628 GLuint cube_control_mode
:1;
638 GLuint default_color_pointer
:27;
643 GLuint non_normalized_coord
:1;
645 GLuint address_round
:6;
647 GLuint chroma_key_mode
:1;
648 GLuint chroma_key_index
:2;
649 GLuint chroma_key_enable
:1;
650 GLuint monochrome_filter_width
:3;
651 GLuint monochrome_filter_height
:3;
655 struct gen7_sampler_state
659 GLuint aniso_algorithm
:1;
666 GLuint lod_preclamp
:1;
667 GLuint default_color_mode
:1;
674 GLuint cube_control_mode
:1;
675 GLuint shadow_function
:3;
684 GLuint default_color_pointer
:27;
689 GLuint r_wrap_mode
:3;
690 GLuint t_wrap_mode
:3;
691 GLuint s_wrap_mode
:3;
693 GLuint non_normalized_coord
:1;
694 GLuint trilinear_quality
:2;
695 GLuint address_round
:6;
697 GLuint chroma_key_mode
:1;
698 GLuint chroma_key_index
:2;
699 GLuint chroma_key_enable
:1;
704 struct brw_clipper_viewport
712 struct brw_cc_viewport
718 struct brw_sf_viewport
729 /* scissor coordinates are inclusive */
738 struct gen6_sf_viewport
{
747 struct gen7_sf_clip_viewport
{
769 struct brw_urb_immediate
{
772 GLuint swizzle_control
:2;
777 GLuint response_length
:4;
781 GLuint end_of_thread
:1;
784 /* Instruction format for the execution units:
787 struct brw_instruction
793 GLuint access_mode
:1;
794 GLuint mask_control
:1;
795 GLuint dependency_control
:2;
796 GLuint compression_control
:2; /* gen6: quarter control */
797 GLuint thread_control
:2;
798 GLuint predicate_control
:4;
799 GLuint predicate_inverse
:1;
800 GLuint execution_size
:3;
802 * Conditional Modifier for most instructions. On Gen6+, this is also
803 * used for the SEND instruction's Message Target/SFID.
805 GLuint destreg__conditionalmod
:4;
806 GLuint acc_wr_control
:1;
807 GLuint cmpt_control
:1;
808 GLuint debug_control
:1;
815 GLuint dest_reg_file
:2;
816 GLuint dest_reg_type
:3;
817 GLuint src0_reg_file
:2;
818 GLuint src0_reg_type
:3;
819 GLuint src1_reg_file
:2;
820 GLuint src1_reg_type
:3;
821 GLuint nibctrl
:1; /* gen7+ */
822 GLuint dest_subreg_nr
:5;
823 GLuint dest_reg_nr
:8;
824 GLuint dest_horiz_stride
:2;
825 GLuint dest_address_mode
:1;
830 GLuint dest_reg_file
:2;
831 GLuint dest_reg_type
:3;
832 GLuint src0_reg_file
:2;
833 GLuint src0_reg_type
:3;
834 GLuint src1_reg_file
:2; /* 0x00000c00 */
835 GLuint src1_reg_type
:3; /* 0x00007000 */
836 GLuint nibctrl
:1; /* gen7+ */
837 GLint dest_indirect_offset
:10; /* offset against the deref'd address reg */
838 GLuint dest_subreg_nr
:3; /* subnr for the address reg a0.x */
839 GLuint dest_horiz_stride
:2;
840 GLuint dest_address_mode
:1;
845 GLuint dest_reg_file
:2;
846 GLuint dest_reg_type
:3;
847 GLuint src0_reg_file
:2;
848 GLuint src0_reg_type
:3;
849 GLuint src1_reg_file
:2;
850 GLuint src1_reg_type
:3;
851 GLuint nibctrl
:1; /* gen7+ */
852 GLuint dest_writemask
:4;
853 GLuint dest_subreg_nr
:1;
854 GLuint dest_reg_nr
:8;
855 GLuint dest_horiz_stride
:2;
856 GLuint dest_address_mode
:1;
861 GLuint dest_reg_file
:2;
862 GLuint dest_reg_type
:3;
863 GLuint src0_reg_file
:2;
864 GLuint src0_reg_type
:3;
865 GLuint src1_reg_file
:2;
866 GLuint src1_reg_type
:3;
867 GLuint nibctrl
:1; /* gen7+ */
868 GLuint dest_writemask
:4;
869 GLint dest_indirect_offset
:6;
870 GLuint dest_subreg_nr
:3;
871 GLuint dest_horiz_stride
:2;
872 GLuint dest_address_mode
:1;
876 GLuint dest_reg_file
:2;
877 GLuint dest_reg_type
:3;
878 GLuint src0_reg_file
:2;
879 GLuint src0_reg_type
:3;
880 GLuint src1_reg_file
:2;
881 GLuint src1_reg_type
:3;
888 GLuint dest_reg_file
:1; /* gen6, not gen7+ */
889 GLuint flag_subreg_num
:1;
890 GLuint flag_reg_nr
:1; /* gen7+ */
893 GLuint src0_negate
:1;
895 GLuint src1_negate
:1;
897 GLuint src2_negate
:1;
898 GLuint src_type
:2; /* gen7+ */
899 GLuint dst_type
:2; /* gen7+ */
901 GLuint nibctrl
:1; /* gen7+ */
903 GLuint dest_writemask
:4;
904 GLuint dest_subreg_nr
:3;
905 GLuint dest_reg_nr
:8;
915 GLuint src0_subreg_nr
:5;
916 GLuint src0_reg_nr
:8;
918 GLuint src0_negate
:1;
919 GLuint src0_address_mode
:1;
920 GLuint src0_horiz_stride
:2;
922 GLuint src0_vert_stride
:4;
923 GLuint flag_subreg_nr
:1;
924 GLuint flag_reg_nr
:1; /* gen7+ */
930 GLint src0_indirect_offset
:10;
931 GLuint src0_subreg_nr
:3;
933 GLuint src0_negate
:1;
934 GLuint src0_address_mode
:1;
935 GLuint src0_horiz_stride
:2;
937 GLuint src0_vert_stride
:4;
938 GLuint flag_subreg_nr
:1;
939 GLuint flag_reg_nr
:1; /* gen7+ */
947 GLuint src0_subreg_nr
:1;
948 GLuint src0_reg_nr
:8;
950 GLuint src0_negate
:1;
951 GLuint src0_address_mode
:1;
955 GLuint src0_vert_stride
:4;
956 GLuint flag_subreg_nr
:1;
957 GLuint flag_reg_nr
:1; /* gen7+ */
965 GLint src0_indirect_offset
:6;
966 GLuint src0_subreg_nr
:3;
968 GLuint src0_negate
:1;
969 GLuint src0_address_mode
:1;
973 GLuint src0_vert_stride
:4;
974 GLuint flag_subreg_nr
:1;
975 GLuint flag_reg_nr
:1; /* gen7+ */
979 /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
981 * Does not apply to Gen6+. The SFID/message target moved to bits
982 * 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
987 GLuint end_of_thread
:1;
990 } send_gen5
; /* for Ironlake only */
993 GLuint src0_rep_ctrl
:1;
994 GLuint src0_swizzle
:8;
995 GLuint src0_subreg_nr
:3;
996 GLuint src0_reg_nr
:8;
998 GLuint src1_rep_ctrl
:1;
999 GLuint src1_swizzle
:8;
1000 GLuint src1_subreg_nr_low
:2;
1010 GLuint src1_subreg_nr
:5;
1011 GLuint src1_reg_nr
:8;
1013 GLuint src1_negate
:1;
1014 GLuint src1_address_mode
:1;
1015 GLuint src1_horiz_stride
:2;
1016 GLuint src1_width
:3;
1017 GLuint src1_vert_stride
:4;
1023 GLuint src1_swz_x
:2;
1024 GLuint src1_swz_y
:2;
1025 GLuint src1_subreg_nr
:1;
1026 GLuint src1_reg_nr
:8;
1028 GLuint src1_negate
:1;
1029 GLuint src1_address_mode
:1;
1030 GLuint src1_swz_z
:2;
1031 GLuint src1_swz_w
:2;
1033 GLuint src1_vert_stride
:4;
1039 GLint src1_indirect_offset
:10;
1040 GLuint src1_subreg_nr
:3;
1042 GLuint src1_negate
:1;
1043 GLuint src1_address_mode
:1;
1044 GLuint src1_horiz_stride
:2;
1045 GLuint src1_width
:3;
1046 GLuint src1_vert_stride
:4;
1052 GLuint src1_swz_x
:2;
1053 GLuint src1_swz_y
:2;
1054 GLint src1_indirect_offset
:6;
1055 GLuint src1_subreg_nr
:3;
1057 GLuint src1_negate
:1;
1059 GLuint src1_swz_z
:2;
1060 GLuint src1_swz_w
:2;
1062 GLuint src1_vert_stride
:4;
1069 GLint jump_count
:16; /* note: signed */
1074 /* This is also used for gen7 IF/ELSE instructions */
1077 /* Signed jump distance to the ip to jump to if all channels
1078 * are disabled after the break or continue. It should point
1079 * to the end of the innermost control flow block, as that's
1080 * where some channel could get re-enabled.
1084 /* Signed jump distance to the location to resume execution
1085 * of this channel if it's enabled for the break or continue.
1091 * \defgroup SEND instructions / Message Descriptors
1097 * Generic Message Descriptor for Gen4 SEND instructions. The structs
1098 * below expand function_control to something specific for their
1099 * message. Due to struct packing issues, they duplicate these bits.
1101 * See the G45 PRM, Volume 4, Table 14-15.
1104 GLuint function_control
:16;
1105 GLuint response_length
:4;
1106 GLuint msg_length
:4;
1107 GLuint msg_target
:4;
1109 GLuint end_of_thread
:1;
1113 * Generic Message Descriptor for Gen5-7 SEND instructions.
1115 * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15. (Sadly, most
1116 * of the information on the SEND instruction is missing from the public
1119 * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies.
1120 * According to the SEND instruction description:
1121 * "The MSb of the message description, the EOT field, always comes from
1122 * bit 127 of the instruction word"...which is bit 31 of this field.
1125 GLuint function_control
:19;
1126 GLuint header_present
:1;
1127 GLuint response_length
:5;
1128 GLuint msg_length
:4;
1130 GLuint end_of_thread
:1;
1133 /** G45 PRM, Volume 4, Section 6.1.1.1 */
1141 GLuint response_length
:4;
1142 GLuint msg_length
:4;
1143 GLuint msg_target
:4;
1145 GLuint end_of_thread
:1;
1148 /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */
1157 GLuint header_present
:1;
1158 GLuint response_length
:5;
1159 GLuint msg_length
:4;
1161 GLuint end_of_thread
:1;
1164 /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */
1166 GLuint binding_table_index
:8;
1168 GLuint return_format
:2;
1170 GLuint response_length
:4;
1171 GLuint msg_length
:4;
1172 GLuint msg_target
:4;
1174 GLuint end_of_thread
:1;
1177 /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */
1179 GLuint binding_table_index
:8;
1182 GLuint response_length
:4;
1183 GLuint msg_length
:4;
1184 GLuint msg_target
:4;
1186 GLuint end_of_thread
:1;
1189 /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */
1191 GLuint binding_table_index
:8;
1196 GLuint header_present
:1;
1197 GLuint response_length
:5;
1198 GLuint msg_length
:4;
1200 GLuint end_of_thread
:1;
1204 GLuint binding_table_index
:8;
1208 GLuint header_present
:1;
1209 GLuint response_length
:5;
1210 GLuint msg_length
:4;
1212 GLuint end_of_thread
:1;
1215 struct brw_urb_immediate urb
;
1220 GLuint swizzle_control
:2;
1226 GLuint header_present
:1;
1227 GLuint response_length
:5;
1228 GLuint msg_length
:4;
1230 GLuint end_of_thread
:1;
1236 GLuint swizzle_control
:1;
1238 GLuint per_slot_offset
:1;
1240 GLuint header_present
:1;
1241 GLuint response_length
:5;
1242 GLuint msg_length
:4;
1244 GLuint end_of_thread
:1;
1247 /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
1249 GLuint binding_table_index
:8;
1250 GLuint msg_control
:4;
1252 GLuint target_cache
:2;
1253 GLuint response_length
:4;
1254 GLuint msg_length
:4;
1255 GLuint msg_target
:4;
1257 GLuint end_of_thread
:1;
1260 /** G45 PRM, Volume 4, Section 5.10.1.1.2 */
1262 GLuint binding_table_index
:8;
1263 GLuint msg_control
:3;
1265 GLuint target_cache
:2;
1266 GLuint response_length
:4;
1267 GLuint msg_length
:4;
1268 GLuint msg_target
:4;
1270 GLuint end_of_thread
:1;
1273 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1275 GLuint binding_table_index
:8;
1276 GLuint msg_control
:3;
1278 GLuint target_cache
:2;
1280 GLuint header_present
:1;
1281 GLuint response_length
:5;
1282 GLuint msg_length
:4;
1284 GLuint end_of_thread
:1;
1287 /** G45 PRM, Volume 4, Section 5.10.1.1.2. For both Gen4 and G45. */
1289 GLuint binding_table_index
:8;
1290 GLuint msg_control
:3;
1291 GLuint last_render_target
:1;
1293 GLuint send_commit_msg
:1;
1294 GLuint response_length
:4;
1295 GLuint msg_length
:4;
1296 GLuint msg_target
:4;
1298 GLuint end_of_thread
:1;
1301 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1303 GLuint binding_table_index
:8;
1304 GLuint msg_control
:3;
1305 GLuint last_render_target
:1;
1307 GLuint send_commit_msg
:1;
1309 GLuint header_present
:1;
1310 GLuint response_length
:5;
1311 GLuint msg_length
:4;
1313 GLuint end_of_thread
:1;
1317 * Message for the Sandybridge Sampler Cache or Constant Cache Data Port.
1319 * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
1322 GLuint binding_table_index
:8;
1323 GLuint msg_control
:5;
1326 GLuint header_present
:1;
1327 GLuint response_length
:5;
1328 GLuint msg_length
:4;
1330 GLuint end_of_thread
:1;
1331 } gen6_dp_sampler_const_cache
;
1334 * Message for the Sandybridge Render Cache Data Port.
1336 * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1,
1337 * Section 3.9.2.1.1: Message Descriptor.
1339 * "Slot Group Select" and "Last Render Target" are part of the
1340 * 5-bit message control for Render Target Write messages. See
1341 * Section 3.9.9.2.1 of the same volume.
1344 GLuint binding_table_index
:8;
1345 GLuint msg_control
:3;
1346 GLuint slot_group_select
:1;
1347 GLuint last_render_target
:1;
1349 GLuint send_commit_msg
:1;
1351 GLuint header_present
:1;
1352 GLuint response_length
:5;
1353 GLuint msg_length
:4;
1355 GLuint end_of_thread
:1;
1359 * Message for any of the Gen7 Data Port caches.
1361 * Most fields are defined in the Ivybridge PRM, Volume 4 Part 1,
1362 * section 3.9.2.1.1 "Message Descriptor". Once again, "Slot Group
1363 * Select" and "Last Render Target" are part of the 6-bit message
1364 * control for Render Target Writes (section 3.9.11.2).
1367 GLuint binding_table_index
:8;
1368 GLuint msg_control
:3;
1369 GLuint slot_group_select
:1;
1370 GLuint last_render_target
:1;
1371 GLuint msg_control_pad
:1;
1374 GLuint header_present
:1;
1375 GLuint response_length
:5;
1376 GLuint msg_length
:4;
1378 GLuint end_of_thread
:1;
1383 GLuint src1_subreg_nr_high
:1;
1384 GLuint src1_reg_nr
:8;
1386 GLuint src2_rep_ctrl
:1;
1387 GLuint src2_swizzle
:8;
1388 GLuint src2_subreg_nr
:3;
1389 GLuint src2_reg_nr
:8;
1399 struct brw_compact_instruction
{
1401 unsigned opcode
:7; /* 0- 6 */
1402 unsigned debug_control
:1; /* 7- 7 */
1403 unsigned control_index
:5; /* 8-12 */
1404 unsigned data_type_index
:5; /* 13-17 */
1405 unsigned sub_reg_index
:5; /* 18-22 */
1406 unsigned acc_wr_control
:1; /* 23-23 */
1407 unsigned conditionalmod
:4; /* 24-27 */
1408 unsigned flag_subreg_nr
:1; /* 28-28 */
1409 unsigned cmpt_ctrl
:1; /* 29-29 */
1410 unsigned src0_index
:2; /* 30-31 */
1414 unsigned src0_index
:3; /* 32-24 */
1415 unsigned src1_index
:5; /* 35-39 */
1416 unsigned dst_reg_nr
:8; /* 40-47 */
1417 unsigned src0_reg_nr
:8; /* 48-55 */
1418 unsigned src1_reg_nr
:8; /* 56-63 */