src/mesa/drivers/dri/i965/brw_structs.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #ifndef BRW_STRUCTS_H
  34 #define BRW_STRUCTS_H
  35
  36 struct brw_urb_fence
  37 {
  38    struct
  39    {
  40       unsigned length:8;
  41       unsigned vs_realloc:1;
  42       unsigned gs_realloc:1;
  43       unsigned clp_realloc:1;
  44       unsigned sf_realloc:1;
  45       unsigned vfe_realloc:1;
  46       unsigned cs_realloc:1;
  47       unsigned pad:2;
  48       unsigned opcode:16;
  49    } header;
  50
  51    struct
  52    {
  53       unsigned vs_fence:10;
  54       unsigned gs_fence:10;
  55       unsigned clp_fence:10;
  56       unsigned pad:2;
  57    } bits0;
  58
  59    struct
  60    {
  61       unsigned sf_fence:10;
  62       unsigned vf_fence:10;
  63       unsigned cs_fence:11;
  64       unsigned pad:1;
  65    } bits1;
  66 };
  67
  68 /* State structs for the various fixed function units:
  69  */
  70
  71
  72 struct thread0
  73 {
  74    unsigned pad0:1;
  75    unsigned grf_reg_count:3;
  76    unsigned pad1:2;
  77    unsigned kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
  78 };
  79
  80 struct thread1
  81 {
  82    unsigned ext_halt_exception_enable:1;
  83    unsigned sw_exception_enable:1;
  84    unsigned mask_stack_exception_enable:1;
  85    unsigned timeout_exception_enable:1;
  86    unsigned illegal_op_exception_enable:1;
  87    unsigned pad0:3;
  88    unsigned depth_coef_urb_read_offset:6;       /* WM only */
  89    unsigned pad1:2;
  90    unsigned floating_point_mode:1;
  91    unsigned thread_priority:1;
  92    unsigned binding_table_entry_count:8;
  93    unsigned pad3:5;
  94    unsigned single_program_flow:1;
  95 };
  96
  97 struct thread2
  98 {
  99    unsigned per_thread_scratch_space:4;
 100    unsigned pad0:6;
 101    unsigned scratch_space_base_pointer:22;
 102 };
 103
 104
 105 struct thread3
 106 {
 107    unsigned dispatch_grf_start_reg:4;
 108    unsigned urb_entry_read_offset:6;
 109    unsigned pad0:1;
 110    unsigned urb_entry_read_length:6;
 111    unsigned pad1:1;
 112    unsigned const_urb_entry_read_offset:6;
 113    unsigned pad2:1;
 114    unsigned const_urb_entry_read_length:6;
 115    unsigned pad3:1;
 116 };
 117
 118
 119
 120 struct brw_clip_unit_state
 121 {
 122    struct thread0 thread0;
 123    struct
 124    {
 125       unsigned pad0:7;
 126       unsigned sw_exception_enable:1;
 127       unsigned pad1:3;
 128       unsigned mask_stack_exception_enable:1;
 129       unsigned pad2:1;
 130       unsigned illegal_op_exception_enable:1;
 131       unsigned pad3:2;
 132       unsigned floating_point_mode:1;
 133       unsigned thread_priority:1;
 134       unsigned binding_table_entry_count:8;
 135       unsigned pad4:5;
 136       unsigned single_program_flow:1;
 137    } thread1;
 138
 139    struct thread2 thread2;
 140    struct thread3 thread3;
 141
 142    struct
 143    {
 144       unsigned pad0:9;
 145       unsigned gs_output_stats:1; /* not always */
 146       unsigned stats_enable:1;
 147       unsigned nr_urb_entries:7;
 148       unsigned pad1:1;
 149       unsigned urb_entry_allocation_size:5;
 150       unsigned pad2:1;
 151       unsigned max_threads:5;   /* may be less */
 152       unsigned pad3:2;
 153    } thread4;
 154
 155    struct
 156    {
 157       unsigned pad0:13;
 158       unsigned clip_mode:3;
 159       unsigned userclip_enable_flags:8;
 160       unsigned userclip_must_clip:1;
 161       unsigned negative_w_clip_test:1;
 162       unsigned guard_band_enable:1;
 163       unsigned viewport_z_clip_enable:1;
 164       unsigned viewport_xy_clip_enable:1;
 165       unsigned vertex_position_space:1;
 166       unsigned api_mode:1;
 167       unsigned pad2:1;
 168    } clip5;
 169
 170    struct
 171    {
 172       unsigned pad0:5;
 173       unsigned clipper_viewport_state_ptr:27;
 174    } clip6;
 175
 176
 177    float viewport_xmin;
 178    float viewport_xmax;
 179    float viewport_ymin;
 180    float viewport_ymax;
 181 };
 182
 183 struct gen6_blend_state
 184 {
 185    struct {
 186       unsigned dest_blend_factor:5;
 187       unsigned source_blend_factor:5;
 188       unsigned pad3:1;
 189       unsigned blend_func:3;
 190       unsigned pad2:1;
 191       unsigned ia_dest_blend_factor:5;
 192       unsigned ia_source_blend_factor:5;
 193       unsigned pad1:1;
 194       unsigned ia_blend_func:3;
 195       unsigned pad0:1;
 196       unsigned ia_blend_enable:1;
 197       unsigned blend_enable:1;
 198    } blend0;
 199
 200    struct {
 201       unsigned post_blend_clamp_enable:1;
 202       unsigned pre_blend_clamp_enable:1;
 203       unsigned clamp_range:2;
 204       unsigned pad0:4;
 205       unsigned x_dither_offset:2;
 206       unsigned y_dither_offset:2;
 207       unsigned dither_enable:1;
 208       unsigned alpha_test_func:3;
 209       unsigned alpha_test_enable:1;
 210       unsigned pad1:1;
 211       unsigned logic_op_func:4;
 212       unsigned logic_op_enable:1;
 213       unsigned pad2:1;
 214       unsigned write_disable_b:1;
 215       unsigned write_disable_g:1;
 216       unsigned write_disable_r:1;
 217       unsigned write_disable_a:1;
 218       unsigned pad3:1;
 219       unsigned alpha_to_coverage_dither:1;
 220       unsigned alpha_to_one:1;
 221       unsigned alpha_to_coverage:1;
 222    } blend1;
 223 };
 224
 225 struct gen6_color_calc_state
 226 {
 227    struct {
 228       unsigned alpha_test_format:1;
 229       unsigned pad0:14;
 230       unsigned round_disable:1;
 231       unsigned bf_stencil_ref:8;
 232       unsigned stencil_ref:8;
 233    } cc0;
 234
 235    union {
 236       float alpha_ref_f;
 237       struct {
 238          unsigned ui:8;
 239          unsigned pad0:24;
 240       } alpha_ref_fi;
 241    } cc1;
 242
 243    float constant_r;
 244    float constant_g;
 245    float constant_b;
 246    float constant_a;
 247 };
 248
 249 struct gen6_depth_stencil_state
 250 {
 251    struct {
 252       unsigned pad0:3;
 253       unsigned bf_stencil_pass_depth_pass_op:3;
 254       unsigned bf_stencil_pass_depth_fail_op:3;
 255       unsigned bf_stencil_fail_op:3;
 256       unsigned bf_stencil_func:3;
 257       unsigned bf_stencil_enable:1;
 258       unsigned pad1:2;
 259       unsigned stencil_write_enable:1;
 260       unsigned stencil_pass_depth_pass_op:3;
 261       unsigned stencil_pass_depth_fail_op:3;
 262       unsigned stencil_fail_op:3;
 263       unsigned stencil_func:3;
 264       unsigned stencil_enable:1;
 265    } ds0;
 266
 267    struct {
 268       unsigned bf_stencil_write_mask:8;
 269       unsigned bf_stencil_test_mask:8;
 270       unsigned stencil_write_mask:8;
 271       unsigned stencil_test_mask:8;
 272    } ds1;
 273
 274    struct {
 275       unsigned pad0:26;
 276       unsigned depth_write_enable:1;
 277       unsigned depth_test_func:3;
 278       unsigned pad1:1;
 279       unsigned depth_test_enable:1;
 280    } ds2;
 281 };
 282
 283 struct brw_cc_unit_state
 284 {
 285    struct
 286    {
 287       unsigned pad0:3;
 288       unsigned bf_stencil_pass_depth_pass_op:3;
 289       unsigned bf_stencil_pass_depth_fail_op:3;
 290       unsigned bf_stencil_fail_op:3;
 291       unsigned bf_stencil_func:3;
 292       unsigned bf_stencil_enable:1;
 293       unsigned pad1:2;
 294       unsigned stencil_write_enable:1;
 295       unsigned stencil_pass_depth_pass_op:3;
 296       unsigned stencil_pass_depth_fail_op:3;
 297       unsigned stencil_fail_op:3;
 298       unsigned stencil_func:3;
 299       unsigned stencil_enable:1;
 300    } cc0;
 301
 302
 303    struct
 304    {
 305       unsigned bf_stencil_ref:8;
 306       unsigned stencil_write_mask:8;
 307       unsigned stencil_test_mask:8;
 308       unsigned stencil_ref:8;
 309    } cc1;
 310
 311
 312    struct
 313    {
 314       unsigned logicop_enable:1;
 315       unsigned pad0:10;
 316       unsigned depth_write_enable:1;
 317       unsigned depth_test_function:3;
 318       unsigned depth_test:1;
 319       unsigned bf_stencil_write_mask:8;
 320       unsigned bf_stencil_test_mask:8;
 321    } cc2;
 322
 323
 324    struct
 325    {
 326       unsigned pad0:8;
 327       unsigned alpha_test_func:3;
 328       unsigned alpha_test:1;
 329       unsigned blend_enable:1;
 330       unsigned ia_blend_enable:1;
 331       unsigned pad1:1;
 332       unsigned alpha_test_format:1;
 333       unsigned pad2:16;
 334    } cc3;
 335
 336    struct
 337    {
 338       unsigned pad0:5;
 339       unsigned cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 340    } cc4;
 341
 342    struct
 343    {
 344       unsigned pad0:2;
 345       unsigned ia_dest_blend_factor:5;
 346       unsigned ia_src_blend_factor:5;
 347       unsigned ia_blend_function:3;
 348       unsigned statistics_enable:1;
 349       unsigned logicop_func:4;
 350       unsigned pad1:11;
 351       unsigned dither_enable:1;
 352    } cc5;
 353
 354    struct
 355    {
 356       unsigned clamp_post_alpha_blend:1;
 357       unsigned clamp_pre_alpha_blend:1;
 358       unsigned clamp_range:2;
 359       unsigned pad0:11;
 360       unsigned y_dither_offset:2;
 361       unsigned x_dither_offset:2;
 362       unsigned dest_blend_factor:5;
 363       unsigned src_blend_factor:5;
 364       unsigned blend_function:3;
 365    } cc6;
 366
 367    struct {
 368       union {
 369          float f;
 370          uint8_t ub[4];
 371       } alpha_ref;
 372    } cc7;
 373 };
 374
 375 struct brw_sf_unit_state
 376 {
 377    struct thread0 thread0;
 378    struct thread1 thread1;
 379    struct thread2 thread2;
 380    struct thread3 thread3;
 381
 382    struct
 383    {
 384       unsigned pad0:10;
 385       unsigned stats_enable:1;
 386       unsigned nr_urb_entries:7;
 387       unsigned pad1:1;
 388       unsigned urb_entry_allocation_size:5;
 389       unsigned pad2:1;
 390       unsigned max_threads:6;
 391       unsigned pad3:1;
 392    } thread4;
 393
 394    struct
 395    {
 396       unsigned front_winding:1;
 397       unsigned viewport_transform:1;
 398       unsigned pad0:3;
 399       unsigned sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 400    } sf5;
 401
 402    struct
 403    {
 404       unsigned pad0:9;
 405       unsigned dest_org_vbias:4;
 406       unsigned dest_org_hbias:4;
 407       unsigned scissor:1;
 408       unsigned disable_2x2_trifilter:1;
 409       unsigned disable_zero_pix_trifilter:1;
 410       unsigned point_rast_rule:2;
 411       unsigned line_endcap_aa_region_width:2;
 412       unsigned line_width:4;
 413       unsigned fast_scissor_disable:1;
 414       unsigned cull_mode:2;
 415       unsigned aa_enable:1;
 416    } sf6;
 417
 418    struct
 419    {
 420       unsigned point_size:11;
 421       unsigned use_point_size_state:1;
 422       unsigned subpixel_precision:1;
 423       unsigned sprite_point:1;
 424       unsigned pad0:10;
 425       unsigned aa_line_distance_mode:1;
 426       unsigned trifan_pv:2;
 427       unsigned linestrip_pv:2;
 428       unsigned tristrip_pv:2;
 429       unsigned line_last_pixel_enable:1;
 430    } sf7;
 431
 432 };
 433
 434 struct gen6_scissor_rect
 435 {
 436    unsigned xmin:16;
 437    unsigned ymin:16;
 438    unsigned xmax:16;
 439    unsigned ymax:16;
 440 };
 441
 442 struct brw_gs_unit_state
 443 {
 444    struct thread0 thread0;
 445    struct thread1 thread1;
 446    struct thread2 thread2;
 447    struct thread3 thread3;
 448
 449    struct
 450    {
 451       unsigned pad0:8;
 452       unsigned rendering_enable:1; /* for Ironlake */
 453       unsigned pad4:1;
 454       unsigned stats_enable:1;
 455       unsigned nr_urb_entries:7;
 456       unsigned pad1:1;
 457       unsigned urb_entry_allocation_size:5;
 458       unsigned pad2:1;
 459       unsigned max_threads:5;
 460       unsigned pad3:2;
 461    } thread4;
 462
 463    struct
 464    {
 465       unsigned sampler_count:3;
 466       unsigned pad0:2;
 467       unsigned sampler_state_pointer:27;
 468    } gs5;
 469
 470
 471    struct
 472    {
 473       unsigned max_vp_index:4;
 474       unsigned pad0:12;
 475       unsigned svbi_post_inc_value:10;
 476       unsigned pad1:1;
 477       unsigned svbi_post_inc_enable:1;
 478       unsigned svbi_payload:1;
 479       unsigned discard_adjaceny:1;
 480       unsigned reorder_enable:1;
 481       unsigned pad2:1;
 482    } gs6;
 483 };
 484
 485
 486 struct brw_vs_unit_state
 487 {
 488    struct thread0 thread0;
 489    struct thread1 thread1;
 490    struct thread2 thread2;
 491    struct thread3 thread3;
 492
 493    struct
 494    {
 495       unsigned pad0:10;
 496       unsigned stats_enable:1;
 497       unsigned nr_urb_entries:7;
 498       unsigned pad1:1;
 499       unsigned urb_entry_allocation_size:5;
 500       unsigned pad2:1;
 501       unsigned max_threads:6;
 502       unsigned pad3:1;
 503    } thread4;
 504
 505    struct
 506    {
 507       unsigned sampler_count:3;
 508       unsigned pad0:2;
 509       unsigned sampler_state_pointer:27;
 510    } vs5;
 511
 512    struct
 513    {
 514       unsigned vs_enable:1;
 515       unsigned vert_cache_disable:1;
 516       unsigned pad0:30;
 517    } vs6;
 518 };
 519
 520
 521 struct brw_wm_unit_state
 522 {
 523    struct thread0 thread0;
 524    struct thread1 thread1;
 525    struct thread2 thread2;
 526    struct thread3 thread3;
 527
 528    struct {
 529       unsigned stats_enable:1;
 530       unsigned depth_buffer_clear:1;
 531       unsigned sampler_count:3;
 532       unsigned sampler_state_pointer:27;
 533    } wm4;
 534
 535    struct
 536    {
 537       unsigned enable_8_pix:1;
 538       unsigned enable_16_pix:1;
 539       unsigned enable_32_pix:1;
 540       unsigned enable_con_32_pix:1;
 541       unsigned enable_con_64_pix:1;
 542       unsigned pad0:1;
 543
 544       /* These next four bits are for Ironlake+ */
 545       unsigned fast_span_coverage_enable:1;
 546       unsigned depth_buffer_clear:1;
 547       unsigned depth_buffer_resolve_enable:1;
 548       unsigned hierarchical_depth_buffer_resolve_enable:1;
 549
 550       unsigned legacy_global_depth_bias:1;
 551       unsigned line_stipple:1;
 552       unsigned depth_offset:1;
 553       unsigned polygon_stipple:1;
 554       unsigned line_aa_region_width:2;
 555       unsigned line_endcap_aa_region_width:2;
 556       unsigned early_depth_test:1;
 557       unsigned thread_dispatch_enable:1;
 558       unsigned program_uses_depth:1;
 559       unsigned program_computes_depth:1;
 560       unsigned program_uses_killpixel:1;
 561       unsigned legacy_line_rast: 1;
 562       unsigned transposed_urb_read_enable:1;
 563       unsigned max_threads:7;
 564    } wm5;
 565
 566    float global_depth_offset_constant;
 567    float global_depth_offset_scale;
 568
 569    /* for Ironlake only */
 570    struct {
 571       unsigned pad0:1;
 572       unsigned grf_reg_count_1:3;
 573       unsigned pad1:2;
 574       unsigned kernel_start_pointer_1:26;
 575    } wm8;
 576
 577    struct {
 578       unsigned pad0:1;
 579       unsigned grf_reg_count_2:3;
 580       unsigned pad1:2;
 581       unsigned kernel_start_pointer_2:26;
 582    } wm9;
 583
 584    struct {
 585       unsigned pad0:1;
 586       unsigned grf_reg_count_3:3;
 587       unsigned pad1:2;
 588       unsigned kernel_start_pointer_3:26;
 589    } wm10;
 590 };
 591
 592 struct brw_sampler_default_color {
 593    float color[4];
 594 };
 595
 596 struct gen5_sampler_default_color {
 597    uint8_t ub[4];
 598    float f[4];
 599    uint16_t hf[4];
 600    uint16_t us[4];
 601    int16_t s[4];
 602    uint8_t b[4];
 603 };
 604
 605 struct brw_sampler_state
 606 {
 607
 608    struct
 609    {
 610       unsigned shadow_function:3;
 611       unsigned lod_bias:11;
 612       unsigned min_filter:3;
 613       unsigned mag_filter:3;
 614       unsigned mip_filter:2;
 615       unsigned base_level:5;
 616       unsigned min_mag_neq:1;
 617       unsigned lod_preclamp:1;
 618       unsigned default_color_mode:1;
 619       unsigned pad0:1;
 620       unsigned disable:1;
 621    } ss0;
 622
 623    struct
 624    {
 625       unsigned r_wrap_mode:3;
 626       unsigned t_wrap_mode:3;
 627       unsigned s_wrap_mode:3;
 628       unsigned cube_control_mode:1;
 629       unsigned pad:2;
 630       unsigned max_lod:10;
 631       unsigned min_lod:10;
 632    } ss1;
 633
 634
 635    struct
 636    {
 637       unsigned pad:5;
 638       unsigned default_color_pointer:27;
 639    } ss2;
 640
 641    struct
 642    {
 643       unsigned non_normalized_coord:1;
 644       unsigned pad:12;
 645       unsigned address_round:6;
 646       unsigned max_aniso:3;
 647       unsigned chroma_key_mode:1;
 648       unsigned chroma_key_index:2;
 649       unsigned chroma_key_enable:1;
 650       unsigned monochrome_filter_width:3;
 651       unsigned monochrome_filter_height:3;
 652    } ss3;
 653 };
 654
 655 struct gen7_sampler_state
 656 {
 657    struct
 658    {
 659       unsigned aniso_algorithm:1;
 660       unsigned lod_bias:13;
 661       unsigned min_filter:3;
 662       unsigned mag_filter:3;
 663       unsigned mip_filter:2;
 664       unsigned base_level:5;
 665       unsigned pad1:1;
 666       unsigned lod_preclamp:1;
 667       unsigned default_color_mode:1;
 668       unsigned pad0:1;
 669       unsigned disable:1;
 670    } ss0;
 671
 672    struct
 673    {
 674       unsigned cube_control_mode:1;
 675       unsigned shadow_function:3;
 676       unsigned pad:4;
 677       unsigned max_lod:12;
 678       unsigned min_lod:12;
 679    } ss1;
 680
 681    struct
 682    {
 683       unsigned pad:5;
 684       unsigned default_color_pointer:27;
 685    } ss2;
 686
 687    struct
 688    {
 689       unsigned r_wrap_mode:3;
 690       unsigned t_wrap_mode:3;
 691       unsigned s_wrap_mode:3;
 692       unsigned pad:1;
 693       unsigned non_normalized_coord:1;
 694       unsigned trilinear_quality:2;
 695       unsigned address_round:6;
 696       unsigned max_aniso:3;
 697       unsigned chroma_key_mode:1;
 698       unsigned chroma_key_index:2;
 699       unsigned chroma_key_enable:1;
 700       unsigned pad0:6;
 701    } ss3;
 702 };
 703
 704 struct brw_clipper_viewport
 705 {
 706    float xmin;
 707    float xmax;
 708    float ymin;
 709    float ymax;
 710 };
 711
 712 struct brw_cc_viewport
 713 {
 714    float min_depth;
 715    float max_depth;
 716 };
 717
 718 struct brw_sf_viewport
 719 {
 720    struct {
 721       float m00;
 722       float m11;
 723       float m22;
 724       float m30;
 725       float m31;
 726       float m32;
 727    } viewport;
 728
 729    /* scissor coordinates are inclusive */
 730    struct {
 731       int16_t xmin;
 732       int16_t ymin;
 733       int16_t xmax;
 734       int16_t ymax;
 735    } scissor;
 736 };
 737
 738 struct gen6_sf_viewport {
 739    float m00;
 740    float m11;
 741    float m22;
 742    float m30;
 743    float m31;
 744    float m32;
 745 };
 746
 747 struct gen7_sf_clip_viewport {
 748    struct {
 749       float m00;
 750       float m11;
 751       float m22;
 752       float m30;
 753       float m31;
 754       float m32;
 755    } viewport;
 756
 757    unsigned pad0[2];
 758
 759    struct {
 760       float xmin;
 761       float xmax;
 762       float ymin;
 763       float ymax;
 764    } guardband;
 765
 766    float pad1[4];
 767 };
 768
 769 struct brw_urb_immediate {
 770    unsigned opcode:4;
 771    unsigned offset:6;
 772    unsigned swizzle_control:2;
 773    unsigned pad:1;
 774    unsigned allocate:1;
 775    unsigned used:1;
 776    unsigned complete:1;
 777    unsigned response_length:4;
 778    unsigned msg_length:4;
 779    unsigned msg_target:4;
 780    unsigned pad1:3;
 781    unsigned end_of_thread:1;
 782 };
 783
 784 /* Instruction format for the execution units:
 785  */
 786
 787 struct brw_instruction
 788 {
 789    struct
 790    {
 791       unsigned opcode:7;
 792       unsigned pad:1;
 793       unsigned access_mode:1;
 794       unsigned mask_control:1;
 795       unsigned dependency_control:2;
 796       unsigned compression_control:2; /* gen6: quarter control */
 797       unsigned thread_control:2;
 798       unsigned predicate_control:4;
 799       unsigned predicate_inverse:1;
 800       unsigned execution_size:3;
 801       /**
 802        * Conditional Modifier for most instructions.  On Gen6+, this is also
 803        * used for the SEND instruction's Message Target/SFID.
 804        */
 805       unsigned destreg__conditionalmod:4;
 806       unsigned acc_wr_control:1;
 807       unsigned cmpt_control:1;
 808       unsigned debug_control:1;
 809       unsigned saturate:1;
 810    } header;
 811
 812    union {
 813       struct
 814       {
 815          unsigned dest_reg_file:2;
 816          unsigned dest_reg_type:3;
 817          unsigned src0_reg_file:2;
 818          unsigned src0_reg_type:3;
 819          unsigned src1_reg_file:2;
 820          unsigned src1_reg_type:3;
 821          unsigned nibctrl:1; /* gen7+ */
 822          unsigned dest_subreg_nr:5;
 823          unsigned dest_reg_nr:8;
 824          unsigned dest_horiz_stride:2;
 825          unsigned dest_address_mode:1;
 826       } da1;
 827
 828       struct
 829       {
 830          unsigned dest_reg_file:2;
 831          unsigned dest_reg_type:3;
 832          unsigned src0_reg_file:2;
 833          unsigned src0_reg_type:3;
 834          unsigned src1_reg_file:2;        /* 0x00000c00 */
 835          unsigned src1_reg_type:3;        /* 0x00007000 */
 836          unsigned nibctrl:1; /* gen7+ */
 837          int dest_indirect_offset:10;   /* offset against the deref'd address reg */
 838          unsigned dest_subreg_nr:3; /* subnr for the address reg a0.x */
 839          unsigned dest_horiz_stride:2;
 840          unsigned dest_address_mode:1;
 841       } ia1;
 842
 843       struct
 844       {
 845          unsigned dest_reg_file:2;
 846          unsigned dest_reg_type:3;
 847          unsigned src0_reg_file:2;
 848          unsigned src0_reg_type:3;
 849          unsigned src1_reg_file:2;
 850          unsigned src1_reg_type:3;
 851          unsigned nibctrl:1; /* gen7+ */
 852          unsigned dest_writemask:4;
 853          unsigned dest_subreg_nr:1;
 854          unsigned dest_reg_nr:8;
 855          unsigned dest_horiz_stride:2;
 856          unsigned dest_address_mode:1;
 857       } da16;
 858
 859       struct
 860       {
 861          unsigned dest_reg_file:2;
 862          unsigned dest_reg_type:3;
 863          unsigned src0_reg_file:2;
 864          unsigned src0_reg_type:3;
 865          unsigned src1_reg_file:2;
 866          unsigned src1_reg_type:3;
 867          unsigned nibctrl:1; /* gen7+ */
 868          unsigned dest_writemask:4;
 869          int dest_indirect_offset:6;
 870          unsigned dest_subreg_nr:3;
 871          unsigned dest_horiz_stride:2;
 872          unsigned dest_address_mode:1;
 873       } ia16;
 874
 875       struct {
 876          unsigned dest_reg_file:2;
 877          unsigned dest_reg_type:3;
 878          unsigned src0_reg_file:2;
 879          unsigned src0_reg_type:3;
 880          unsigned src1_reg_file:2;
 881          unsigned src1_reg_type:3;
 882          unsigned pad:1;
 883
 884          int jump_count:16;
 885       } branch_gen6;
 886
 887       struct {
 888          unsigned dest_reg_file:1; /* gen6, not gen7+ */
 889          unsigned flag_subreg_num:1;
 890          unsigned flag_reg_nr:1; /* gen7+ */
 891          unsigned pad0:1;
 892          unsigned src0_abs:1;
 893          unsigned src0_negate:1;
 894          unsigned src1_abs:1;
 895          unsigned src1_negate:1;
 896          unsigned src2_abs:1;
 897          unsigned src2_negate:1;
 898          unsigned src_type:2; /* gen7+ */
 899          unsigned dst_type:2; /* gen7+ */
 900          unsigned pad1:1;
 901          unsigned nibctrl:1; /* gen7+ */
 902          unsigned pad2:1;
 903          unsigned dest_writemask:4;
 904          unsigned dest_subreg_nr:3;
 905          unsigned dest_reg_nr:8;
 906       } da3src;
 907
 908       uint32_t ud;
 909    } bits1;
 910
 911
 912    union {
 913       struct
 914       {
 915          unsigned src0_subreg_nr:5;
 916          unsigned src0_reg_nr:8;
 917          unsigned src0_abs:1;
 918          unsigned src0_negate:1;
 919          unsigned src0_address_mode:1;
 920          unsigned src0_horiz_stride:2;
 921          unsigned src0_width:3;
 922          unsigned src0_vert_stride:4;
 923          unsigned flag_subreg_nr:1;
 924          unsigned flag_reg_nr:1; /* gen7+ */
 925          unsigned pad:5;
 926       } da1;
 927
 928       struct
 929       {
 930          int src0_indirect_offset:10;
 931          unsigned src0_subreg_nr:3;
 932          unsigned src0_abs:1;
 933          unsigned src0_negate:1;
 934          unsigned src0_address_mode:1;
 935          unsigned src0_horiz_stride:2;
 936          unsigned src0_width:3;
 937          unsigned src0_vert_stride:4;
 938          unsigned flag_subreg_nr:1;
 939          unsigned flag_reg_nr:1; /* gen7+ */
 940          unsigned pad:5;
 941       } ia1;
 942
 943       struct
 944       {
 945          unsigned src0_swz_x:2;
 946          unsigned src0_swz_y:2;
 947          unsigned src0_subreg_nr:1;
 948          unsigned src0_reg_nr:8;
 949          unsigned src0_abs:1;
 950          unsigned src0_negate:1;
 951          unsigned src0_address_mode:1;
 952          unsigned src0_swz_z:2;
 953          unsigned src0_swz_w:2;
 954          unsigned pad0:1;
 955          unsigned src0_vert_stride:4;
 956          unsigned flag_subreg_nr:1;
 957          unsigned flag_reg_nr:1; /* gen7+ */
 958          unsigned pad1:5;
 959       } da16;
 960
 961       struct
 962       {
 963          unsigned src0_swz_x:2;
 964          unsigned src0_swz_y:2;
 965          int src0_indirect_offset:6;
 966          unsigned src0_subreg_nr:3;
 967          unsigned src0_abs:1;
 968          unsigned src0_negate:1;
 969          unsigned src0_address_mode:1;
 970          unsigned src0_swz_z:2;
 971          unsigned src0_swz_w:2;
 972          unsigned pad0:1;
 973          unsigned src0_vert_stride:4;
 974          unsigned flag_subreg_nr:1;
 975          unsigned flag_reg_nr:1; /* gen7+ */
 976          unsigned pad1:5;
 977       } ia16;
 978
 979       /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
 980        *
 981        * Does not apply to Gen6+.  The SFID/message target moved to bits
 982        * 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
 983        */
 984        struct
 985        {
 986            unsigned pad:26;
 987            unsigned end_of_thread:1;
 988            unsigned pad1:1;
 989            unsigned sfid:4;
 990        } send_gen5;  /* for Ironlake only */
 991
 992       struct {
 993          unsigned src0_rep_ctrl:1;
 994          unsigned src0_swizzle:8;
 995          unsigned src0_subreg_nr:3;
 996          unsigned src0_reg_nr:8;
 997          unsigned pad0:1;
 998          unsigned src1_rep_ctrl:1;
 999          unsigned src1_swizzle:8;
1000          unsigned src1_subreg_nr_low:2;
1001       } da3src;
1002
1003       uint32_t ud;
1004    } bits2;
1005
1006    union
1007    {
1008       struct
1009       {
1010          unsigned src1_subreg_nr:5;
1011          unsigned src1_reg_nr:8;
1012          unsigned src1_abs:1;
1013          unsigned src1_negate:1;
1014          unsigned src1_address_mode:1;
1015          unsigned src1_horiz_stride:2;
1016          unsigned src1_width:3;
1017          unsigned src1_vert_stride:4;
1018          unsigned pad0:7;
1019       } da1;
1020
1021       struct
1022       {
1023          unsigned src1_swz_x:2;
1024          unsigned src1_swz_y:2;
1025          unsigned src1_subreg_nr:1;
1026          unsigned src1_reg_nr:8;
1027          unsigned src1_abs:1;
1028          unsigned src1_negate:1;
1029          unsigned src1_address_mode:1;
1030          unsigned src1_swz_z:2;
1031          unsigned src1_swz_w:2;
1032          unsigned pad1:1;
1033          unsigned src1_vert_stride:4;
1034          unsigned pad2:7;
1035       } da16;
1036
1037       struct
1038       {
1039          int  src1_indirect_offset:10;
1040          unsigned src1_subreg_nr:3;
1041          unsigned src1_abs:1;
1042          unsigned src1_negate:1;
1043          unsigned src1_address_mode:1;
1044          unsigned src1_horiz_stride:2;
1045          unsigned src1_width:3;
1046          unsigned src1_vert_stride:4;
1047          unsigned pad1:7;
1048       } ia1;
1049
1050       struct
1051       {
1052          unsigned src1_swz_x:2;
1053          unsigned src1_swz_y:2;
1054          int  src1_indirect_offset:6;
1055          unsigned src1_subreg_nr:3;
1056          unsigned src1_abs:1;
1057          unsigned src1_negate:1;
1058          unsigned pad0:1;
1059          unsigned src1_swz_z:2;
1060          unsigned src1_swz_w:2;
1061          unsigned pad1:1;
1062          unsigned src1_vert_stride:4;
1063          unsigned pad2:7;
1064       } ia16;
1065
1066
1067       struct
1068       {
1069          int  jump_count:16;    /* note: signed */
1070          unsigned  pop_count:4;
1071          unsigned  pad0:12;
1072       } if_else;
1073
1074       /* This is also used for gen7 IF/ELSE instructions */
1075       struct
1076       {
1077          /* Signed jump distance to the ip to jump to if all channels
1078           * are disabled after the break or continue.  It should point
1079           * to the end of the innermost control flow block, as that's
1080           * where some channel could get re-enabled.
1081           */
1082          int jip:16;
1083
1084          /* Signed jump distance to the location to resume execution
1085           * of this channel if it's enabled for the break or continue.
1086           */
1087          int uip:16;
1088       } break_cont;
1089
1090       /**
1091        * \defgroup SEND instructions / Message Descriptors
1092        *
1093        * @{
1094        */
1095
1096       /**
1097        * Generic Message Descriptor for Gen4 SEND instructions.  The structs
1098        * below expand function_control to something specific for their
1099        * message.  Due to struct packing issues, they duplicate these bits.
1100        *
1101        * See the G45 PRM, Volume 4, Table 14-15.
1102        */
1103       struct {
1104          unsigned function_control:16;
1105          unsigned response_length:4;
1106          unsigned msg_length:4;
1107          unsigned msg_target:4;
1108          unsigned pad1:3;
1109          unsigned end_of_thread:1;
1110       } generic;
1111
1112       /**
1113        * Generic Message Descriptor for Gen5-7 SEND instructions.
1114        *
1115        * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15.  (Sadly, most
1116        * of the information on the SEND instruction is missing from the public
1117        * Ironlake PRM.)
1118        *
1119        * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies.
1120        * According to the SEND instruction description:
1121        * "The MSb of the message description, the EOT field, always comes from
1122        *  bit 127 of the instruction word"...which is bit 31 of this field.
1123        */
1124       struct {
1125          unsigned function_control:19;
1126          unsigned header_present:1;
1127          unsigned response_length:5;
1128          unsigned msg_length:4;
1129          unsigned pad1:2;
1130          unsigned end_of_thread:1;
1131       } generic_gen5;
1132
1133       /** G45 PRM, Volume 4, Section 6.1.1.1 */
1134       struct {
1135          unsigned function:4;
1136          unsigned int_type:1;
1137          unsigned precision:1;
1138          unsigned saturate:1;
1139          unsigned data_type:1;
1140          unsigned pad0:8;
1141          unsigned response_length:4;
1142          unsigned msg_length:4;
1143          unsigned msg_target:4;
1144          unsigned pad1:3;
1145          unsigned end_of_thread:1;
1146       } math;
1147
1148       /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */
1149       struct {
1150          unsigned function:4;
1151          unsigned int_type:1;
1152          unsigned precision:1;
1153          unsigned saturate:1;
1154          unsigned data_type:1;
1155          unsigned snapshot:1;
1156          unsigned pad0:10;
1157          unsigned header_present:1;
1158          unsigned response_length:5;
1159          unsigned msg_length:4;
1160          unsigned pad1:2;
1161          unsigned end_of_thread:1;
1162       } math_gen5;
1163
1164       /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */
1165       struct {
1166          unsigned binding_table_index:8;
1167          unsigned sampler:4;
1168          unsigned return_format:2;
1169          unsigned msg_type:2;
1170          unsigned response_length:4;
1171          unsigned msg_length:4;
1172          unsigned msg_target:4;
1173          unsigned pad1:3;
1174          unsigned end_of_thread:1;
1175       } sampler;
1176
1177       /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */
1178       struct {
1179          unsigned binding_table_index:8;
1180          unsigned sampler:4;
1181          unsigned msg_type:4;
1182          unsigned response_length:4;
1183          unsigned msg_length:4;
1184          unsigned msg_target:4;
1185          unsigned pad1:3;
1186          unsigned end_of_thread:1;
1187       } sampler_g4x;
1188
1189       /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */
1190       struct {
1191          unsigned binding_table_index:8;
1192          unsigned sampler:4;
1193          unsigned msg_type:4;
1194          unsigned simd_mode:2;
1195          unsigned pad0:1;
1196          unsigned header_present:1;
1197          unsigned response_length:5;
1198          unsigned msg_length:4;
1199          unsigned pad1:2;
1200          unsigned end_of_thread:1;
1201       } sampler_gen5;
1202
1203       struct {
1204          unsigned binding_table_index:8;
1205          unsigned sampler:4;
1206          unsigned msg_type:5;
1207          unsigned simd_mode:2;
1208          unsigned header_present:1;
1209          unsigned response_length:5;
1210          unsigned msg_length:4;
1211          unsigned pad1:2;
1212          unsigned end_of_thread:1;
1213       } sampler_gen7;
1214
1215       struct brw_urb_immediate urb;
1216
1217       struct {
1218          unsigned opcode:4;
1219          unsigned offset:6;
1220          unsigned swizzle_control:2;
1221          unsigned pad:1;
1222          unsigned allocate:1;
1223          unsigned used:1;
1224          unsigned complete:1;
1225          unsigned pad0:3;
1226          unsigned header_present:1;
1227          unsigned response_length:5;
1228          unsigned msg_length:4;
1229          unsigned pad1:2;
1230          unsigned end_of_thread:1;
1231       } urb_gen5;
1232
1233       struct {
1234          unsigned opcode:3;
1235          unsigned offset:11;
1236          unsigned swizzle_control:1;
1237          unsigned complete:1;
1238          unsigned per_slot_offset:1;
1239          unsigned pad0:2;
1240          unsigned header_present:1;
1241          unsigned response_length:5;
1242          unsigned msg_length:4;
1243          unsigned pad1:2;
1244          unsigned end_of_thread:1;
1245       } urb_gen7;
1246
1247       /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
1248       struct {
1249          unsigned binding_table_index:8;
1250          unsigned msg_control:4;
1251          unsigned msg_type:2;
1252          unsigned target_cache:2;
1253          unsigned response_length:4;
1254          unsigned msg_length:4;
1255          unsigned msg_target:4;
1256          unsigned pad1:3;
1257          unsigned end_of_thread:1;
1258       } dp_read;
1259
1260       /** G45 PRM, Volume 4, Section 5.10.1.1.2 */
1261       struct {
1262          unsigned binding_table_index:8;
1263          unsigned msg_control:3;
1264          unsigned msg_type:3;
1265          unsigned target_cache:2;
1266          unsigned response_length:4;
1267          unsigned msg_length:4;
1268          unsigned msg_target:4;
1269          unsigned pad1:3;
1270          unsigned end_of_thread:1;
1271       } dp_read_g4x;
1272
1273       /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1274       struct {
1275          unsigned binding_table_index:8;
1276          unsigned msg_control:3;
1277          unsigned msg_type:3;
1278          unsigned target_cache:2;
1279          unsigned pad0:3;
1280          unsigned header_present:1;
1281          unsigned response_length:5;
1282          unsigned msg_length:4;
1283          unsigned pad1:2;
1284          unsigned end_of_thread:1;
1285       } dp_read_gen5;
1286
1287       /** G45 PRM, Volume 4, Section 5.10.1.1.2.  For both Gen4 and G45. */
1288       struct {
1289          unsigned binding_table_index:8;
1290          unsigned msg_control:3;
1291          unsigned last_render_target:1;
1292          unsigned msg_type:3;
1293          unsigned send_commit_msg:1;
1294          unsigned response_length:4;
1295          unsigned msg_length:4;
1296          unsigned msg_target:4;
1297          unsigned pad1:3;
1298          unsigned end_of_thread:1;
1299       } dp_write;
1300
1301       /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1302       struct {
1303          unsigned binding_table_index:8;
1304          unsigned msg_control:3;
1305          unsigned last_render_target:1;
1306          unsigned msg_type:3;
1307          unsigned send_commit_msg:1;
1308          unsigned pad0:3;
1309          unsigned header_present:1;
1310          unsigned response_length:5;
1311          unsigned msg_length:4;
1312          unsigned pad1:2;
1313          unsigned end_of_thread:1;
1314       } dp_write_gen5;
1315
1316       /**
1317        * Message for the Sandybridge Sampler Cache or Constant Cache Data Port.
1318        *
1319        * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
1320        **/
1321       struct {
1322          unsigned binding_table_index:8;
1323          unsigned msg_control:5;
1324          unsigned msg_type:3;
1325          unsigned pad0:3;
1326          unsigned header_present:1;
1327          unsigned response_length:5;
1328          unsigned msg_length:4;
1329          unsigned pad1:2;
1330          unsigned end_of_thread:1;
1331       } gen6_dp_sampler_const_cache;
1332
1333       /**
1334        * Message for the Sandybridge Render Cache Data Port.
1335        *
1336        * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1,
1337        * Section 3.9.2.1.1: Message Descriptor.
1338        *
1339        * "Slot Group Select" and "Last Render Target" are part of the
1340        * 5-bit message control for Render Target Write messages.  See
1341        * Section 3.9.9.2.1 of the same volume.
1342        */
1343       struct {
1344          unsigned binding_table_index:8;
1345          unsigned msg_control:3;
1346          unsigned slot_group_select:1;
1347          unsigned last_render_target:1;
1348          unsigned msg_type:4;
1349          unsigned send_commit_msg:1;
1350          unsigned pad0:1;
1351          unsigned header_present:1;
1352          unsigned response_length:5;
1353          unsigned msg_length:4;
1354          unsigned pad1:2;
1355          unsigned end_of_thread:1;
1356       } gen6_dp;
1357
1358       /**
1359        * Message for any of the Gen7 Data Port caches.
1360        *
1361        * Most fields are defined in the Ivybridge PRM, Volume 4 Part 1,
1362        * section 3.9.2.1.1 "Message Descriptor".  Once again, "Slot Group
1363        * Select" and "Last Render Target" are part of the 6-bit message
1364        * control for Render Target Writes (section 3.9.11.2).
1365        */
1366       struct {
1367          unsigned binding_table_index:8;
1368          unsigned msg_control:3;
1369          unsigned slot_group_select:1;
1370          unsigned last_render_target:1;
1371          unsigned msg_control_pad:1;
1372          unsigned msg_type:4;
1373          unsigned pad1:1;
1374          unsigned header_present:1;
1375          unsigned response_length:5;
1376          unsigned msg_length:4;
1377          unsigned pad2:2;
1378          unsigned end_of_thread:1;
1379       } gen7_dp;
1380
1381       /**
1382        * Message for the Gen7 Pixel Interpolator.
1383        *
1384        * Defined in the Ivybridge PRM, Volume 4 Part 2,
1385        * section 4.1.1.1.
1386        */
1387       struct {
1388          GLuint msg_data:8;
1389          GLuint pad1:3;
1390          GLuint slot_group:1;
1391          GLuint msg_type:2;
1392          GLuint interpolation_mode:1;
1393          GLuint pad2:1;
1394          GLuint simd_mode:1;
1395          GLuint pad3:1;
1396          GLuint response_length:5;
1397          GLuint msg_length:4;
1398          GLuint pad4:2;
1399          GLuint end_of_thread:1;
1400       } gen7_pi;
1401       /** @} */
1402
1403       struct {
1404          unsigned src1_subreg_nr_high:1;
1405          unsigned src1_reg_nr:8;
1406          unsigned pad0:1;
1407          unsigned src2_rep_ctrl:1;
1408          unsigned src2_swizzle:8;
1409          unsigned src2_subreg_nr:3;
1410          unsigned src2_reg_nr:8;
1411          unsigned pad1:2;
1412       } da3src;
1413
1414       int d;
1415       unsigned ud;
1416       float f;
1417    } bits3;
1418 };
1419
1420 struct brw_compact_instruction {
1421    struct {
1422       unsigned opcode:7;          /*  0- 6 */
1423       unsigned debug_control:1;   /*  7- 7 */
1424       unsigned control_index:5;   /*  8-12 */
1425       unsigned data_type_index:5; /* 13-17 */
1426       unsigned sub_reg_index:5;   /* 18-22 */
1427       unsigned acc_wr_control:1;  /* 23-23 */
1428       unsigned conditionalmod:4;  /* 24-27 */
1429       unsigned flag_subreg_nr:1;     /* 28-28 */
1430       unsigned cmpt_ctrl:1;       /* 29-29 */
1431       unsigned src0_index:2;      /* 30-31 */
1432    } dw0;
1433
1434    struct {
1435       unsigned src0_index:3;  /* 32-24 */
1436       unsigned src1_index:5;  /* 35-39 */
1437       unsigned dst_reg_nr:8;  /* 40-47 */
1438       unsigned src0_reg_nr:8; /* 48-55 */
1439       unsigned src1_reg_nr:8; /* 56-63 */
1440    } dw1;
1441 };
1442
1443 #endif