src/mesa/drivers/dri/i965/brw_structs.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_STRUCTS_H
  34 #define BRW_STRUCTS_H
  35
  36
  37 /** Number of general purpose registers (VS, WM, etc) */
  38 #define BRW_MAX_GRF 128
  39
  40 /** Number of message register file registers */
  41 #define BRW_MAX_MRF 16
  42
  43
  44 /* Command packets:
  45  */
  46 struct header
  47 {
  48    GLuint length:16;
  49    GLuint opcode:16;
  50 };
  51
  52
  53 union header_union
  54 {
  55    struct header bits;
  56    GLuint dword;
  57 };
  58
  59 struct brw_3d_control
  60 {
  61    struct
  62    {
  63       GLuint length:8;
  64       GLuint notify_enable:1;
  65       GLuint pad:3;
  66       GLuint wc_flush_enable:1;
  67       GLuint depth_stall_enable:1;
  68       GLuint operation:2;
  69       GLuint opcode:16;
  70    } header;
  71
  72    struct
  73    {
  74       GLuint pad:2;
  75       GLuint dest_addr_type:1;
  76       GLuint dest_addr:29;
  77    } dest;
  78
  79    GLuint dword2;
  80    GLuint dword3;
  81 };
  82
  83
  84 struct brw_3d_primitive
  85 {
  86    struct
  87    {
  88       GLuint length:8;
  89       GLuint pad:2;
  90       GLuint topology:5;
  91       GLuint indexed:1;
  92       GLuint opcode:16;
  93    } header;
  94
  95    GLuint verts_per_instance;
  96    GLuint start_vert_location;
  97    GLuint instance_count;
  98    GLuint start_instance_location;
  99    GLuint base_vert_location;
 100 };
 101
 102 /* These seem to be passed around as function args, so it works out
 103  * better to keep them as #defines:
 104  */
 105 #define BRW_FLUSH_READ_CACHE           0x1
 106 #define BRW_FLUSH_STATE_CACHE          0x2
 107 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
 108 #define BRW_FLUSH_SNAPSHOT_COUNTERS    0x8
 109
 110 struct brw_mi_flush
 111 {
 112    GLuint flags:4;
 113    GLuint pad:12;
 114    GLuint opcode:16;
 115 };
 116
 117 struct brw_vf_statistics
 118 {
 119    GLuint statistics_enable:1;
 120    GLuint pad:15;
 121    GLuint opcode:16;
 122 };
 123
 124
 125
 126 struct brw_binding_table_pointers
 127 {
 128    struct header header;
 129    GLuint vs;
 130    GLuint gs;
 131    GLuint clp;
 132    GLuint sf;
 133    GLuint wm;
 134 };
 135
 136
 137 struct brw_blend_constant_color
 138 {
 139    struct header header;
 140    GLfloat blend_constant_color[4];
 141 };
 142
 143
 144 struct brw_depthbuffer
 145 {
 146    union header_union header;
 147
 148    union {
 149       struct {
 150          GLuint pitch:18;
 151          GLuint format:3;
 152          GLuint pad:2;
 153          GLuint software_tiled_rendering_mode:2;
 154          GLuint depth_offset_disable:1;
 155          GLuint tile_walk:1;
 156          GLuint tiled_surface:1;
 157          GLuint pad2:1;
 158          GLuint surface_type:3;
 159       } bits;
 160       GLuint dword;
 161    } dword1;
 162
 163    GLuint dword2_base_addr;
 164
 165    union {
 166       struct {
 167          GLuint pad:1;
 168          GLuint mipmap_layout:1;
 169          GLuint lod:4;
 170          GLuint width:13;
 171          GLuint height:13;
 172       } bits;
 173       GLuint dword;
 174    } dword3;
 175
 176    union {
 177       struct {
 178          GLuint pad:10;
 179          GLuint min_array_element:11;
 180          GLuint depth:11;
 181       } bits;
 182       GLuint dword;
 183    } dword4;
 184 };
 185
 186 struct brw_depthbuffer_g4x
 187 {
 188    union header_union header;
 189
 190    union {
 191       struct {
 192          GLuint pitch:18;
 193          GLuint format:3;
 194          GLuint pad:2;
 195          GLuint software_tiled_rendering_mode:2;
 196          GLuint depth_offset_disable:1;
 197          GLuint tile_walk:1;
 198          GLuint tiled_surface:1;
 199          GLuint pad2:1;
 200          GLuint surface_type:3;
 201       } bits;
 202       GLuint dword;
 203    } dword1;
 204
 205    GLuint dword2_base_addr;
 206
 207    union {
 208       struct {
 209          GLuint pad:1;
 210          GLuint mipmap_layout:1;
 211          GLuint lod:4;
 212          GLuint width:13;
 213          GLuint height:13;
 214       } bits;
 215       GLuint dword;
 216    } dword3;
 217
 218    union {
 219       struct {
 220          GLuint pad:10;
 221          GLuint min_array_element:11;
 222          GLuint depth:11;
 223       } bits;
 224       GLuint dword;
 225    } dword4;
 226
 227    union {
 228       struct {
 229          GLuint xoffset:16;
 230          GLuint yoffset:16;
 231       } bits;
 232       GLuint dword;
 233    } dword5;   /* NEW in Integrated Graphics Device */
 234 };
 235
 236 struct brw_drawrect
 237 {
 238    struct header header;
 239    GLuint xmin:16;
 240    GLuint ymin:16;
 241    GLuint xmax:16;
 242    GLuint ymax:16;
 243    GLuint xorg:16;
 244    GLuint yorg:16;
 245 };
 246
 247
 248
 249
 250 struct brw_global_depth_offset_clamp
 251 {
 252    struct header header;
 253    GLfloat depth_offset_clamp;
 254 };
 255
 256 struct brw_indexbuffer
 257 {
 258    union {
 259       struct
 260       {
 261          GLuint length:8;
 262          GLuint index_format:2;
 263          GLuint cut_index_enable:1;
 264          GLuint pad:5;
 265          GLuint opcode:16;
 266       } bits;
 267       GLuint dword;
 268
 269    } header;
 270
 271    GLuint buffer_start;
 272    GLuint buffer_end;
 273 };
 274
 275 /* NEW in Integrated Graphics Device */
 276 struct brw_aa_line_parameters
 277 {
 278    struct header header;
 279
 280    struct {
 281       GLuint aa_coverage_slope:8;
 282       GLuint pad0:8;
 283       GLuint aa_coverage_bias:8;
 284       GLuint pad1:8;
 285    } bits0;
 286
 287    struct {
 288       GLuint aa_coverage_endcap_slope:8;
 289       GLuint pad0:8;
 290       GLuint aa_coverage_endcap_bias:8;
 291       GLuint pad1:8;
 292    } bits1;
 293 };
 294
 295 struct brw_line_stipple
 296 {
 297    struct header header;
 298
 299    struct
 300    {
 301       GLuint pattern:16;
 302       GLuint pad:16;
 303    } bits0;
 304
 305    struct
 306    {
 307       GLuint repeat_count:9;
 308       GLuint pad:7;
 309       GLuint inverse_repeat_count:16;
 310    } bits1;
 311 };
 312
 313
 314 struct brw_pipelined_state_pointers
 315 {
 316    struct header header;
 317
 318    struct {
 319       GLuint pad:5;
 320       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 321    } vs;
 322
 323    struct
 324    {
 325       GLuint enable:1;
 326       GLuint pad:4;
 327       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 328    } gs;
 329
 330    struct
 331    {
 332       GLuint enable:1;
 333       GLuint pad:4;
 334       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 335    } clp;
 336
 337    struct
 338    {
 339       GLuint pad:5;
 340       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 341    } sf;
 342
 343    struct
 344    {
 345       GLuint pad:5;
 346       GLuint offset:27; /* Offset from GENERAL_STATE_BASE */
 347    } wm;
 348
 349    struct
 350    {
 351       GLuint pad:5;
 352       GLuint offset:27; /* Offset from GENERAL_STATE_BASE. KW: check me! */
 353    } cc;
 354 };
 355
 356
 357 struct brw_polygon_stipple_offset
 358 {
 359    struct header header;
 360
 361    struct {
 362       GLuint y_offset:5;
 363       GLuint pad:3;
 364       GLuint x_offset:5;
 365       GLuint pad0:19;
 366    } bits0;
 367 };
 368
 369
 370
 371 struct brw_polygon_stipple
 372 {
 373    struct header header;
 374    GLuint stipple[32];
 375 };
 376
 377
 378
 379 struct brw_pipeline_select
 380 {
 381    struct
 382    {
 383       GLuint pipeline_select:1;
 384       GLuint pad:15;
 385       GLuint opcode:16;
 386    } header;
 387 };
 388
 389
 390 struct brw_pipe_control
 391 {
 392    struct
 393    {
 394       GLuint length:8;
 395       GLuint notify_enable:1;
 396       GLuint texture_cache_flush_enable:1;
 397       GLuint indirect_state_pointers_disable:1;
 398       GLuint instruction_state_cache_flush_enable:1;
 399       GLuint write_cache_flush_enable:1;
 400       GLuint depth_stall_enable:1;
 401       GLuint post_sync_operation:2;
 402
 403       GLuint opcode:16;
 404    } header;
 405
 406    struct
 407    {
 408       GLuint pad:2;
 409       GLuint dest_addr_type:1;
 410       GLuint dest_addr:29;
 411    } bits1;
 412
 413    GLuint data0;
 414    GLuint data1;
 415 };
 416
 417
 418 struct brw_urb_fence
 419 {
 420    struct
 421    {
 422       GLuint length:8;
 423       GLuint vs_realloc:1;
 424       GLuint gs_realloc:1;
 425       GLuint clp_realloc:1;
 426       GLuint sf_realloc:1;
 427       GLuint vfe_realloc:1;
 428       GLuint cs_realloc:1;
 429       GLuint pad:2;
 430       GLuint opcode:16;
 431    } header;
 432
 433    struct
 434    {
 435       GLuint vs_fence:10;
 436       GLuint gs_fence:10;
 437       GLuint clp_fence:10;
 438       GLuint pad:2;
 439    } bits0;
 440
 441    struct
 442    {
 443       GLuint sf_fence:10;
 444       GLuint vf_fence:10;
 445       GLuint cs_fence:11;
 446       GLuint pad:1;
 447    } bits1;
 448 };
 449
 450 struct brw_cs_urb_state
 451 {
 452    struct header header;
 453
 454    struct
 455    {
 456       GLuint nr_urb_entries:3;
 457       GLuint pad:1;
 458       GLuint urb_entry_size:5;
 459       GLuint pad0:23;
 460    } bits0;
 461 };
 462
 463 struct brw_constant_buffer
 464 {
 465    struct
 466    {
 467       GLuint length:8;
 468       GLuint valid:1;
 469       GLuint pad:7;
 470       GLuint opcode:16;
 471    } header;
 472
 473    struct
 474    {
 475       GLuint buffer_length:6;
 476       GLuint buffer_address:26;
 477    } bits0;
 478 };
 479
 480 struct brw_state_base_address
 481 {
 482    struct header header;
 483
 484    struct
 485    {
 486       GLuint modify_enable:1;
 487       GLuint pad:4;
 488       GLuint general_state_address:27;
 489    } bits0;
 490
 491    struct
 492    {
 493       GLuint modify_enable:1;
 494       GLuint pad:4;
 495       GLuint surface_state_address:27;
 496    } bits1;
 497
 498    struct
 499    {
 500       GLuint modify_enable:1;
 501       GLuint pad:4;
 502       GLuint indirect_object_state_address:27;
 503    } bits2;
 504
 505    struct
 506    {
 507       GLuint modify_enable:1;
 508       GLuint pad:11;
 509       GLuint general_state_upper_bound:20;
 510    } bits3;
 511
 512    struct
 513    {
 514       GLuint modify_enable:1;
 515       GLuint pad:11;
 516       GLuint indirect_object_state_upper_bound:20;
 517    } bits4;
 518 };
 519
 520 struct brw_state_prefetch
 521 {
 522    struct header header;
 523
 524    struct
 525    {
 526       GLuint prefetch_count:3;
 527       GLuint pad:3;
 528       GLuint prefetch_pointer:26;
 529    } bits0;
 530 };
 531
 532 struct brw_system_instruction_pointer
 533 {
 534    struct header header;
 535
 536    struct
 537    {
 538       GLuint pad:4;
 539       GLuint system_instruction_pointer:28;
 540    } bits0;
 541 };
 542
 543
 544
 545
 546 /* State structs for the various fixed function units:
 547  */
 548
 549
 550 struct thread0
 551 {
 552    GLuint pad0:1;
 553    GLuint grf_reg_count:3;
 554    GLuint pad1:2;
 555    GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
 556 };
 557
 558 struct thread1
 559 {
 560    GLuint ext_halt_exception_enable:1;
 561    GLuint sw_exception_enable:1;
 562    GLuint mask_stack_exception_enable:1;
 563    GLuint timeout_exception_enable:1;
 564    GLuint illegal_op_exception_enable:1;
 565    GLuint pad0:3;
 566    GLuint depth_coef_urb_read_offset:6; /* WM only */
 567    GLuint pad1:2;
 568    GLuint floating_point_mode:1;
 569    GLuint thread_priority:1;
 570    GLuint binding_table_entry_count:8;
 571    GLuint pad3:5;
 572    GLuint single_program_flow:1;
 573 };
 574
 575 struct thread2
 576 {
 577    GLuint per_thread_scratch_space:4;
 578    GLuint pad0:6;
 579    GLuint scratch_space_base_pointer:22;
 580 };
 581
 582
 583 struct thread3
 584 {
 585    GLuint dispatch_grf_start_reg:4;
 586    GLuint urb_entry_read_offset:6;
 587    GLuint pad0:1;
 588    GLuint urb_entry_read_length:6;
 589    GLuint pad1:1;
 590    GLuint const_urb_entry_read_offset:6;
 591    GLuint pad2:1;
 592    GLuint const_urb_entry_read_length:6;
 593    GLuint pad3:1;
 594 };
 595
 596
 597
 598 struct brw_clip_unit_state
 599 {
 600    struct thread0 thread0;
 601    struct
 602    {
 603       GLuint pad0:7;
 604       GLuint sw_exception_enable:1;
 605       GLuint pad1:3;
 606       GLuint mask_stack_exception_enable:1;
 607       GLuint pad2:1;
 608       GLuint illegal_op_exception_enable:1;
 609       GLuint pad3:2;
 610       GLuint floating_point_mode:1;
 611       GLuint thread_priority:1;
 612       GLuint binding_table_entry_count:8;
 613       GLuint pad4:5;
 614       GLuint single_program_flow:1;
 615    } thread1;
 616
 617    struct thread2 thread2;
 618    struct thread3 thread3;
 619
 620    struct
 621    {
 622       GLuint pad0:9;
 623       GLuint gs_output_stats:1; /* not always */
 624       GLuint stats_enable:1;
 625       GLuint nr_urb_entries:7;
 626       GLuint pad1:1;
 627       GLuint urb_entry_allocation_size:5;
 628       GLuint pad2:1;
 629       GLuint max_threads:5;     /* may be less */
 630       GLuint pad3:2;
 631    } thread4;
 632
 633    struct
 634    {
 635       GLuint pad0:13;
 636       GLuint clip_mode:3;
 637       GLuint userclip_enable_flags:8;
 638       GLuint userclip_must_clip:1;
 639       GLuint negative_w_clip_test:1;
 640       GLuint guard_band_enable:1;
 641       GLuint viewport_z_clip_enable:1;
 642       GLuint viewport_xy_clip_enable:1;
 643       GLuint vertex_position_space:1;
 644       GLuint api_mode:1;
 645       GLuint pad2:1;
 646    } clip5;
 647
 648    struct
 649    {
 650       GLuint pad0:5;
 651       GLuint clipper_viewport_state_ptr:27;
 652    } clip6;
 653
 654
 655    GLfloat viewport_xmin;
 656    GLfloat viewport_xmax;
 657    GLfloat viewport_ymin;
 658    GLfloat viewport_ymax;
 659 };
 660
 661 struct gen6_blend_state
 662 {
 663    struct {
 664       GLuint dest_blend_factor:5;
 665       GLuint source_blend_factor:5;
 666       GLuint pad3:1;
 667       GLuint blend_func:3;
 668       GLuint pad2:1;
 669       GLuint ia_dest_blend_factor:5;
 670       GLuint ia_source_blend_factor:5;
 671       GLuint pad1:1;
 672       GLuint ia_blend_func:3;
 673       GLuint pad0:1;
 674       GLuint ia_blend_enable:1;
 675       GLuint blend_enable:1;
 676    } blend0;
 677
 678    struct {
 679       GLuint post_blend_clamp_enable:1;
 680       GLuint pre_blend_clamp_enable:1;
 681       GLuint clamp_range:2;
 682       GLuint pad0:4;
 683       GLuint x_dither_offset:2;
 684       GLuint y_dither_offset:2;
 685       GLuint dither_enable:1;
 686       GLuint alpha_test_func:3;
 687       GLuint alpha_test_enable:1;
 688       GLuint pad1:1;
 689       GLuint logic_op_func:4;
 690       GLuint logic_op_enable:1;
 691       GLuint pad2:1;
 692       GLuint write_disable_b:1;
 693       GLuint write_disable_g:1;
 694       GLuint write_disable_r:1;
 695       GLuint write_disable_a:1;
 696       GLuint pad3:1;
 697       GLuint alpha_to_coverage_dither:1;
 698       GLuint alpha_to_one:1;
 699       GLuint alpha_to_coverage:1;
 700    } blend1;
 701 };
 702
 703 struct gen6_color_calc_state
 704 {
 705    struct {
 706       GLuint alpha_test_format:1;
 707       GLuint pad0:14;
 708       GLuint round_disable:1;
 709       GLuint bf_stencil_ref:8;
 710       GLuint stencil_ref:8;
 711    } cc0;
 712
 713    union {
 714       GLfloat alpha_ref_f;
 715       struct {
 716          GLuint ui:8;
 717          GLuint pad0:24;
 718       } alpha_ref_fi;
 719    } cc1;
 720
 721    GLfloat constant_r;
 722    GLfloat constant_g;
 723    GLfloat constant_b;
 724    GLfloat constant_a;
 725 };
 726
 727 struct gen6_depth_stencil_state
 728 {
 729    struct {
 730       GLuint pad0:3;
 731       GLuint bf_stencil_pass_depth_pass_op:3;
 732       GLuint bf_stencil_pass_depth_fail_op:3;
 733       GLuint bf_stencil_fail_op:3;
 734       GLuint bf_stencil_func:3;
 735       GLuint bf_stencil_enable:1;
 736       GLuint pad1:2;
 737       GLuint stencil_write_enable:1;
 738       GLuint stencil_pass_depth_pass_op:3;
 739       GLuint stencil_pass_depth_fail_op:3;
 740       GLuint stencil_fail_op:3;
 741       GLuint stencil_func:3;
 742       GLuint stencil_enable:1;
 743    } ds0;
 744
 745    struct {
 746       GLuint bf_stencil_write_mask:8;
 747       GLuint bf_stencil_test_mask:8;
 748       GLuint stencil_write_mask:8;
 749       GLuint stencil_test_mask:8;
 750    } ds1;
 751
 752    struct {
 753       GLuint pad0:26;
 754       GLuint depth_write_enable:1;
 755       GLuint depth_test_func:3;
 756       GLuint pad1:1;
 757       GLuint depth_test_enable:1;
 758    } ds2;
 759 };
 760
 761 struct brw_cc_unit_state
 762 {
 763    struct
 764    {
 765       GLuint pad0:3;
 766       GLuint bf_stencil_pass_depth_pass_op:3;
 767       GLuint bf_stencil_pass_depth_fail_op:3;
 768       GLuint bf_stencil_fail_op:3;
 769       GLuint bf_stencil_func:3;
 770       GLuint bf_stencil_enable:1;
 771       GLuint pad1:2;
 772       GLuint stencil_write_enable:1;
 773       GLuint stencil_pass_depth_pass_op:3;
 774       GLuint stencil_pass_depth_fail_op:3;
 775       GLuint stencil_fail_op:3;
 776       GLuint stencil_func:3;
 777       GLuint stencil_enable:1;
 778    } cc0;
 779
 780
 781    struct
 782    {
 783       GLuint bf_stencil_ref:8;
 784       GLuint stencil_write_mask:8;
 785       GLuint stencil_test_mask:8;
 786       GLuint stencil_ref:8;
 787    } cc1;
 788
 789
 790    struct
 791    {
 792       GLuint logicop_enable:1;
 793       GLuint pad0:10;
 794       GLuint depth_write_enable:1;
 795       GLuint depth_test_function:3;
 796       GLuint depth_test:1;
 797       GLuint bf_stencil_write_mask:8;
 798       GLuint bf_stencil_test_mask:8;
 799    } cc2;
 800
 801
 802    struct
 803    {
 804       GLuint pad0:8;
 805       GLuint alpha_test_func:3;
 806       GLuint alpha_test:1;
 807       GLuint blend_enable:1;
 808       GLuint ia_blend_enable:1;
 809       GLuint pad1:1;
 810       GLuint alpha_test_format:1;
 811       GLuint pad2:16;
 812    } cc3;
 813
 814    struct
 815    {
 816       GLuint pad0:5;
 817       GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 818    } cc4;
 819
 820    struct
 821    {
 822       GLuint pad0:2;
 823       GLuint ia_dest_blend_factor:5;
 824       GLuint ia_src_blend_factor:5;
 825       GLuint ia_blend_function:3;
 826       GLuint statistics_enable:1;
 827       GLuint logicop_func:4;
 828       GLuint pad1:11;
 829       GLuint dither_enable:1;
 830    } cc5;
 831
 832    struct
 833    {
 834       GLuint clamp_post_alpha_blend:1;
 835       GLuint clamp_pre_alpha_blend:1;
 836       GLuint clamp_range:2;
 837       GLuint pad0:11;
 838       GLuint y_dither_offset:2;
 839       GLuint x_dither_offset:2;
 840       GLuint dest_blend_factor:5;
 841       GLuint src_blend_factor:5;
 842       GLuint blend_function:3;
 843    } cc6;
 844
 845    struct {
 846       union {
 847          GLfloat f;
 848          GLubyte ub[4];
 849       } alpha_ref;
 850    } cc7;
 851 };
 852
 853 struct brw_sf_unit_state
 854 {
 855    struct thread0 thread0;
 856    struct thread1 thread1;
 857    struct thread2 thread2;
 858    struct thread3 thread3;
 859
 860    struct
 861    {
 862       GLuint pad0:10;
 863       GLuint stats_enable:1;
 864       GLuint nr_urb_entries:7;
 865       GLuint pad1:1;
 866       GLuint urb_entry_allocation_size:5;
 867       GLuint pad2:1;
 868       GLuint max_threads:6;
 869       GLuint pad3:1;
 870    } thread4;
 871
 872    struct
 873    {
 874       GLuint front_winding:1;
 875       GLuint viewport_transform:1;
 876       GLuint pad0:3;
 877       GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 878    } sf5;
 879
 880    struct
 881    {
 882       GLuint pad0:9;
 883       GLuint dest_org_vbias:4;
 884       GLuint dest_org_hbias:4;
 885       GLuint scissor:1;
 886       GLuint disable_2x2_trifilter:1;
 887       GLuint disable_zero_pix_trifilter:1;
 888       GLuint point_rast_rule:2;
 889       GLuint line_endcap_aa_region_width:2;
 890       GLuint line_width:4;
 891       GLuint fast_scissor_disable:1;
 892       GLuint cull_mode:2;
 893       GLuint aa_enable:1;
 894    } sf6;
 895
 896    struct
 897    {
 898       GLuint point_size:11;
 899       GLuint use_point_size_state:1;
 900       GLuint subpixel_precision:1;
 901       GLuint sprite_point:1;
 902       GLuint pad0:10;
 903       GLuint aa_line_distance_mode:1;
 904       GLuint trifan_pv:2;
 905       GLuint linestrip_pv:2;
 906       GLuint tristrip_pv:2;
 907       GLuint line_last_pixel_enable:1;
 908    } sf7;
 909
 910 };
 911
 912 struct gen6_scissor_rect
 913 {
 914    GLuint xmin:16;
 915    GLuint ymin:16;
 916    GLuint xmax:16;
 917    GLuint ymax:16;
 918 };
 919
 920 struct brw_gs_unit_state
 921 {
 922    struct thread0 thread0;
 923    struct thread1 thread1;
 924    struct thread2 thread2;
 925    struct thread3 thread3;
 926
 927    struct
 928    {
 929       GLuint pad0:8;
 930       GLuint rendering_enable:1; /* for Ironlake */
 931       GLuint pad4:1;
 932       GLuint stats_enable:1;
 933       GLuint nr_urb_entries:7;
 934       GLuint pad1:1;
 935       GLuint urb_entry_allocation_size:5;
 936       GLuint pad2:1;
 937       GLuint max_threads:5;
 938       GLuint pad3:2;
 939    } thread4;
 940
 941    struct
 942    {
 943       GLuint sampler_count:3;
 944       GLuint pad0:2;
 945       GLuint sampler_state_pointer:27;
 946    } gs5;
 947
 948
 949    struct
 950    {
 951       GLuint max_vp_index:4;
 952       GLuint pad0:12;
 953       GLuint svbi_post_inc_value:10;
 954       GLuint pad1:1;
 955       GLuint svbi_post_inc_enable:1;
 956       GLuint svbi_payload:1;
 957       GLuint discard_adjaceny:1;
 958       GLuint reorder_enable:1;
 959       GLuint pad2:1;
 960    } gs6;
 961 };
 962
 963
 964 struct brw_vs_unit_state
 965 {
 966    struct thread0 thread0;
 967    struct thread1 thread1;
 968    struct thread2 thread2;
 969    struct thread3 thread3;
 970
 971    struct
 972    {
 973       GLuint pad0:10;
 974       GLuint stats_enable:1;
 975       GLuint nr_urb_entries:7;
 976       GLuint pad1:1;
 977       GLuint urb_entry_allocation_size:5;
 978       GLuint pad2:1;
 979       GLuint max_threads:6;
 980       GLuint pad3:1;
 981    } thread4;
 982
 983    struct
 984    {
 985       GLuint sampler_count:3;
 986       GLuint pad0:2;
 987       GLuint sampler_state_pointer:27;
 988    } vs5;
 989
 990    struct
 991    {
 992       GLuint vs_enable:1;
 993       GLuint vert_cache_disable:1;
 994       GLuint pad0:30;
 995    } vs6;
 996 };
 997
 998
 999 struct brw_wm_unit_state
1000 {
1001    struct thread0 thread0;
1002    struct thread1 thread1;
1003    struct thread2 thread2;
1004    struct thread3 thread3;
1005
1006    struct {
1007       GLuint stats_enable:1;
1008       GLuint depth_buffer_clear:1;
1009       GLuint sampler_count:3;
1010       GLuint sampler_state_pointer:27;
1011    } wm4;
1012
1013    struct
1014    {
1015       GLuint enable_8_pix:1;
1016       GLuint enable_16_pix:1;
1017       GLuint enable_32_pix:1;
1018       GLuint enable_con_32_pix:1;
1019       GLuint enable_con_64_pix:1;
1020       GLuint pad0:5;
1021       GLuint legacy_global_depth_bias:1;
1022       GLuint line_stipple:1;
1023       GLuint depth_offset:1;
1024       GLuint polygon_stipple:1;
1025       GLuint line_aa_region_width:2;
1026       GLuint line_endcap_aa_region_width:2;
1027       GLuint early_depth_test:1;
1028       GLuint thread_dispatch_enable:1;
1029       GLuint program_uses_depth:1;
1030       GLuint program_computes_depth:1;
1031       GLuint program_uses_killpixel:1;
1032       GLuint legacy_line_rast: 1;
1033       GLuint transposed_urb_read_enable:1;
1034       GLuint max_threads:7;
1035    } wm5;
1036
1037    GLfloat global_depth_offset_constant;
1038    GLfloat global_depth_offset_scale;
1039
1040    /* for Ironlake only */
1041    struct {
1042       GLuint pad0:1;
1043       GLuint grf_reg_count_1:3;
1044       GLuint pad1:2;
1045       GLuint kernel_start_pointer_1:26;
1046    } wm8;
1047
1048    struct {
1049       GLuint pad0:1;
1050       GLuint grf_reg_count_2:3;
1051       GLuint pad1:2;
1052       GLuint kernel_start_pointer_2:26;
1053    } wm9;
1054
1055    struct {
1056       GLuint pad0:1;
1057       GLuint grf_reg_count_3:3;
1058       GLuint pad1:2;
1059       GLuint kernel_start_pointer_3:26;
1060    } wm10;
1061 };
1062
1063 struct brw_sampler_default_color {
1064    GLfloat color[4];
1065 };
1066
1067 struct gen5_sampler_default_color {
1068    uint8_t ub[4];
1069    float f[4];
1070    uint16_t hf[4];
1071    uint16_t us[4];
1072    int16_t s[4];
1073    uint8_t b[4];
1074 };
1075
1076 struct brw_sampler_state
1077 {
1078
1079    struct
1080    {
1081       GLuint shadow_function:3;
1082       GLuint lod_bias:11;
1083       GLuint min_filter:3;
1084       GLuint mag_filter:3;
1085       GLuint mip_filter:2;
1086       GLuint base_level:5;
1087       GLuint min_mag_neq:1;
1088       GLuint lod_preclamp:1;
1089       GLuint default_color_mode:1;
1090       GLuint pad0:1;
1091       GLuint disable:1;
1092    } ss0;
1093
1094    struct
1095    {
1096       GLuint r_wrap_mode:3;
1097       GLuint t_wrap_mode:3;
1098       GLuint s_wrap_mode:3;
1099       GLuint cube_control_mode:1;
1100       GLuint pad:2;
1101       GLuint max_lod:10;
1102       GLuint min_lod:10;
1103    } ss1;
1104
1105
1106    struct
1107    {
1108       GLuint pad:5;
1109       GLuint default_color_pointer:27;
1110    } ss2;
1111
1112    struct
1113    {
1114       GLuint non_normalized_coord:1;
1115       GLuint pad:12;
1116       GLuint address_round:6;
1117       GLuint max_aniso:3;
1118       GLuint chroma_key_mode:1;
1119       GLuint chroma_key_index:2;
1120       GLuint chroma_key_enable:1;
1121       GLuint monochrome_filter_width:3;
1122       GLuint monochrome_filter_height:3;
1123    } ss3;
1124 };
1125
1126
1127 struct brw_clipper_viewport
1128 {
1129    GLfloat xmin;
1130    GLfloat xmax;
1131    GLfloat ymin;
1132    GLfloat ymax;
1133 };
1134
1135 struct brw_cc_viewport
1136 {
1137    GLfloat min_depth;
1138    GLfloat max_depth;
1139 };
1140
1141 struct brw_sf_viewport
1142 {
1143    struct {
1144       GLfloat m00;
1145       GLfloat m11;
1146       GLfloat m22;
1147       GLfloat m30;
1148       GLfloat m31;
1149       GLfloat m32;
1150    } viewport;
1151
1152    /* scissor coordinates are inclusive */
1153    struct {
1154       GLshort xmin;
1155       GLshort ymin;
1156       GLshort xmax;
1157       GLshort ymax;
1158    } scissor;
1159 };
1160
1161 struct gen6_sf_viewport {
1162    GLfloat m00;
1163    GLfloat m11;
1164    GLfloat m22;
1165    GLfloat m30;
1166    GLfloat m31;
1167    GLfloat m32;
1168 };
1169
1170 /* Documented in the subsystem/shared-functions/sampler chapter...
1171  */
1172 struct brw_surface_state
1173 {
1174    struct {
1175       GLuint cube_pos_z:1;
1176       GLuint cube_neg_z:1;
1177       GLuint cube_pos_y:1;
1178       GLuint cube_neg_y:1;
1179       GLuint cube_pos_x:1;
1180       GLuint cube_neg_x:1;
1181       GLuint pad:2;
1182       /* Required on gen6 for surfaces accessed through render cache messages.
1183        */
1184       GLuint render_cache_read_write:1;
1185       /* Ironlake and newer: instead of replicating one of the texels */
1186       GLuint cube_corner_average:1;
1187       GLuint mipmap_layout_mode:1;
1188       GLuint vert_line_stride_ofs:1;
1189       GLuint vert_line_stride:1;
1190       GLuint color_blend:1;
1191       GLuint writedisable_blue:1;
1192       GLuint writedisable_green:1;
1193       GLuint writedisable_red:1;
1194       GLuint writedisable_alpha:1;
1195       GLuint surface_format:9;     /**< BRW_SURFACEFORMAT_x */
1196       GLuint data_return_format:1;
1197       GLuint pad0:1;
1198       GLuint surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
1199    } ss0;
1200
1201    struct {
1202       GLuint base_addr;
1203    } ss1;
1204
1205    struct {
1206       GLuint pad:2;
1207       GLuint mip_count:4;
1208       GLuint width:13;
1209       GLuint height:13;
1210    } ss2;
1211
1212    struct {
1213       GLuint tile_walk:1;
1214       GLuint tiled_surface:1;
1215       GLuint pad:1;
1216       GLuint pitch:18;
1217       GLuint depth:11;
1218    } ss3;
1219
1220    struct {
1221       GLuint multisample_position_palette_index:3;
1222       GLuint pad1:1;
1223       GLuint num_multisamples:3;
1224       GLuint pad0:1;
1225       GLuint render_target_view_extent:9;
1226       GLuint min_array_elt:11;
1227       GLuint min_lod:4;
1228    } ss4;
1229
1230    struct {
1231       GLuint pad1:16;
1232       GLuint cache_control:2;
1233       GLuint gfdt:1;
1234       GLuint encrypt:1;
1235       GLuint y_offset:4;
1236       GLuint pad0:1;
1237       GLuint x_offset:7;
1238    } ss5;   /* New in G4X */
1239
1240 };
1241
1242
1243
1244 struct brw_vertex_buffer_state
1245 {
1246    struct {
1247       GLuint pitch:11;
1248       GLuint pad:15;
1249       GLuint access_type:1;
1250       GLuint vb_index:5;
1251    } vb0;
1252
1253    GLuint start_addr;
1254    GLuint max_index;
1255 #if 1
1256    GLuint instance_data_step_rate; /* not included for sequential/random vertices? */
1257 #endif
1258 };
1259
1260 #define BRW_VBP_MAX 17
1261
1262 struct brw_vb_array_state {
1263    struct header header;
1264    struct brw_vertex_buffer_state vb[BRW_VBP_MAX];
1265 };
1266
1267
1268 struct brw_vertex_element_state
1269 {
1270    struct
1271    {
1272       GLuint src_offset:11;
1273       GLuint pad:5;
1274       GLuint src_format:9;
1275       GLuint pad0:1;
1276       GLuint valid:1;
1277       GLuint vertex_buffer_index:5;
1278    } ve0;
1279
1280    struct
1281    {
1282       GLuint dst_offset:8;
1283       GLuint pad:8;
1284       GLuint vfcomponent3:4;
1285       GLuint vfcomponent2:4;
1286       GLuint vfcomponent1:4;
1287       GLuint vfcomponent0:4;
1288    } ve1;
1289 };
1290
1291 #define BRW_VEP_MAX 18
1292
1293 struct brw_vertex_element_packet {
1294    struct header header;
1295    struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */
1296 };
1297
1298
1299 struct brw_urb_immediate {
1300    GLuint opcode:4;
1301    GLuint offset:6;
1302    GLuint swizzle_control:2;
1303    GLuint pad:1;
1304    GLuint allocate:1;
1305    GLuint used:1;
1306    GLuint complete:1;
1307    GLuint response_length:4;
1308    GLuint msg_length:4;
1309    GLuint msg_target:4;
1310    GLuint pad1:3;
1311    GLuint end_of_thread:1;
1312 };
1313
1314 /* Instruction format for the execution units:
1315  */
1316
1317 struct brw_instruction
1318 {
1319    struct
1320    {
1321       GLuint opcode:7;
1322       GLuint pad:1;
1323       GLuint access_mode:1;
1324       GLuint mask_control:1;
1325       GLuint dependency_control:2;
1326       GLuint compression_control:2; /* gen6: quater control */
1327       GLuint thread_control:2;
1328       GLuint predicate_control:4;
1329       GLuint predicate_inverse:1;
1330       GLuint execution_size:3;
1331       GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */
1332       GLuint acc_wr_control:1;
1333       GLuint cmpt_control:1;
1334       GLuint debug_control:1;
1335       GLuint saturate:1;
1336    } header;
1337
1338    union {
1339       struct
1340       {
1341          GLuint dest_reg_file:2;
1342          GLuint dest_reg_type:3;
1343          GLuint src0_reg_file:2;
1344          GLuint src0_reg_type:3;
1345          GLuint src1_reg_file:2;
1346          GLuint src1_reg_type:3;
1347          GLuint pad:1;
1348          GLuint dest_subreg_nr:5;
1349          GLuint dest_reg_nr:8;
1350          GLuint dest_horiz_stride:2;
1351          GLuint dest_address_mode:1;
1352       } da1;
1353
1354       struct
1355       {
1356          GLuint dest_reg_file:2;
1357          GLuint dest_reg_type:3;
1358          GLuint src0_reg_file:2;
1359          GLuint src0_reg_type:3;
1360          GLuint src1_reg_file:2;        /* 0x00000c00 */
1361          GLuint src1_reg_type:3;        /* 0x00007000 */
1362          GLuint pad:1;
1363          GLint dest_indirect_offset:10; /* offset against the deref'd address reg */
1364          GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
1365          GLuint dest_horiz_stride:2;
1366          GLuint dest_address_mode:1;
1367       } ia1;
1368
1369       struct
1370       {
1371          GLuint dest_reg_file:2;
1372          GLuint dest_reg_type:3;
1373          GLuint src0_reg_file:2;
1374          GLuint src0_reg_type:3;
1375          GLuint src1_reg_file:2;
1376          GLuint src1_reg_type:3;
1377          GLuint pad:1;
1378          GLuint dest_writemask:4;
1379          GLuint dest_subreg_nr:1;
1380          GLuint dest_reg_nr:8;
1381          GLuint dest_horiz_stride:2;
1382          GLuint dest_address_mode:1;
1383       } da16;
1384
1385       struct
1386       {
1387          GLuint dest_reg_file:2;
1388          GLuint dest_reg_type:3;
1389          GLuint src0_reg_file:2;
1390          GLuint src0_reg_type:3;
1391          GLuint pad0:6;
1392          GLuint dest_writemask:4;
1393          GLint dest_indirect_offset:6;
1394          GLuint dest_subreg_nr:3;
1395          GLuint dest_horiz_stride:2;
1396          GLuint dest_address_mode:1;
1397       } ia16;
1398
1399       struct {
1400          GLuint dest_reg_file:2;
1401          GLuint dest_reg_type:3;
1402          GLuint src0_reg_file:2;
1403          GLuint src0_reg_type:3;
1404          GLuint src1_reg_file:2;
1405          GLuint src1_reg_type:3;
1406          GLuint pad:1;
1407
1408          GLint jump_count:16;
1409       } branch_gen6;
1410    } bits1;
1411
1412
1413    union {
1414       struct
1415       {
1416          GLuint src0_subreg_nr:5;
1417          GLuint src0_reg_nr:8;
1418          GLuint src0_abs:1;
1419          GLuint src0_negate:1;
1420          GLuint src0_address_mode:1;
1421          GLuint src0_horiz_stride:2;
1422          GLuint src0_width:3;
1423          GLuint src0_vert_stride:4;
1424          GLuint flag_reg_nr:1;
1425          GLuint pad:6;
1426       } da1;
1427
1428       struct
1429       {
1430          GLint src0_indirect_offset:10;
1431          GLuint src0_subreg_nr:3;
1432          GLuint src0_abs:1;
1433          GLuint src0_negate:1;
1434          GLuint src0_address_mode:1;
1435          GLuint src0_horiz_stride:2;
1436          GLuint src0_width:3;
1437          GLuint src0_vert_stride:4;
1438          GLuint flag_reg_nr:1;
1439          GLuint pad:6;
1440       } ia1;
1441
1442       struct
1443       {
1444          GLuint src0_swz_x:2;
1445          GLuint src0_swz_y:2;
1446          GLuint src0_subreg_nr:1;
1447          GLuint src0_reg_nr:8;
1448          GLuint src0_abs:1;
1449          GLuint src0_negate:1;
1450          GLuint src0_address_mode:1;
1451          GLuint src0_swz_z:2;
1452          GLuint src0_swz_w:2;
1453          GLuint pad0:1;
1454          GLuint src0_vert_stride:4;
1455          GLuint flag_reg_nr:1;
1456          GLuint pad1:6;
1457       } da16;
1458
1459       struct
1460       {
1461          GLuint src0_swz_x:2;
1462          GLuint src0_swz_y:2;
1463          GLint src0_indirect_offset:6;
1464          GLuint src0_subreg_nr:3;
1465          GLuint src0_abs:1;
1466          GLuint src0_negate:1;
1467          GLuint src0_address_mode:1;
1468          GLuint src0_swz_z:2;
1469          GLuint src0_swz_w:2;
1470          GLuint pad0:1;
1471          GLuint src0_vert_stride:4;
1472          GLuint flag_reg_nr:1;
1473          GLuint pad1:6;
1474       } ia16;
1475
1476        struct
1477        {
1478            GLuint pad:26;
1479            GLuint end_of_thread:1;
1480            GLuint pad1:1;
1481            GLuint sfid:4;
1482        } send_gen5;  /* for Ironlake only */
1483
1484    } bits2;
1485
1486    union
1487    {
1488       struct
1489       {
1490          GLuint src1_subreg_nr:5;
1491          GLuint src1_reg_nr:8;
1492          GLuint src1_abs:1;
1493          GLuint src1_negate:1;
1494          GLuint src1_address_mode:1;
1495          GLuint src1_horiz_stride:2;
1496          GLuint src1_width:3;
1497          GLuint src1_vert_stride:4;
1498          GLuint pad0:7;
1499       } da1;
1500
1501       struct
1502       {
1503          GLuint src1_swz_x:2;
1504          GLuint src1_swz_y:2;
1505          GLuint src1_subreg_nr:1;
1506          GLuint src1_reg_nr:8;
1507          GLuint src1_abs:1;
1508          GLuint src1_negate:1;
1509          GLuint src1_address_mode:1;
1510          GLuint src1_swz_z:2;
1511          GLuint src1_swz_w:2;
1512          GLuint pad1:1;
1513          GLuint src1_vert_stride:4;
1514          GLuint pad2:7;
1515       } da16;
1516
1517       struct
1518       {
1519          GLint  src1_indirect_offset:10;
1520          GLuint src1_subreg_nr:3;
1521          GLuint src1_abs:1;
1522          GLuint src1_negate:1;
1523          GLuint src1_address_mode:1;
1524          GLuint src1_horiz_stride:2;
1525          GLuint src1_width:3;
1526          GLuint src1_vert_stride:4;
1527          GLuint flag_reg_nr:1;
1528          GLuint pad1:6;
1529       } ia1;
1530
1531       struct
1532       {
1533          GLuint src1_swz_x:2;
1534          GLuint src1_swz_y:2;
1535          GLint  src1_indirect_offset:6;
1536          GLuint src1_subreg_nr:3;
1537          GLuint src1_abs:1;
1538          GLuint src1_negate:1;
1539          GLuint pad0:1;
1540          GLuint src1_swz_z:2;
1541          GLuint src1_swz_w:2;
1542          GLuint pad1:1;
1543          GLuint src1_vert_stride:4;
1544          GLuint flag_reg_nr:1;
1545          GLuint pad2:6;
1546       } ia16;
1547
1548
1549       struct
1550       {
1551          GLint  jump_count:16;  /* note: signed */
1552          GLuint  pop_count:4;
1553          GLuint  pad0:12;
1554       } if_else;
1555
1556       struct
1557       {
1558          /* Signed jump distance to the ip to jump to if all channels
1559           * are disabled after the break or continue.  It should point
1560           * to the end of the innermost control flow block, as that's
1561           * where some channel could get re-enabled.
1562           */
1563          int jip:16;
1564
1565          /* Signed jump distance to the location to resume execution
1566           * of this channel if it's enabled for the break or continue.
1567           */
1568          int uip:16;
1569       } break_cont;
1570
1571       struct {
1572          GLuint function:4;
1573          GLuint int_type:1;
1574          GLuint precision:1;
1575          GLuint saturate:1;
1576          GLuint data_type:1;
1577          GLuint pad0:8;
1578          GLuint response_length:4;
1579          GLuint msg_length:4;
1580          GLuint msg_target:4;
1581          GLuint pad1:3;
1582          GLuint end_of_thread:1;
1583       } math;
1584
1585       struct {
1586          GLuint function:4;
1587          GLuint int_type:1;
1588          GLuint precision:1;
1589          GLuint saturate:1;
1590          GLuint data_type:1;
1591          GLuint snapshot:1;
1592          GLuint pad0:10;
1593          GLuint header_present:1;
1594          GLuint response_length:5;
1595          GLuint msg_length:4;
1596          GLuint pad1:2;
1597          GLuint end_of_thread:1;
1598       } math_gen5;
1599
1600       struct {
1601          GLuint binding_table_index:8;
1602          GLuint sampler:4;
1603          GLuint return_format:2;
1604          GLuint msg_type:2;
1605          GLuint response_length:4;
1606          GLuint msg_length:4;
1607          GLuint msg_target:4;
1608          GLuint pad1:3;
1609          GLuint end_of_thread:1;
1610       } sampler;
1611
1612       struct {
1613          GLuint binding_table_index:8;
1614          GLuint sampler:4;
1615          GLuint msg_type:4;
1616          GLuint response_length:4;
1617          GLuint msg_length:4;
1618          GLuint msg_target:4;
1619          GLuint pad1:3;
1620          GLuint end_of_thread:1;
1621       } sampler_g4x;
1622
1623       struct {
1624          GLuint binding_table_index:8;
1625          GLuint sampler:4;
1626          GLuint msg_type:4;
1627          GLuint simd_mode:2;
1628          GLuint pad0:1;
1629          GLuint header_present:1;
1630          GLuint response_length:5;
1631          GLuint msg_length:4;
1632          GLuint pad1:2;
1633          GLuint end_of_thread:1;
1634       } sampler_gen5;
1635
1636       struct brw_urb_immediate urb;
1637
1638       struct {
1639          GLuint opcode:4;
1640          GLuint offset:6;
1641          GLuint swizzle_control:2;
1642          GLuint pad:1;
1643          GLuint allocate:1;
1644          GLuint used:1;
1645          GLuint complete:1;
1646          GLuint pad0:3;
1647          GLuint header_present:1;
1648          GLuint response_length:5;
1649          GLuint msg_length:4;
1650          GLuint pad1:2;
1651          GLuint end_of_thread:1;
1652       } urb_gen5;
1653
1654       struct {
1655          GLuint binding_table_index:8;
1656          GLuint msg_control:4;
1657          GLuint msg_type:2;
1658          GLuint target_cache:2;
1659          GLuint response_length:4;
1660          GLuint msg_length:4;
1661          GLuint msg_target:4;
1662          GLuint pad1:3;
1663          GLuint end_of_thread:1;
1664       } dp_read;
1665
1666       struct {
1667          GLuint binding_table_index:8;
1668          GLuint msg_control:3;
1669          GLuint msg_type:3;
1670          GLuint target_cache:2;
1671          GLuint pad0:3;
1672          GLuint header_present:1;
1673          GLuint response_length:5;
1674          GLuint msg_length:4;
1675          GLuint pad1:2;
1676          GLuint end_of_thread:1;
1677       } dp_read_gen5;
1678
1679       struct {
1680          GLuint binding_table_index:8;
1681          GLuint msg_control:3;
1682          GLuint pixel_scoreboard_clear:1;
1683          GLuint msg_type:3;
1684          GLuint send_commit_msg:1;
1685          GLuint response_length:4;
1686          GLuint msg_length:4;
1687          GLuint msg_target:4;
1688          GLuint pad1:3;
1689          GLuint end_of_thread:1;
1690       } dp_write;
1691
1692       struct {
1693          GLuint binding_table_index:8;
1694          GLuint msg_control:3;
1695          GLuint pixel_scoreboard_clear:1;
1696          GLuint msg_type:3;
1697          GLuint send_commit_msg:1;
1698          GLuint pad0:3;
1699          GLuint header_present:1;
1700          GLuint response_length:5;
1701          GLuint msg_length:4;
1702          GLuint pad1:2;
1703          GLuint end_of_thread:1;
1704       } dp_write_gen5;
1705
1706       /* Sandybridge DP for sample cache, constant cache, render cache */
1707       struct {
1708          GLuint binding_table_index:8;
1709          GLuint msg_control:5;
1710          GLuint msg_type:3;
1711          GLuint pad0:3;
1712          GLuint header_present:1;
1713          GLuint response_length:5;
1714          GLuint msg_length:4;
1715          GLuint pad1:2;
1716          GLuint end_of_thread:1;
1717       } dp_sampler_const_cache;
1718
1719       struct {
1720          GLuint binding_table_index:8;
1721          GLuint msg_control:3;
1722          GLuint slot_group_select:1;
1723          GLuint pixel_scoreboard_clear:1;
1724          GLuint msg_type:4;
1725          GLuint send_commit_msg:1;
1726          GLuint pad0:1;
1727          GLuint header_present:1;
1728          GLuint response_length:5;
1729          GLuint msg_length:4;
1730          GLuint pad1:2;
1731          GLuint end_of_thread:1;
1732       } dp_render_cache;
1733
1734       struct {
1735          GLuint function_control:16;
1736          GLuint response_length:4;
1737          GLuint msg_length:4;
1738          GLuint msg_target:4;
1739          GLuint pad1:3;
1740          GLuint end_of_thread:1;
1741       } generic;
1742
1743       /* Of this struct, only end_of_thread is not present for gen6. */
1744       struct {
1745          GLuint function_control:19;
1746          GLuint header_present:1;
1747          GLuint response_length:5;
1748          GLuint msg_length:4;
1749          GLuint pad1:2;
1750          GLuint end_of_thread:1;
1751       } generic_gen5;
1752
1753       GLint d;
1754       GLuint ud;
1755       float f;
1756    } bits3;
1757 };
1758
1759
1760 #endif