2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
37 /** Number of general purpose registers (VS, WM, etc) */
38 #define BRW_MAX_GRF 128
41 * First GRF used for the MRF hack.
43 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
44 * haven't converted our compiler to be aware of this, so it asks for MRFs and
45 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
46 * register allocators have to be careful of this to avoid corrupting the "MRF"s
47 * with actual GRF allocations.
49 #define GEN7_MRF_HACK_START 112.
51 /** Number of message register file registers */
52 #define BRW_MAX_MRF 16
54 /* These seem to be passed around as function args, so it works out
55 * better to keep them as #defines:
57 #define BRW_FLUSH_READ_CACHE 0x1
58 #define BRW_FLUSH_STATE_CACHE 0x2
59 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
60 #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8
94 /* State structs for the various fixed function units:
101 GLuint grf_reg_count
:3;
103 GLuint kernel_start_pointer
:26; /* Offset from GENERAL_STATE_BASE */
108 GLuint ext_halt_exception_enable
:1;
109 GLuint sw_exception_enable
:1;
110 GLuint mask_stack_exception_enable
:1;
111 GLuint timeout_exception_enable
:1;
112 GLuint illegal_op_exception_enable
:1;
114 GLuint depth_coef_urb_read_offset
:6; /* WM only */
116 GLuint floating_point_mode
:1;
117 GLuint thread_priority
:1;
118 GLuint binding_table_entry_count
:8;
120 GLuint single_program_flow
:1;
125 GLuint per_thread_scratch_space
:4;
127 GLuint scratch_space_base_pointer
:22;
133 GLuint dispatch_grf_start_reg
:4;
134 GLuint urb_entry_read_offset
:6;
136 GLuint urb_entry_read_length
:6;
138 GLuint const_urb_entry_read_offset
:6;
140 GLuint const_urb_entry_read_length
:6;
146 struct brw_clip_unit_state
148 struct thread0 thread0
;
152 GLuint sw_exception_enable
:1;
154 GLuint mask_stack_exception_enable
:1;
156 GLuint illegal_op_exception_enable
:1;
158 GLuint floating_point_mode
:1;
159 GLuint thread_priority
:1;
160 GLuint binding_table_entry_count
:8;
162 GLuint single_program_flow
:1;
165 struct thread2 thread2
;
166 struct thread3 thread3
;
171 GLuint gs_output_stats
:1; /* not always */
172 GLuint stats_enable
:1;
173 GLuint nr_urb_entries
:7;
175 GLuint urb_entry_allocation_size
:5;
177 GLuint max_threads
:5; /* may be less */
185 GLuint userclip_enable_flags
:8;
186 GLuint userclip_must_clip
:1;
187 GLuint negative_w_clip_test
:1;
188 GLuint guard_band_enable
:1;
189 GLuint viewport_z_clip_enable
:1;
190 GLuint viewport_xy_clip_enable
:1;
191 GLuint vertex_position_space
:1;
199 GLuint clipper_viewport_state_ptr
:27;
203 GLfloat viewport_xmin
;
204 GLfloat viewport_xmax
;
205 GLfloat viewport_ymin
;
206 GLfloat viewport_ymax
;
209 struct gen6_blend_state
212 GLuint dest_blend_factor
:5;
213 GLuint source_blend_factor
:5;
217 GLuint ia_dest_blend_factor
:5;
218 GLuint ia_source_blend_factor
:5;
220 GLuint ia_blend_func
:3;
222 GLuint ia_blend_enable
:1;
223 GLuint blend_enable
:1;
227 GLuint post_blend_clamp_enable
:1;
228 GLuint pre_blend_clamp_enable
:1;
229 GLuint clamp_range
:2;
231 GLuint x_dither_offset
:2;
232 GLuint y_dither_offset
:2;
233 GLuint dither_enable
:1;
234 GLuint alpha_test_func
:3;
235 GLuint alpha_test_enable
:1;
237 GLuint logic_op_func
:4;
238 GLuint logic_op_enable
:1;
240 GLuint write_disable_b
:1;
241 GLuint write_disable_g
:1;
242 GLuint write_disable_r
:1;
243 GLuint write_disable_a
:1;
245 GLuint alpha_to_coverage_dither
:1;
246 GLuint alpha_to_one
:1;
247 GLuint alpha_to_coverage
:1;
251 struct gen6_color_calc_state
254 GLuint alpha_test_format
:1;
256 GLuint round_disable
:1;
257 GLuint bf_stencil_ref
:8;
258 GLuint stencil_ref
:8;
275 struct gen6_depth_stencil_state
279 GLuint bf_stencil_pass_depth_pass_op
:3;
280 GLuint bf_stencil_pass_depth_fail_op
:3;
281 GLuint bf_stencil_fail_op
:3;
282 GLuint bf_stencil_func
:3;
283 GLuint bf_stencil_enable
:1;
285 GLuint stencil_write_enable
:1;
286 GLuint stencil_pass_depth_pass_op
:3;
287 GLuint stencil_pass_depth_fail_op
:3;
288 GLuint stencil_fail_op
:3;
289 GLuint stencil_func
:3;
290 GLuint stencil_enable
:1;
294 GLuint bf_stencil_write_mask
:8;
295 GLuint bf_stencil_test_mask
:8;
296 GLuint stencil_write_mask
:8;
297 GLuint stencil_test_mask
:8;
302 GLuint depth_write_enable
:1;
303 GLuint depth_test_func
:3;
305 GLuint depth_test_enable
:1;
309 struct brw_cc_unit_state
314 GLuint bf_stencil_pass_depth_pass_op
:3;
315 GLuint bf_stencil_pass_depth_fail_op
:3;
316 GLuint bf_stencil_fail_op
:3;
317 GLuint bf_stencil_func
:3;
318 GLuint bf_stencil_enable
:1;
320 GLuint stencil_write_enable
:1;
321 GLuint stencil_pass_depth_pass_op
:3;
322 GLuint stencil_pass_depth_fail_op
:3;
323 GLuint stencil_fail_op
:3;
324 GLuint stencil_func
:3;
325 GLuint stencil_enable
:1;
331 GLuint bf_stencil_ref
:8;
332 GLuint stencil_write_mask
:8;
333 GLuint stencil_test_mask
:8;
334 GLuint stencil_ref
:8;
340 GLuint logicop_enable
:1;
342 GLuint depth_write_enable
:1;
343 GLuint depth_test_function
:3;
345 GLuint bf_stencil_write_mask
:8;
346 GLuint bf_stencil_test_mask
:8;
353 GLuint alpha_test_func
:3;
355 GLuint blend_enable
:1;
356 GLuint ia_blend_enable
:1;
358 GLuint alpha_test_format
:1;
365 GLuint cc_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
371 GLuint ia_dest_blend_factor
:5;
372 GLuint ia_src_blend_factor
:5;
373 GLuint ia_blend_function
:3;
374 GLuint statistics_enable
:1;
375 GLuint logicop_func
:4;
377 GLuint dither_enable
:1;
382 GLuint clamp_post_alpha_blend
:1;
383 GLuint clamp_pre_alpha_blend
:1;
384 GLuint clamp_range
:2;
386 GLuint y_dither_offset
:2;
387 GLuint x_dither_offset
:2;
388 GLuint dest_blend_factor
:5;
389 GLuint src_blend_factor
:5;
390 GLuint blend_function
:3;
401 struct brw_sf_unit_state
403 struct thread0 thread0
;
404 struct thread1 thread1
;
405 struct thread2 thread2
;
406 struct thread3 thread3
;
411 GLuint stats_enable
:1;
412 GLuint nr_urb_entries
:7;
414 GLuint urb_entry_allocation_size
:5;
416 GLuint max_threads
:6;
422 GLuint front_winding
:1;
423 GLuint viewport_transform
:1;
425 GLuint sf_viewport_state_offset
:27; /* Offset from GENERAL_STATE_BASE */
431 GLuint dest_org_vbias
:4;
432 GLuint dest_org_hbias
:4;
434 GLuint disable_2x2_trifilter
:1;
435 GLuint disable_zero_pix_trifilter
:1;
436 GLuint point_rast_rule
:2;
437 GLuint line_endcap_aa_region_width
:2;
439 GLuint fast_scissor_disable
:1;
446 GLuint point_size
:11;
447 GLuint use_point_size_state
:1;
448 GLuint subpixel_precision
:1;
449 GLuint sprite_point
:1;
451 GLuint aa_line_distance_mode
:1;
453 GLuint linestrip_pv
:2;
454 GLuint tristrip_pv
:2;
455 GLuint line_last_pixel_enable
:1;
460 struct gen6_scissor_rect
468 struct brw_gs_unit_state
470 struct thread0 thread0
;
471 struct thread1 thread1
;
472 struct thread2 thread2
;
473 struct thread3 thread3
;
478 GLuint rendering_enable
:1; /* for Ironlake */
480 GLuint stats_enable
:1;
481 GLuint nr_urb_entries
:7;
483 GLuint urb_entry_allocation_size
:5;
485 GLuint max_threads
:5;
491 GLuint sampler_count
:3;
493 GLuint sampler_state_pointer
:27;
499 GLuint max_vp_index
:4;
501 GLuint svbi_post_inc_value
:10;
503 GLuint svbi_post_inc_enable
:1;
504 GLuint svbi_payload
:1;
505 GLuint discard_adjaceny
:1;
506 GLuint reorder_enable
:1;
512 struct brw_vs_unit_state
514 struct thread0 thread0
;
515 struct thread1 thread1
;
516 struct thread2 thread2
;
517 struct thread3 thread3
;
522 GLuint stats_enable
:1;
523 GLuint nr_urb_entries
:7;
525 GLuint urb_entry_allocation_size
:5;
527 GLuint max_threads
:6;
533 GLuint sampler_count
:3;
535 GLuint sampler_state_pointer
:27;
541 GLuint vert_cache_disable
:1;
547 struct brw_wm_unit_state
549 struct thread0 thread0
;
550 struct thread1 thread1
;
551 struct thread2 thread2
;
552 struct thread3 thread3
;
555 GLuint stats_enable
:1;
556 GLuint depth_buffer_clear
:1;
557 GLuint sampler_count
:3;
558 GLuint sampler_state_pointer
:27;
563 GLuint enable_8_pix
:1;
564 GLuint enable_16_pix
:1;
565 GLuint enable_32_pix
:1;
566 GLuint enable_con_32_pix
:1;
567 GLuint enable_con_64_pix
:1;
570 /* These next four bits are for Ironlake+ */
571 GLuint fast_span_coverage_enable
:1;
572 GLuint depth_buffer_clear
:1;
573 GLuint depth_buffer_resolve_enable
:1;
574 GLuint hierarchical_depth_buffer_resolve_enable
:1;
576 GLuint legacy_global_depth_bias
:1;
577 GLuint line_stipple
:1;
578 GLuint depth_offset
:1;
579 GLuint polygon_stipple
:1;
580 GLuint line_aa_region_width
:2;
581 GLuint line_endcap_aa_region_width
:2;
582 GLuint early_depth_test
:1;
583 GLuint thread_dispatch_enable
:1;
584 GLuint program_uses_depth
:1;
585 GLuint program_computes_depth
:1;
586 GLuint program_uses_killpixel
:1;
587 GLuint legacy_line_rast
: 1;
588 GLuint transposed_urb_read_enable
:1;
589 GLuint max_threads
:7;
592 GLfloat global_depth_offset_constant
;
593 GLfloat global_depth_offset_scale
;
595 /* for Ironlake only */
598 GLuint grf_reg_count_1
:3;
600 GLuint kernel_start_pointer_1
:26;
605 GLuint grf_reg_count_2
:3;
607 GLuint kernel_start_pointer_2
:26;
612 GLuint grf_reg_count_3
:3;
614 GLuint kernel_start_pointer_3
:26;
618 struct brw_sampler_default_color
{
622 struct gen5_sampler_default_color
{
631 struct brw_sampler_state
636 GLuint shadow_function
:3;
642 GLuint min_mag_neq
:1;
643 GLuint lod_preclamp
:1;
644 GLuint default_color_mode
:1;
651 GLuint r_wrap_mode
:3;
652 GLuint t_wrap_mode
:3;
653 GLuint s_wrap_mode
:3;
654 GLuint cube_control_mode
:1;
664 GLuint default_color_pointer
:27;
669 GLuint non_normalized_coord
:1;
671 GLuint address_round
:6;
673 GLuint chroma_key_mode
:1;
674 GLuint chroma_key_index
:2;
675 GLuint chroma_key_enable
:1;
676 GLuint monochrome_filter_width
:3;
677 GLuint monochrome_filter_height
:3;
681 struct gen7_sampler_state
685 GLuint aniso_algorithm
:1;
692 GLuint lod_preclamp
:1;
693 GLuint default_color_mode
:1;
700 GLuint cube_control_mode
:1;
701 GLuint shadow_function
:3;
710 GLuint default_color_pointer
:27;
715 GLuint r_wrap_mode
:3;
716 GLuint t_wrap_mode
:3;
717 GLuint s_wrap_mode
:3;
719 GLuint non_normalized_coord
:1;
720 GLuint trilinear_quality
:2;
721 GLuint address_round
:6;
723 GLuint chroma_key_mode
:1;
724 GLuint chroma_key_index
:2;
725 GLuint chroma_key_enable
:1;
730 struct brw_clipper_viewport
738 struct brw_cc_viewport
744 struct brw_sf_viewport
755 /* scissor coordinates are inclusive */
764 struct gen6_sf_viewport
{
773 struct gen7_sf_clip_viewport
{
795 /* volume 5c Shared Functions - 1.13.4.1.2 */
796 struct gen7_surface_state
806 GLuint render_cache_read_write
:1;
808 GLuint surface_array_spacing
:1;
809 GLuint vert_line_stride_ofs
:1;
810 GLuint vert_line_stride
:1;
812 GLuint tiled_surface
:1;
813 GLuint horizontal_alignment
:1;
814 GLuint vertical_alignment
:2;
815 GLuint surface_format
:9; /**< BRW_SURFACEFORMAT_x */
818 GLuint surface_type
:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */
839 GLuint multisample_position_palette_index
:3;
840 GLuint num_multisamples
:3;
841 GLuint multisampled_surface_storage_format
:1;
842 GLuint render_target_view_extent
:11;
843 GLuint min_array_elt
:11;
860 GLuint y_offset_for_uv_plane
:14;
862 GLuint x_offset_for_uv_plane
:14;
864 } planar
; /** Interpretation when Surface Format == PLANAR */
867 GLuint append_counter_enable
:1;
869 GLuint append_counter_address
:26;
870 } mcs_disabled
; /** Interpretation when mcs_enable == 0 */
874 GLuint mcs_surface_pitch
:9;
875 GLuint mcs_base_address
:20;
876 } mcs_enabled
; /** Interpretation when mcs_enable == 1 */
880 GLuint resource_min_lod
:12;
882 /* Only on Haswell */
884 GLuint shader_channel_select_a
:3;
885 GLuint shader_channel_select_b
:3;
886 GLuint shader_channel_select_g
:3;
887 GLuint shader_channel_select_r
:3;
889 GLuint alpha_clear_color
:1;
890 GLuint blue_clear_color
:1;
891 GLuint green_clear_color
:1;
892 GLuint red_clear_color
:1;
897 struct brw_vertex_element_state
901 GLuint src_offset
:11;
906 GLuint vertex_buffer_index
:5;
913 GLuint vfcomponent3
:4;
914 GLuint vfcomponent2
:4;
915 GLuint vfcomponent1
:4;
916 GLuint vfcomponent0
:4;
920 struct brw_urb_immediate
{
923 GLuint swizzle_control
:2;
928 GLuint response_length
:4;
932 GLuint end_of_thread
:1;
935 /* Instruction format for the execution units:
938 struct brw_instruction
944 GLuint access_mode
:1;
945 GLuint mask_control
:1;
946 GLuint dependency_control
:2;
947 GLuint compression_control
:2; /* gen6: quater control */
948 GLuint thread_control
:2;
949 GLuint predicate_control
:4;
950 GLuint predicate_inverse
:1;
951 GLuint execution_size
:3;
953 * Conditional Modifier for most instructions. On Gen6+, this is also
954 * used for the SEND instruction's Message Target/SFID.
956 GLuint destreg__conditionalmod
:4;
957 GLuint acc_wr_control
:1;
958 GLuint cmpt_control
:1;
959 GLuint debug_control
:1;
966 GLuint dest_reg_file
:2;
967 GLuint dest_reg_type
:3;
968 GLuint src0_reg_file
:2;
969 GLuint src0_reg_type
:3;
970 GLuint src1_reg_file
:2;
971 GLuint src1_reg_type
:3;
973 GLuint dest_subreg_nr
:5;
974 GLuint dest_reg_nr
:8;
975 GLuint dest_horiz_stride
:2;
976 GLuint dest_address_mode
:1;
981 GLuint dest_reg_file
:2;
982 GLuint dest_reg_type
:3;
983 GLuint src0_reg_file
:2;
984 GLuint src0_reg_type
:3;
985 GLuint src1_reg_file
:2; /* 0x00000c00 */
986 GLuint src1_reg_type
:3; /* 0x00007000 */
988 GLint dest_indirect_offset
:10; /* offset against the deref'd address reg */
989 GLuint dest_subreg_nr
:3; /* subnr for the address reg a0.x */
990 GLuint dest_horiz_stride
:2;
991 GLuint dest_address_mode
:1;
996 GLuint dest_reg_file
:2;
997 GLuint dest_reg_type
:3;
998 GLuint src0_reg_file
:2;
999 GLuint src0_reg_type
:3;
1000 GLuint src1_reg_file
:2;
1001 GLuint src1_reg_type
:3;
1003 GLuint dest_writemask
:4;
1004 GLuint dest_subreg_nr
:1;
1005 GLuint dest_reg_nr
:8;
1006 GLuint dest_horiz_stride
:2;
1007 GLuint dest_address_mode
:1;
1012 GLuint dest_reg_file
:2;
1013 GLuint dest_reg_type
:3;
1014 GLuint src0_reg_file
:2;
1015 GLuint src0_reg_type
:3;
1017 GLuint dest_writemask
:4;
1018 GLint dest_indirect_offset
:6;
1019 GLuint dest_subreg_nr
:3;
1020 GLuint dest_horiz_stride
:2;
1021 GLuint dest_address_mode
:1;
1025 GLuint dest_reg_file
:2;
1026 GLuint dest_reg_type
:3;
1027 GLuint src0_reg_file
:2;
1028 GLuint src0_reg_type
:3;
1029 GLuint src1_reg_file
:2;
1030 GLuint src1_reg_type
:3;
1033 GLint jump_count
:16;
1037 GLuint dest_reg_file
:1;
1038 GLuint flag_subreg_num
:1;
1041 GLuint src0_negate
:1;
1043 GLuint src1_negate
:1;
1045 GLuint src2_negate
:1;
1047 GLuint dest_writemask
:4;
1048 GLuint dest_subreg_nr
:3;
1049 GLuint dest_reg_nr
:8;
1059 GLuint src0_subreg_nr
:5;
1060 GLuint src0_reg_nr
:8;
1062 GLuint src0_negate
:1;
1063 GLuint src0_address_mode
:1;
1064 GLuint src0_horiz_stride
:2;
1065 GLuint src0_width
:3;
1066 GLuint src0_vert_stride
:4;
1067 GLuint flag_subreg_nr
:1;
1068 GLuint flag_reg_nr
:1;
1074 GLint src0_indirect_offset
:10;
1075 GLuint src0_subreg_nr
:3;
1077 GLuint src0_negate
:1;
1078 GLuint src0_address_mode
:1;
1079 GLuint src0_horiz_stride
:2;
1080 GLuint src0_width
:3;
1081 GLuint src0_vert_stride
:4;
1082 GLuint flag_subreg_nr
:1;
1083 GLuint flag_reg_nr
:1;
1089 GLuint src0_swz_x
:2;
1090 GLuint src0_swz_y
:2;
1091 GLuint src0_subreg_nr
:1;
1092 GLuint src0_reg_nr
:8;
1094 GLuint src0_negate
:1;
1095 GLuint src0_address_mode
:1;
1096 GLuint src0_swz_z
:2;
1097 GLuint src0_swz_w
:2;
1099 GLuint src0_vert_stride
:4;
1100 GLuint flag_subreg_nr
:1;
1101 GLuint flag_reg_nr
:1;
1107 GLuint src0_swz_x
:2;
1108 GLuint src0_swz_y
:2;
1109 GLint src0_indirect_offset
:6;
1110 GLuint src0_subreg_nr
:3;
1112 GLuint src0_negate
:1;
1113 GLuint src0_address_mode
:1;
1114 GLuint src0_swz_z
:2;
1115 GLuint src0_swz_w
:2;
1117 GLuint src0_vert_stride
:4;
1118 GLuint flag_subreg_nr
:1;
1119 GLuint flag_reg_nr
:1;
1123 /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction.
1125 * Does not apply to Gen6+. The SFID/message target moved to bits
1126 * 27:24 of the header (destreg__conditionalmod); EOT is in bits3.
1131 GLuint end_of_thread
:1;
1134 } send_gen5
; /* for Ironlake only */
1137 GLuint src0_rep_ctrl
:1;
1138 GLuint src0_swizzle
:8;
1139 GLuint src0_subreg_nr
:3;
1140 GLuint src0_reg_nr
:8;
1142 GLuint src1_rep_ctrl
:1;
1143 GLuint src1_swizzle
:8;
1144 GLuint src1_subreg_nr_low
:2;
1154 GLuint src1_subreg_nr
:5;
1155 GLuint src1_reg_nr
:8;
1157 GLuint src1_negate
:1;
1158 GLuint src1_address_mode
:1;
1159 GLuint src1_horiz_stride
:2;
1160 GLuint src1_width
:3;
1161 GLuint src1_vert_stride
:4;
1167 GLuint src1_swz_x
:2;
1168 GLuint src1_swz_y
:2;
1169 GLuint src1_subreg_nr
:1;
1170 GLuint src1_reg_nr
:8;
1172 GLuint src1_negate
:1;
1173 GLuint src1_address_mode
:1;
1174 GLuint src1_swz_z
:2;
1175 GLuint src1_swz_w
:2;
1177 GLuint src1_vert_stride
:4;
1183 GLint src1_indirect_offset
:10;
1184 GLuint src1_subreg_nr
:3;
1186 GLuint src1_negate
:1;
1187 GLuint src1_address_mode
:1;
1188 GLuint src1_horiz_stride
:2;
1189 GLuint src1_width
:3;
1190 GLuint src1_vert_stride
:4;
1196 GLuint src1_swz_x
:2;
1197 GLuint src1_swz_y
:2;
1198 GLint src1_indirect_offset
:6;
1199 GLuint src1_subreg_nr
:3;
1201 GLuint src1_negate
:1;
1203 GLuint src1_swz_z
:2;
1204 GLuint src1_swz_w
:2;
1206 GLuint src1_vert_stride
:4;
1213 GLint jump_count
:16; /* note: signed */
1218 /* This is also used for gen7 IF/ELSE instructions */
1221 /* Signed jump distance to the ip to jump to if all channels
1222 * are disabled after the break or continue. It should point
1223 * to the end of the innermost control flow block, as that's
1224 * where some channel could get re-enabled.
1228 /* Signed jump distance to the location to resume execution
1229 * of this channel if it's enabled for the break or continue.
1235 * \defgroup SEND instructions / Message Descriptors
1241 * Generic Message Descriptor for Gen4 SEND instructions. The structs
1242 * below expand function_control to something specific for their
1243 * message. Due to struct packing issues, they duplicate these bits.
1245 * See the G45 PRM, Volume 4, Table 14-15.
1248 GLuint function_control
:16;
1249 GLuint response_length
:4;
1250 GLuint msg_length
:4;
1251 GLuint msg_target
:4;
1253 GLuint end_of_thread
:1;
1257 * Generic Message Descriptor for Gen5-7 SEND instructions.
1259 * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15. (Sadly, most
1260 * of the information on the SEND instruction is missing from the public
1263 * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies.
1264 * According to the SEND instruction description:
1265 * "The MSb of the message description, the EOT field, always comes from
1266 * bit 127 of the instruction word"...which is bit 31 of this field.
1269 GLuint function_control
:19;
1270 GLuint header_present
:1;
1271 GLuint response_length
:5;
1272 GLuint msg_length
:4;
1274 GLuint end_of_thread
:1;
1277 /** G45 PRM, Volume 4, Section 6.1.1.1 */
1285 GLuint response_length
:4;
1286 GLuint msg_length
:4;
1287 GLuint msg_target
:4;
1289 GLuint end_of_thread
:1;
1292 /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */
1301 GLuint header_present
:1;
1302 GLuint response_length
:5;
1303 GLuint msg_length
:4;
1305 GLuint end_of_thread
:1;
1308 /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */
1310 GLuint binding_table_index
:8;
1312 GLuint return_format
:2;
1314 GLuint response_length
:4;
1315 GLuint msg_length
:4;
1316 GLuint msg_target
:4;
1318 GLuint end_of_thread
:1;
1321 /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */
1323 GLuint binding_table_index
:8;
1326 GLuint response_length
:4;
1327 GLuint msg_length
:4;
1328 GLuint msg_target
:4;
1330 GLuint end_of_thread
:1;
1333 /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */
1335 GLuint binding_table_index
:8;
1340 GLuint header_present
:1;
1341 GLuint response_length
:5;
1342 GLuint msg_length
:4;
1344 GLuint end_of_thread
:1;
1348 GLuint binding_table_index
:8;
1352 GLuint header_present
:1;
1353 GLuint response_length
:5;
1354 GLuint msg_length
:4;
1356 GLuint end_of_thread
:1;
1359 struct brw_urb_immediate urb
;
1364 GLuint swizzle_control
:2;
1370 GLuint header_present
:1;
1371 GLuint response_length
:5;
1372 GLuint msg_length
:4;
1374 GLuint end_of_thread
:1;
1380 GLuint swizzle_control
:1;
1382 GLuint per_slot_offset
:1;
1384 GLuint header_present
:1;
1385 GLuint response_length
:5;
1386 GLuint msg_length
:4;
1388 GLuint end_of_thread
:1;
1391 /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */
1393 GLuint binding_table_index
:8;
1394 GLuint msg_control
:4;
1396 GLuint target_cache
:2;
1397 GLuint response_length
:4;
1398 GLuint msg_length
:4;
1399 GLuint msg_target
:4;
1401 GLuint end_of_thread
:1;
1404 /** G45 PRM, Volume 4, Section 5.10.1.1.2 */
1406 GLuint binding_table_index
:8;
1407 GLuint msg_control
:3;
1409 GLuint target_cache
:2;
1410 GLuint response_length
:4;
1411 GLuint msg_length
:4;
1412 GLuint msg_target
:4;
1414 GLuint end_of_thread
:1;
1417 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1419 GLuint binding_table_index
:8;
1420 GLuint msg_control
:3;
1422 GLuint target_cache
:2;
1424 GLuint header_present
:1;
1425 GLuint response_length
:5;
1426 GLuint msg_length
:4;
1428 GLuint end_of_thread
:1;
1431 /** G45 PRM, Volume 4, Section 5.10.1.1.2. For both Gen4 and G45. */
1433 GLuint binding_table_index
:8;
1434 GLuint msg_control
:3;
1435 GLuint last_render_target
:1;
1437 GLuint send_commit_msg
:1;
1438 GLuint response_length
:4;
1439 GLuint msg_length
:4;
1440 GLuint msg_target
:4;
1442 GLuint end_of_thread
:1;
1445 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */
1447 GLuint binding_table_index
:8;
1448 GLuint msg_control
:3;
1449 GLuint last_render_target
:1;
1451 GLuint send_commit_msg
:1;
1453 GLuint header_present
:1;
1454 GLuint response_length
:5;
1455 GLuint msg_length
:4;
1457 GLuint end_of_thread
:1;
1461 * Message for the Sandybridge Sampler Cache or Constant Cache Data Port.
1463 * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1.
1466 GLuint binding_table_index
:8;
1467 GLuint msg_control
:5;
1470 GLuint header_present
:1;
1471 GLuint response_length
:5;
1472 GLuint msg_length
:4;
1474 GLuint end_of_thread
:1;
1475 } gen6_dp_sampler_const_cache
;
1478 * Message for the Sandybridge Render Cache Data Port.
1480 * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1,
1481 * Section 3.9.2.1.1: Message Descriptor.
1483 * "Slot Group Select" and "Last Render Target" are part of the
1484 * 5-bit message control for Render Target Write messages. See
1485 * Section 3.9.9.2.1 of the same volume.
1488 GLuint binding_table_index
:8;
1489 GLuint msg_control
:3;
1490 GLuint slot_group_select
:1;
1491 GLuint last_render_target
:1;
1493 GLuint send_commit_msg
:1;
1495 GLuint header_present
:1;
1496 GLuint response_length
:5;
1497 GLuint msg_length
:4;
1499 GLuint end_of_thread
:1;
1503 * Message for any of the Gen7 Data Port caches.
1505 * Most fields are defined in BSpec volume 5c.2 Data Port / Messages /
1506 * Data Port Messages / Message Descriptor. Once again, "Slot Group
1507 * Select" and "Last Render Target" are part of the 6-bit message
1508 * control for Render Target Writes.
1511 GLuint binding_table_index
:8;
1512 GLuint msg_control
:3;
1513 GLuint slot_group_select
:1;
1514 GLuint last_render_target
:1;
1515 GLuint msg_control_pad
:1;
1518 GLuint header_present
:1;
1519 GLuint response_length
:5;
1520 GLuint msg_length
:4;
1522 GLuint end_of_thread
:1;
1527 GLuint src1_subreg_nr_high
:1;
1528 GLuint src1_reg_nr
:8;
1530 GLuint src2_rep_ctrl
:1;
1531 GLuint src2_swizzle
:8;
1532 GLuint src2_subreg_nr
:3;
1533 GLuint src2_reg_nr
:8;
1543 struct brw_compact_instruction
{
1545 unsigned opcode
:7; /* 0- 6 */
1546 unsigned debug_control
:1; /* 7- 7 */
1547 unsigned control_index
:5; /* 8-12 */
1548 unsigned data_type_index
:5; /* 13-17 */
1549 unsigned sub_reg_index
:5; /* 18-22 */
1550 unsigned acc_wr_control
:1; /* 23-23 */
1551 unsigned conditionalmod
:4; /* 24-27 */
1552 unsigned flag_subreg_nr
:1; /* 28-28 */
1553 unsigned cmpt_ctrl
:1; /* 29-29 */
1554 unsigned src0_index
:2; /* 30-31 */
1558 unsigned src0_index
:3; /* 32-24 */
1559 unsigned src1_index
:5; /* 35-39 */
1560 unsigned dst_reg_nr
:8; /* 40-47 */
1561 unsigned src0_reg_nr
:8; /* 48-55 */
1562 unsigned src1_reg_nr
:8; /* 56-63 */