src/mesa/drivers/dri/i965/brw_structs.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #ifndef BRW_STRUCTS_H
  34 #define BRW_STRUCTS_H
  35
  36 struct brw_urb_fence
  37 {
  38    struct
  39    {
  40       unsigned length:8;
  41       unsigned vs_realloc:1;
  42       unsigned gs_realloc:1;
  43       unsigned clp_realloc:1;
  44       unsigned sf_realloc:1;
  45       unsigned vfe_realloc:1;
  46       unsigned cs_realloc:1;
  47       unsigned pad:2;
  48       unsigned opcode:16;
  49    } header;
  50
  51    struct
  52    {
  53       unsigned vs_fence:10;
  54       unsigned gs_fence:10;
  55       unsigned clp_fence:10;
  56       unsigned pad:2;
  57    } bits0;
  58
  59    struct
  60    {
  61       unsigned sf_fence:10;
  62       unsigned vf_fence:10;
  63       unsigned cs_fence:11;
  64       unsigned pad:1;
  65    } bits1;
  66 };
  67
  68 /* State structs for the various fixed function units:
  69  */
  70
  71
  72 struct thread0
  73 {
  74    unsigned pad0:1;
  75    unsigned grf_reg_count:3;
  76    unsigned pad1:2;
  77    unsigned kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
  78 };
  79
  80 struct thread1
  81 {
  82    unsigned ext_halt_exception_enable:1;
  83    unsigned sw_exception_enable:1;
  84    unsigned mask_stack_exception_enable:1;
  85    unsigned timeout_exception_enable:1;
  86    unsigned illegal_op_exception_enable:1;
  87    unsigned pad0:3;
  88    unsigned depth_coef_urb_read_offset:6;       /* WM only */
  89    unsigned pad1:2;
  90    unsigned floating_point_mode:1;
  91    unsigned thread_priority:1;
  92    unsigned binding_table_entry_count:8;
  93    unsigned pad3:5;
  94    unsigned single_program_flow:1;
  95 };
  96
  97 struct thread2
  98 {
  99    unsigned per_thread_scratch_space:4;
 100    unsigned pad0:6;
 101    unsigned scratch_space_base_pointer:22;
 102 };
 103
 104
 105 struct thread3
 106 {
 107    unsigned dispatch_grf_start_reg:4;
 108    unsigned urb_entry_read_offset:6;
 109    unsigned pad0:1;
 110    unsigned urb_entry_read_length:6;
 111    unsigned pad1:1;
 112    unsigned const_urb_entry_read_offset:6;
 113    unsigned pad2:1;
 114    unsigned const_urb_entry_read_length:6;
 115    unsigned pad3:1;
 116 };
 117
 118 struct brw_wm_unit_state
 119 {
 120    struct thread0 thread0;
 121    struct thread1 thread1;
 122    struct thread2 thread2;
 123    struct thread3 thread3;
 124
 125    struct {
 126       unsigned stats_enable:1;
 127       unsigned depth_buffer_clear:1;
 128       unsigned sampler_count:3;
 129       unsigned sampler_state_pointer:27;
 130    } wm4;
 131
 132    struct
 133    {
 134       unsigned enable_8_pix:1;
 135       unsigned enable_16_pix:1;
 136       unsigned enable_32_pix:1;
 137       unsigned enable_con_32_pix:1;
 138       unsigned enable_con_64_pix:1;
 139       unsigned pad0:1;
 140
 141       /* These next four bits are for Ironlake+ */
 142       unsigned fast_span_coverage_enable:1;
 143       unsigned depth_buffer_clear:1;
 144       unsigned depth_buffer_resolve_enable:1;
 145       unsigned hierarchical_depth_buffer_resolve_enable:1;
 146
 147       unsigned legacy_global_depth_bias:1;
 148       unsigned line_stipple:1;
 149       unsigned depth_offset:1;
 150       unsigned polygon_stipple:1;
 151       unsigned line_aa_region_width:2;
 152       unsigned line_endcap_aa_region_width:2;
 153       unsigned early_depth_test:1;
 154       unsigned thread_dispatch_enable:1;
 155       unsigned program_uses_depth:1;
 156       unsigned program_computes_depth:1;
 157       unsigned program_uses_killpixel:1;
 158       unsigned legacy_line_rast: 1;
 159       unsigned transposed_urb_read_enable:1;
 160       unsigned max_threads:7;
 161    } wm5;
 162
 163    float global_depth_offset_constant;
 164    float global_depth_offset_scale;
 165
 166    /* for Ironlake only */
 167    struct {
 168       unsigned pad0:1;
 169       unsigned grf_reg_count_1:3;
 170       unsigned pad1:2;
 171       unsigned kernel_start_pointer_1:26;
 172    } wm8;
 173
 174    struct {
 175       unsigned pad0:1;
 176       unsigned grf_reg_count_2:3;
 177       unsigned pad1:2;
 178       unsigned kernel_start_pointer_2:26;
 179    } wm9;
 180
 181    struct {
 182       unsigned pad0:1;
 183       unsigned grf_reg_count_3:3;
 184       unsigned pad1:2;
 185       unsigned kernel_start_pointer_3:26;
 186    } wm10;
 187 };
 188
 189 struct gen5_sampler_default_color {
 190    uint8_t ub[4];
 191    float f[4];
 192    uint16_t hf[4];
 193    uint16_t us[4];
 194    int16_t s[4];
 195    uint8_t b[4];
 196 };
 197
 198 #endif