2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 #include "main/mtypes.h"
27 #include "brw_context.h"
28 #include "brw_state.h"
29 #include "brw_defines.h"
32 brw_isl_format_for_mesa_format(mesa_format mesa_format
)
34 /* This table is ordered according to the enum ordering in formats.h. We do
35 * expect that enum to be extended without our explicit initialization
36 * staying in sync, so we initialize to 0 even though
37 * ISL_FORMAT_R32G32B32A32_FLOAT happens to also be 0.
39 static const enum isl_format table
[MESA_FORMAT_COUNT
] = {
40 [0 ... MESA_FORMAT_COUNT
-1] = ISL_FORMAT_UNSUPPORTED
,
42 [MESA_FORMAT_R8G8B8A8_UNORM
] = ISL_FORMAT_R8G8B8A8_UNORM
,
43 [MESA_FORMAT_B8G8R8A8_UNORM
] = ISL_FORMAT_B8G8R8A8_UNORM
,
44 [MESA_FORMAT_R8G8B8X8_UNORM
] = ISL_FORMAT_R8G8B8X8_UNORM
,
45 [MESA_FORMAT_B8G8R8X8_UNORM
] = ISL_FORMAT_B8G8R8X8_UNORM
,
46 [MESA_FORMAT_RGB_UNORM8
] = ISL_FORMAT_R8G8B8_UNORM
,
47 [MESA_FORMAT_B5G6R5_UNORM
] = ISL_FORMAT_B5G6R5_UNORM
,
48 [MESA_FORMAT_B4G4R4A4_UNORM
] = ISL_FORMAT_B4G4R4A4_UNORM
,
49 [MESA_FORMAT_B5G5R5A1_UNORM
] = ISL_FORMAT_B5G5R5A1_UNORM
,
50 [MESA_FORMAT_L8A8_UNORM
] = ISL_FORMAT_L8A8_UNORM
,
51 [MESA_FORMAT_L16A16_UNORM
] = ISL_FORMAT_L16A16_UNORM
,
52 [MESA_FORMAT_A_UNORM8
] = ISL_FORMAT_A8_UNORM
,
53 [MESA_FORMAT_A_UNORM16
] = ISL_FORMAT_A16_UNORM
,
54 [MESA_FORMAT_L_UNORM8
] = ISL_FORMAT_L8_UNORM
,
55 [MESA_FORMAT_L_UNORM16
] = ISL_FORMAT_L16_UNORM
,
56 [MESA_FORMAT_I_UNORM8
] = ISL_FORMAT_I8_UNORM
,
57 [MESA_FORMAT_I_UNORM16
] = ISL_FORMAT_I16_UNORM
,
58 [MESA_FORMAT_YCBCR_REV
] = ISL_FORMAT_YCRCB_NORMAL
,
59 [MESA_FORMAT_YCBCR
] = ISL_FORMAT_YCRCB_SWAPUVY
,
60 [MESA_FORMAT_R_UNORM8
] = ISL_FORMAT_R8_UNORM
,
61 [MESA_FORMAT_R8G8_UNORM
] = ISL_FORMAT_R8G8_UNORM
,
62 [MESA_FORMAT_R_UNORM16
] = ISL_FORMAT_R16_UNORM
,
63 [MESA_FORMAT_R16G16_UNORM
] = ISL_FORMAT_R16G16_UNORM
,
64 [MESA_FORMAT_B10G10R10A2_UNORM
] = ISL_FORMAT_B10G10R10A2_UNORM
,
65 [MESA_FORMAT_S_UINT8
] = ISL_FORMAT_R8_UINT
,
67 [MESA_FORMAT_B8G8R8A8_SRGB
] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB
,
68 [MESA_FORMAT_R8G8B8A8_SRGB
] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB
,
69 [MESA_FORMAT_B8G8R8X8_SRGB
] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB
,
70 [MESA_FORMAT_R_SRGB8
] = ISL_FORMAT_L8_UNORM_SRGB
,
71 [MESA_FORMAT_L_SRGB8
] = ISL_FORMAT_L8_UNORM_SRGB
,
72 [MESA_FORMAT_L8A8_SRGB
] = ISL_FORMAT_L8A8_UNORM_SRGB
,
73 [MESA_FORMAT_SRGB_DXT1
] = ISL_FORMAT_BC1_UNORM_SRGB
,
74 [MESA_FORMAT_SRGBA_DXT1
] = ISL_FORMAT_BC1_UNORM_SRGB
,
75 [MESA_FORMAT_SRGBA_DXT3
] = ISL_FORMAT_BC2_UNORM_SRGB
,
76 [MESA_FORMAT_SRGBA_DXT5
] = ISL_FORMAT_BC3_UNORM_SRGB
,
78 [MESA_FORMAT_RGB_FXT1
] = ISL_FORMAT_FXT1
,
79 [MESA_FORMAT_RGBA_FXT1
] = ISL_FORMAT_FXT1
,
80 [MESA_FORMAT_RGB_DXT1
] = ISL_FORMAT_BC1_UNORM
,
81 [MESA_FORMAT_RGBA_DXT1
] = ISL_FORMAT_BC1_UNORM
,
82 [MESA_FORMAT_RGBA_DXT3
] = ISL_FORMAT_BC2_UNORM
,
83 [MESA_FORMAT_RGBA_DXT5
] = ISL_FORMAT_BC3_UNORM
,
85 [MESA_FORMAT_RGBA_FLOAT32
] = ISL_FORMAT_R32G32B32A32_FLOAT
,
86 [MESA_FORMAT_RGBA_FLOAT16
] = ISL_FORMAT_R16G16B16A16_FLOAT
,
87 [MESA_FORMAT_RGB_FLOAT32
] = ISL_FORMAT_R32G32B32_FLOAT
,
88 [MESA_FORMAT_A_FLOAT32
] = ISL_FORMAT_A32_FLOAT
,
89 [MESA_FORMAT_A_FLOAT16
] = ISL_FORMAT_A16_FLOAT
,
90 [MESA_FORMAT_L_FLOAT32
] = ISL_FORMAT_L32_FLOAT
,
91 [MESA_FORMAT_L_FLOAT16
] = ISL_FORMAT_L16_FLOAT
,
92 [MESA_FORMAT_LA_FLOAT32
] = ISL_FORMAT_L32A32_FLOAT
,
93 [MESA_FORMAT_LA_FLOAT16
] = ISL_FORMAT_L16A16_FLOAT
,
94 [MESA_FORMAT_I_FLOAT32
] = ISL_FORMAT_I32_FLOAT
,
95 [MESA_FORMAT_I_FLOAT16
] = ISL_FORMAT_I16_FLOAT
,
96 [MESA_FORMAT_R_FLOAT32
] = ISL_FORMAT_R32_FLOAT
,
97 [MESA_FORMAT_R_FLOAT16
] = ISL_FORMAT_R16_FLOAT
,
98 [MESA_FORMAT_RG_FLOAT32
] = ISL_FORMAT_R32G32_FLOAT
,
99 [MESA_FORMAT_RG_FLOAT16
] = ISL_FORMAT_R16G16_FLOAT
,
101 [MESA_FORMAT_R_SINT8
] = ISL_FORMAT_R8_SINT
,
102 [MESA_FORMAT_RG_SINT8
] = ISL_FORMAT_R8G8_SINT
,
103 [MESA_FORMAT_RGB_SINT8
] = ISL_FORMAT_R8G8B8_SINT
,
104 [MESA_FORMAT_RGBA_SINT8
] = ISL_FORMAT_R8G8B8A8_SINT
,
105 [MESA_FORMAT_R_SINT16
] = ISL_FORMAT_R16_SINT
,
106 [MESA_FORMAT_RG_SINT16
] = ISL_FORMAT_R16G16_SINT
,
107 [MESA_FORMAT_RGB_SINT16
] = ISL_FORMAT_R16G16B16_SINT
,
108 [MESA_FORMAT_RGBA_SINT16
] = ISL_FORMAT_R16G16B16A16_SINT
,
109 [MESA_FORMAT_R_SINT32
] = ISL_FORMAT_R32_SINT
,
110 [MESA_FORMAT_RG_SINT32
] = ISL_FORMAT_R32G32_SINT
,
111 [MESA_FORMAT_RGB_SINT32
] = ISL_FORMAT_R32G32B32_SINT
,
112 [MESA_FORMAT_RGBA_SINT32
] = ISL_FORMAT_R32G32B32A32_SINT
,
114 [MESA_FORMAT_R_UINT8
] = ISL_FORMAT_R8_UINT
,
115 [MESA_FORMAT_RG_UINT8
] = ISL_FORMAT_R8G8_UINT
,
116 [MESA_FORMAT_RGB_UINT8
] = ISL_FORMAT_R8G8B8_UINT
,
117 [MESA_FORMAT_RGBA_UINT8
] = ISL_FORMAT_R8G8B8A8_UINT
,
118 [MESA_FORMAT_R_UINT16
] = ISL_FORMAT_R16_UINT
,
119 [MESA_FORMAT_RG_UINT16
] = ISL_FORMAT_R16G16_UINT
,
120 [MESA_FORMAT_RGB_UINT16
] = ISL_FORMAT_R16G16B16_UINT
,
121 [MESA_FORMAT_RGBA_UINT16
] = ISL_FORMAT_R16G16B16A16_UINT
,
122 [MESA_FORMAT_R_UINT32
] = ISL_FORMAT_R32_UINT
,
123 [MESA_FORMAT_RG_UINT32
] = ISL_FORMAT_R32G32_UINT
,
124 [MESA_FORMAT_RGB_UINT32
] = ISL_FORMAT_R32G32B32_UINT
,
125 [MESA_FORMAT_RGBA_UINT32
] = ISL_FORMAT_R32G32B32A32_UINT
,
127 [MESA_FORMAT_R_SNORM8
] = ISL_FORMAT_R8_SNORM
,
128 [MESA_FORMAT_R8G8_SNORM
] = ISL_FORMAT_R8G8_SNORM
,
129 [MESA_FORMAT_R8G8B8A8_SNORM
] = ISL_FORMAT_R8G8B8A8_SNORM
,
130 [MESA_FORMAT_R_SNORM16
] = ISL_FORMAT_R16_SNORM
,
131 [MESA_FORMAT_R16G16_SNORM
] = ISL_FORMAT_R16G16_SNORM
,
132 [MESA_FORMAT_RGB_SNORM16
] = ISL_FORMAT_R16G16B16_SNORM
,
133 [MESA_FORMAT_RGBA_SNORM16
] = ISL_FORMAT_R16G16B16A16_SNORM
,
134 [MESA_FORMAT_RGBA_UNORM16
] = ISL_FORMAT_R16G16B16A16_UNORM
,
136 [MESA_FORMAT_R_RGTC1_UNORM
] = ISL_FORMAT_BC4_UNORM
,
137 [MESA_FORMAT_R_RGTC1_SNORM
] = ISL_FORMAT_BC4_SNORM
,
138 [MESA_FORMAT_RG_RGTC2_UNORM
] = ISL_FORMAT_BC5_UNORM
,
139 [MESA_FORMAT_RG_RGTC2_SNORM
] = ISL_FORMAT_BC5_SNORM
,
141 [MESA_FORMAT_ETC1_RGB8
] = ISL_FORMAT_ETC1_RGB8
,
142 [MESA_FORMAT_ETC2_RGB8
] = ISL_FORMAT_ETC2_RGB8
,
143 [MESA_FORMAT_ETC2_SRGB8
] = ISL_FORMAT_ETC2_SRGB8
,
144 [MESA_FORMAT_ETC2_RGBA8_EAC
] = ISL_FORMAT_ETC2_EAC_RGBA8
,
145 [MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
] = ISL_FORMAT_ETC2_EAC_SRGB8_A8
,
146 [MESA_FORMAT_ETC2_R11_EAC
] = ISL_FORMAT_EAC_R11
,
147 [MESA_FORMAT_ETC2_RG11_EAC
] = ISL_FORMAT_EAC_RG11
,
148 [MESA_FORMAT_ETC2_SIGNED_R11_EAC
] = ISL_FORMAT_EAC_SIGNED_R11
,
149 [MESA_FORMAT_ETC2_SIGNED_RG11_EAC
] = ISL_FORMAT_EAC_SIGNED_RG11
,
150 [MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
] = ISL_FORMAT_ETC2_RGB8_PTA
,
151 [MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
] = ISL_FORMAT_ETC2_SRGB8_PTA
,
153 [MESA_FORMAT_BPTC_RGBA_UNORM
] = ISL_FORMAT_BC7_UNORM
,
154 [MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM
] = ISL_FORMAT_BC7_UNORM_SRGB
,
155 [MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT
] = ISL_FORMAT_BC6H_SF16
,
156 [MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT
] = ISL_FORMAT_BC6H_UF16
,
158 [MESA_FORMAT_RGBA_ASTC_4x4
] = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16
,
159 [MESA_FORMAT_RGBA_ASTC_5x4
] = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16
,
160 [MESA_FORMAT_RGBA_ASTC_5x5
] = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16
,
161 [MESA_FORMAT_RGBA_ASTC_6x5
] = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16
,
162 [MESA_FORMAT_RGBA_ASTC_6x6
] = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16
,
163 [MESA_FORMAT_RGBA_ASTC_8x5
] = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16
,
164 [MESA_FORMAT_RGBA_ASTC_8x6
] = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16
,
165 [MESA_FORMAT_RGBA_ASTC_8x8
] = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16
,
166 [MESA_FORMAT_RGBA_ASTC_10x5
] = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16
,
167 [MESA_FORMAT_RGBA_ASTC_10x6
] = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16
,
168 [MESA_FORMAT_RGBA_ASTC_10x8
] = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16
,
169 [MESA_FORMAT_RGBA_ASTC_10x10
] = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16
,
170 [MESA_FORMAT_RGBA_ASTC_12x10
] = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16
,
171 [MESA_FORMAT_RGBA_ASTC_12x12
] = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16
,
172 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4
] = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB
,
173 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4
] = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB
,
174 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5
] = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB
,
175 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5
] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB
,
176 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6
] = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB
,
177 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5
] = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB
,
178 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6
] = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB
,
179 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8
] = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB
,
180 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5
] = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB
,
181 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6
] = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB
,
182 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8
] = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB
,
183 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10
] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB
,
184 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10
] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB
,
185 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12
] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB
,
187 [MESA_FORMAT_R9G9B9E5_FLOAT
] = ISL_FORMAT_R9G9B9E5_SHAREDEXP
,
188 [MESA_FORMAT_R11G11B10_FLOAT
] = ISL_FORMAT_R11G11B10_FLOAT
,
190 [MESA_FORMAT_R10G10B10A2_UNORM
] = ISL_FORMAT_R10G10B10A2_UNORM
,
191 [MESA_FORMAT_B10G10R10A2_UINT
] = ISL_FORMAT_B10G10R10A2_UINT
,
192 [MESA_FORMAT_R10G10B10A2_UINT
] = ISL_FORMAT_R10G10B10A2_UINT
,
194 [MESA_FORMAT_B5G5R5X1_UNORM
] = ISL_FORMAT_B5G5R5X1_UNORM
,
195 [MESA_FORMAT_R8G8B8X8_SRGB
] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB
,
196 [MESA_FORMAT_B10G10R10X2_UNORM
] = ISL_FORMAT_B10G10R10X2_UNORM
,
197 [MESA_FORMAT_RGBX_UNORM16
] = ISL_FORMAT_R16G16B16X16_UNORM
,
198 [MESA_FORMAT_RGBX_FLOAT16
] = ISL_FORMAT_R16G16B16X16_FLOAT
,
199 [MESA_FORMAT_RGBX_FLOAT32
] = ISL_FORMAT_R32G32B32X32_FLOAT
,
202 assert(mesa_format
< MESA_FORMAT_COUNT
);
203 return table
[mesa_format
];
207 intel_screen_init_surface_formats(struct intel_screen
*screen
)
209 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
212 memset(&screen
->mesa_format_supports_texture
, 0,
213 sizeof(screen
->mesa_format_supports_texture
));
215 int gen
= devinfo
->gen
* 10;
216 if (devinfo
->is_g4x
|| devinfo
->is_haswell
)
219 for (format
= MESA_FORMAT_NONE
+ 1; format
< MESA_FORMAT_COUNT
; format
++) {
220 enum isl_format texture
, render
;
221 bool is_integer
= _mesa_is_format_integer_color(format
);
223 render
= texture
= brw_isl_format_for_mesa_format(format
);
225 if (texture
== ISL_FORMAT_UNSUPPORTED
)
228 /* Don't advertise 8 and 16-bit RGB formats to core mesa. This ensures
229 * that they are renderable from an API perspective since core mesa will
230 * fall back to RGBA or RGBX (we can't render to non-power-of-two
231 * formats). For 8-bit, formats, this also keeps us from hitting some
232 * nasty corners in intel_miptree_map_blit if you ever try to map one.
234 int format_size
= _mesa_get_format_bytes(format
);
235 if (format_size
== 3 || format_size
== 6)
238 if (isl_format_supports_sampling(devinfo
, texture
) &&
239 (isl_format_supports_filtering(devinfo
, texture
) || is_integer
))
240 screen
->mesa_format_supports_texture
[format
] = true;
242 /* Re-map some render target formats to make them supported when they
243 * wouldn't be using their format for texturing.
246 /* For these formats, we just need to read/write the first
247 * channel into R, which is to say that we just treat them as
250 case ISL_FORMAT_I32_FLOAT
:
251 case ISL_FORMAT_L32_FLOAT
:
252 render
= ISL_FORMAT_R32_FLOAT
;
254 case ISL_FORMAT_I16_FLOAT
:
255 case ISL_FORMAT_L16_FLOAT
:
256 render
= ISL_FORMAT_R16_FLOAT
;
258 case ISL_FORMAT_I8_UNORM
:
259 case ISL_FORMAT_L8_UNORM
:
260 render
= ISL_FORMAT_R8_UNORM
;
262 case ISL_FORMAT_I16_UNORM
:
263 case ISL_FORMAT_L16_UNORM
:
264 render
= ISL_FORMAT_R16_UNORM
;
266 case ISL_FORMAT_R16G16B16X16_UNORM
:
267 render
= ISL_FORMAT_R16G16B16A16_UNORM
;
269 case ISL_FORMAT_R16G16B16X16_FLOAT
:
270 render
= ISL_FORMAT_R16G16B16A16_FLOAT
;
272 case ISL_FORMAT_B8G8R8X8_UNORM
:
273 /* XRGB is handled as ARGB because the chips in this family
274 * cannot render to XRGB targets. This means that we have to
275 * mask writes to alpha (ala glColorMask) and reconfigure the
276 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
277 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
278 * used. On Gen8+ BGRX is actually allowed (but not RGBX).
280 if (!isl_format_supports_rendering(devinfo
, texture
))
281 render
= ISL_FORMAT_B8G8R8A8_UNORM
;
283 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
284 if (!isl_format_supports_rendering(devinfo
, texture
))
285 render
= ISL_FORMAT_B8G8R8A8_UNORM_SRGB
;
287 case ISL_FORMAT_R8G8B8X8_UNORM
:
288 render
= ISL_FORMAT_R8G8B8A8_UNORM
;
290 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
291 render
= ISL_FORMAT_R8G8B8A8_UNORM_SRGB
;
297 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
298 * integer, so we don't need hardware support for blending on it. Other
299 * than that, GL in general requires alpha blending for render targets,
300 * even though we don't support it for some formats.
302 if (isl_format_supports_rendering(devinfo
, render
) &&
303 (isl_format_supports_alpha_blending(devinfo
, render
) || is_integer
)) {
304 screen
->mesa_to_isl_render_format
[format
] = render
;
305 screen
->mesa_format_supports_render
[format
] = true;
309 /* We will check this table for FBO completeness, but the surface format
310 * table above only covered color rendering.
312 screen
->mesa_format_supports_render
[MESA_FORMAT_Z24_UNORM_S8_UINT
] = true;
313 screen
->mesa_format_supports_render
[MESA_FORMAT_Z24_UNORM_X8_UINT
] = true;
314 screen
->mesa_format_supports_render
[MESA_FORMAT_S_UINT8
] = true;
315 screen
->mesa_format_supports_render
[MESA_FORMAT_Z_FLOAT32
] = true;
316 screen
->mesa_format_supports_render
[MESA_FORMAT_Z32_FLOAT_S8X24_UINT
] = true;
318 screen
->mesa_format_supports_render
[MESA_FORMAT_Z_UNORM16
] = true;
320 /* We remap depth formats to a supported texturing format in
321 * translate_tex_format().
323 screen
->mesa_format_supports_texture
[MESA_FORMAT_Z24_UNORM_S8_UINT
] = true;
324 screen
->mesa_format_supports_texture
[MESA_FORMAT_Z24_UNORM_X8_UINT
] = true;
325 screen
->mesa_format_supports_texture
[MESA_FORMAT_Z_FLOAT32
] = true;
326 screen
->mesa_format_supports_texture
[MESA_FORMAT_Z32_FLOAT_S8X24_UINT
] = true;
327 screen
->mesa_format_supports_texture
[MESA_FORMAT_S_UINT8
] = true;
329 /* Benchmarking shows that Z16 is slower than Z24, so there's no reason to
330 * use it unless you're under memory (not memory bandwidth) pressure.
332 * Apparently, the GPU's depth scoreboarding works on a 32-bit granularity,
333 * which corresponds to one pixel in the depth buffer for Z24 or Z32 formats.
334 * However, it corresponds to two pixels with Z16, which means both need to
335 * hit the early depth case in order for it to happen.
337 * Other speculation is that we may be hitting increased fragment shader
338 * execution from GL_LEQUAL/GL_EQUAL depth tests at reduced precision.
340 * With the PMA stall workaround in place, Z16 is faster than Z24, as it
344 screen
->mesa_format_supports_texture
[MESA_FORMAT_Z_UNORM16
] = true;
346 /* The RGBX formats are not renderable. Normally these get mapped
347 * internally to RGBA formats when rendering. However on Gen9+ when this
348 * internal override is used fast clears don't work so they are disabled in
349 * brw_meta_fast_clear. To avoid this problem we can just pretend not to
350 * support RGBX formats at all. This will cause the upper layers of Mesa to
351 * pick the RGBA formats instead. This works fine because when it is used
352 * as a texture source the swizzle state is programmed to force the alpha
353 * channel to 1.0 anyway. We could also do this for all gens except that
354 * it's a bit more difficult when the hardware doesn't support texture
355 * swizzling. Gens using the blorp have further problems because that
356 * doesn't implement this swizzle override. We don't need to do this for
357 * BGRX because that actually is supported natively on Gen8+.
360 static const mesa_format rgbx_formats
[] = {
361 MESA_FORMAT_R8G8B8X8_UNORM
,
362 MESA_FORMAT_R8G8B8X8_SRGB
,
363 MESA_FORMAT_RGBX_UNORM16
,
364 MESA_FORMAT_RGBX_FLOAT16
,
365 MESA_FORMAT_RGBX_FLOAT32
368 for (int i
= 0; i
< ARRAY_SIZE(rgbx_formats
); i
++) {
369 screen
->mesa_format_supports_texture
[rgbx_formats
[i
]] = false;
370 screen
->mesa_format_supports_render
[rgbx_formats
[i
]] = false;
374 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
375 * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
377 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC1_RGB8
] = true;
379 /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
380 * MESA_FORMAT during glCompressedTexImage2D().
381 * See intel_mipmap_tree::wraps_etc2.
383 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_RGB8
] = true;
384 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_SRGB8
] = true;
385 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_RGBA8_EAC
] = true;
386 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
] = true;
387 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_R11_EAC
] = true;
388 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_RG11_EAC
] = true;
389 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_SIGNED_R11_EAC
] = true;
390 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_SIGNED_RG11_EAC
] = true;
391 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
] = true;
392 screen
->mesa_format_supports_texture
[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
] = true;
396 brw_init_surface_formats(struct brw_context
*brw
)
398 struct intel_screen
*screen
= brw
->screen
;
399 struct gl_context
*ctx
= &brw
->ctx
;
401 brw
->mesa_format_supports_render
= screen
->mesa_format_supports_render
;
402 brw
->mesa_to_isl_render_format
= screen
->mesa_to_isl_render_format
;
404 STATIC_ASSERT(ARRAY_SIZE(ctx
->TextureFormatSupported
) ==
405 ARRAY_SIZE(screen
->mesa_format_supports_texture
));
407 for (unsigned i
= 0; i
< ARRAY_SIZE(ctx
->TextureFormatSupported
); ++i
) {
408 ctx
->TextureFormatSupported
[i
] = screen
->mesa_format_supports_texture
[i
];
413 brw_render_target_supported(struct brw_context
*brw
,
414 struct gl_renderbuffer
*rb
)
416 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
417 mesa_format format
= rb
->Format
;
419 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
420 * we would consider them renderable even though we don't have surface
421 * support for their alpha behavior and don't have the blending unit
422 * available to fake it like we do for XRGB8888. Force them to being
425 if (_mesa_is_format_integer_color(format
) &&
426 rb
->_BaseFormat
!= GL_RGBA
&&
427 rb
->_BaseFormat
!= GL_RG
&&
428 rb
->_BaseFormat
!= GL_RED
)
431 /* Under some conditions, MSAA is not supported for formats whose width is
434 if (devinfo
->gen
< 8 &&
435 rb
->NumSamples
> 0 && _mesa_get_format_bytes(format
) > 8) {
436 /* Gen6: MSAA on >64 bit formats is unsupported. */
437 if (devinfo
->gen
<= 6)
440 /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
441 if (rb
->NumSamples
>= 8)
445 return brw
->mesa_format_supports_render
[format
];
449 translate_tex_format(struct brw_context
*brw
,
450 mesa_format mesa_format
,
453 struct gl_context
*ctx
= &brw
->ctx
;
454 if (srgb_decode
== GL_SKIP_DECODE_EXT
)
455 mesa_format
= _mesa_get_srgb_format_linear(mesa_format
);
457 switch( mesa_format
) {
459 case MESA_FORMAT_Z_UNORM16
:
460 return ISL_FORMAT_R16_UNORM
;
462 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
463 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
464 return ISL_FORMAT_R24_UNORM_X8_TYPELESS
;
466 case MESA_FORMAT_Z_FLOAT32
:
467 return ISL_FORMAT_R32_FLOAT
;
469 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
470 return ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
;
472 case MESA_FORMAT_RGBA_FLOAT32
:
473 /* The value of this ISL surface format is 0, which tricks the
476 return ISL_FORMAT_R32G32B32A32_FLOAT
;
478 case MESA_FORMAT_RGBA_ASTC_4x4
:
479 case MESA_FORMAT_RGBA_ASTC_5x4
:
480 case MESA_FORMAT_RGBA_ASTC_5x5
:
481 case MESA_FORMAT_RGBA_ASTC_6x5
:
482 case MESA_FORMAT_RGBA_ASTC_6x6
:
483 case MESA_FORMAT_RGBA_ASTC_8x5
:
484 case MESA_FORMAT_RGBA_ASTC_8x6
:
485 case MESA_FORMAT_RGBA_ASTC_8x8
:
486 case MESA_FORMAT_RGBA_ASTC_10x5
:
487 case MESA_FORMAT_RGBA_ASTC_10x6
:
488 case MESA_FORMAT_RGBA_ASTC_10x8
:
489 case MESA_FORMAT_RGBA_ASTC_10x10
:
490 case MESA_FORMAT_RGBA_ASTC_12x10
:
491 case MESA_FORMAT_RGBA_ASTC_12x12
: {
492 enum isl_format isl_fmt
=
493 brw_isl_format_for_mesa_format(mesa_format
);
496 * It is possible to process these formats using the LDR Profile
497 * or the Full Profile mode of the hardware. Because, it isn't
498 * possible to determine if an HDR or LDR texture is being rendered, we
499 * can't determine which mode to enable in the hardware. Therefore, to
500 * handle all cases, always default to Full profile unless we are
501 * processing sRGBs, which are incompatible with this mode.
503 if (ctx
->Extensions
.KHR_texture_compression_astc_hdr
)
504 isl_fmt
|= GEN9_SURFACE_ASTC_HDR_FORMAT_BIT
;
510 return brw_isl_format_for_mesa_format(mesa_format
);
515 * Convert a MESA_FORMAT to the corresponding BRW_DEPTHFORMAT enum.
518 brw_depth_format(struct brw_context
*brw
, mesa_format format
)
520 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
523 case MESA_FORMAT_Z_UNORM16
:
524 return BRW_DEPTHFORMAT_D16_UNORM
;
525 case MESA_FORMAT_Z_FLOAT32
:
526 return BRW_DEPTHFORMAT_D32_FLOAT
;
527 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
528 if (devinfo
->gen
>= 6) {
529 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
531 /* Use D24_UNORM_S8, not D24_UNORM_X8.
533 * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
534 * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
535 * 3DSTATE_DEPTH_BUFFER.Surface_Format).
537 * However, on Gen5, D24_UNORM_X8 may be used only if separate
538 * stencil is enabled, and we never enable it. From the Ironlake PRM,
539 * same section as above, 3DSTATE_DEPTH_BUFFER's
540 * "Separate Stencil Buffer Enable" bit:
542 * "If this field is disabled, the Surface Format of the depth
543 * buffer cannot be D24_UNORM_X8_UINT."
545 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
547 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
548 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
549 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
550 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT
;
552 unreachable("Unexpected depth format.");