src/mesa/drivers/dri/i965/brw_surface_formats.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24
  25 #include "isl/isl.h"
  26
  27 #include "brw_context.h"
  28 #include "brw_state.h"
  29 #include "brw_defines.h"
  30
  31 enum isl_format
  32 brw_isl_format_for_mesa_format(mesa_format mesa_format)
  33 {
  34    /* This table is ordered according to the enum ordering in formats.h.  We do
  35     * expect that enum to be extended without our explicit initialization
  36     * staying in sync, so we initialize to 0 even though
  37     * ISL_FORMAT_R32G32B32A32_FLOAT happens to also be 0.
  38     */
  39    static const enum isl_format table[MESA_FORMAT_COUNT] = {
  40       [0 ... MESA_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED,
  41
  42       [MESA_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,
  43       [MESA_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,
  44       [MESA_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,
  45       [MESA_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,
  46       [MESA_FORMAT_RGB_UNORM8] = ISL_FORMAT_R8G8B8_UNORM,
  47       [MESA_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,
  48       [MESA_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,
  49       [MESA_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,
  50       [MESA_FORMAT_L8A8_UNORM] = ISL_FORMAT_L8A8_UNORM,
  51       [MESA_FORMAT_L16A16_UNORM] = ISL_FORMAT_L16A16_UNORM,
  52       [MESA_FORMAT_A_UNORM8] = ISL_FORMAT_A8_UNORM,
  53       [MESA_FORMAT_A_UNORM16] = ISL_FORMAT_A16_UNORM,
  54       [MESA_FORMAT_L_UNORM8] = ISL_FORMAT_L8_UNORM,
  55       [MESA_FORMAT_L_UNORM16] = ISL_FORMAT_L16_UNORM,
  56       [MESA_FORMAT_I_UNORM8] = ISL_FORMAT_I8_UNORM,
  57       [MESA_FORMAT_I_UNORM16] = ISL_FORMAT_I16_UNORM,
  58       [MESA_FORMAT_YCBCR_REV] = ISL_FORMAT_YCRCB_NORMAL,
  59       [MESA_FORMAT_YCBCR] = ISL_FORMAT_YCRCB_SWAPUVY,
  60       [MESA_FORMAT_R_UNORM8] = ISL_FORMAT_R8_UNORM,
  61       [MESA_FORMAT_R8G8_UNORM] = ISL_FORMAT_R8G8_UNORM,
  62       [MESA_FORMAT_R_UNORM16] = ISL_FORMAT_R16_UNORM,
  63       [MESA_FORMAT_R16G16_UNORM] = ISL_FORMAT_R16G16_UNORM,
  64       [MESA_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,
  65       [MESA_FORMAT_S_UINT8] = ISL_FORMAT_R8_UINT,
  66
  67       [MESA_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
  68       [MESA_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
  69       [MESA_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
  70       [MESA_FORMAT_L_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
  71       [MESA_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
  72       [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
  73       [MESA_FORMAT_SRGBA_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
  74       [MESA_FORMAT_SRGBA_DXT3] = ISL_FORMAT_BC2_UNORM_SRGB,
  75       [MESA_FORMAT_SRGBA_DXT5] = ISL_FORMAT_BC3_UNORM_SRGB,
  76
  77       [MESA_FORMAT_RGB_FXT1] = ISL_FORMAT_FXT1,
  78       [MESA_FORMAT_RGBA_FXT1] = ISL_FORMAT_FXT1,
  79       [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_BC1_UNORM,
  80       [MESA_FORMAT_RGBA_DXT1] = ISL_FORMAT_BC1_UNORM,
  81       [MESA_FORMAT_RGBA_DXT3] = ISL_FORMAT_BC2_UNORM,
  82       [MESA_FORMAT_RGBA_DXT5] = ISL_FORMAT_BC3_UNORM,
  83
  84       [MESA_FORMAT_RGBA_FLOAT32] = ISL_FORMAT_R32G32B32A32_FLOAT,
  85       [MESA_FORMAT_RGBA_FLOAT16] = ISL_FORMAT_R16G16B16A16_FLOAT,
  86       [MESA_FORMAT_RGB_FLOAT32] = ISL_FORMAT_R32G32B32_FLOAT,
  87       [MESA_FORMAT_A_FLOAT32] = ISL_FORMAT_A32_FLOAT,
  88       [MESA_FORMAT_A_FLOAT16] = ISL_FORMAT_A16_FLOAT,
  89       [MESA_FORMAT_L_FLOAT32] = ISL_FORMAT_L32_FLOAT,
  90       [MESA_FORMAT_L_FLOAT16] = ISL_FORMAT_L16_FLOAT,
  91       [MESA_FORMAT_LA_FLOAT32] = ISL_FORMAT_L32A32_FLOAT,
  92       [MESA_FORMAT_LA_FLOAT16] = ISL_FORMAT_L16A16_FLOAT,
  93       [MESA_FORMAT_I_FLOAT32] = ISL_FORMAT_I32_FLOAT,
  94       [MESA_FORMAT_I_FLOAT16] = ISL_FORMAT_I16_FLOAT,
  95       [MESA_FORMAT_R_FLOAT32] = ISL_FORMAT_R32_FLOAT,
  96       [MESA_FORMAT_R_FLOAT16] = ISL_FORMAT_R16_FLOAT,
  97       [MESA_FORMAT_RG_FLOAT32] = ISL_FORMAT_R32G32_FLOAT,
  98       [MESA_FORMAT_RG_FLOAT16] = ISL_FORMAT_R16G16_FLOAT,
  99
 100       [MESA_FORMAT_R_SINT8] = ISL_FORMAT_R8_SINT,
 101       [MESA_FORMAT_RG_SINT8] = ISL_FORMAT_R8G8_SINT,
 102       [MESA_FORMAT_RGB_SINT8] = ISL_FORMAT_R8G8B8_SINT,
 103       [MESA_FORMAT_RGBA_SINT8] = ISL_FORMAT_R8G8B8A8_SINT,
 104       [MESA_FORMAT_R_SINT16] = ISL_FORMAT_R16_SINT,
 105       [MESA_FORMAT_RG_SINT16] = ISL_FORMAT_R16G16_SINT,
 106       [MESA_FORMAT_RGB_SINT16] = ISL_FORMAT_R16G16B16_SINT,
 107       [MESA_FORMAT_RGBA_SINT16] = ISL_FORMAT_R16G16B16A16_SINT,
 108       [MESA_FORMAT_R_SINT32] = ISL_FORMAT_R32_SINT,
 109       [MESA_FORMAT_RG_SINT32] = ISL_FORMAT_R32G32_SINT,
 110       [MESA_FORMAT_RGB_SINT32] = ISL_FORMAT_R32G32B32_SINT,
 111       [MESA_FORMAT_RGBA_SINT32] = ISL_FORMAT_R32G32B32A32_SINT,
 112
 113       [MESA_FORMAT_R_UINT8] = ISL_FORMAT_R8_UINT,
 114       [MESA_FORMAT_RG_UINT8] = ISL_FORMAT_R8G8_UINT,
 115       [MESA_FORMAT_RGB_UINT8] = ISL_FORMAT_R8G8B8_UINT,
 116       [MESA_FORMAT_RGBA_UINT8] = ISL_FORMAT_R8G8B8A8_UINT,
 117       [MESA_FORMAT_R_UINT16] = ISL_FORMAT_R16_UINT,
 118       [MESA_FORMAT_RG_UINT16] = ISL_FORMAT_R16G16_UINT,
 119       [MESA_FORMAT_RGB_UINT16] = ISL_FORMAT_R16G16B16_UINT,
 120       [MESA_FORMAT_RGBA_UINT16] = ISL_FORMAT_R16G16B16A16_UINT,
 121       [MESA_FORMAT_R_UINT32] = ISL_FORMAT_R32_UINT,
 122       [MESA_FORMAT_RG_UINT32] = ISL_FORMAT_R32G32_UINT,
 123       [MESA_FORMAT_RGB_UINT32] = ISL_FORMAT_R32G32B32_UINT,
 124       [MESA_FORMAT_RGBA_UINT32] = ISL_FORMAT_R32G32B32A32_UINT,
 125
 126       [MESA_FORMAT_R_SNORM8] = ISL_FORMAT_R8_SNORM,
 127       [MESA_FORMAT_R8G8_SNORM] = ISL_FORMAT_R8G8_SNORM,
 128       [MESA_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,
 129       [MESA_FORMAT_R_SNORM16] = ISL_FORMAT_R16_SNORM,
 130       [MESA_FORMAT_R16G16_SNORM] = ISL_FORMAT_R16G16_SNORM,
 131       [MESA_FORMAT_RGB_SNORM16] = ISL_FORMAT_R16G16B16_SNORM,
 132       [MESA_FORMAT_RGBA_SNORM16] = ISL_FORMAT_R16G16B16A16_SNORM,
 133       [MESA_FORMAT_RGBA_UNORM16] = ISL_FORMAT_R16G16B16A16_UNORM,
 134
 135       [MESA_FORMAT_R_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,
 136       [MESA_FORMAT_R_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,
 137       [MESA_FORMAT_RG_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,
 138       [MESA_FORMAT_RG_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,
 139
 140       [MESA_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,
 141       [MESA_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,
 142       [MESA_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,
 143       [MESA_FORMAT_ETC2_RGBA8_EAC] = ISL_FORMAT_ETC2_EAC_RGBA8,
 144       [MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,
 145       [MESA_FORMAT_ETC2_R11_EAC] = ISL_FORMAT_EAC_R11,
 146       [MESA_FORMAT_ETC2_RG11_EAC] = ISL_FORMAT_EAC_RG11,
 147       [MESA_FORMAT_ETC2_SIGNED_R11_EAC] = ISL_FORMAT_EAC_SIGNED_R11,
 148       [MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = ISL_FORMAT_EAC_SIGNED_RG11,
 149       [MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_RGB8_PTA,
 150       [MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_SRGB8_PTA,
 151
 152       [MESA_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,
 153       [MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM] = ISL_FORMAT_BC7_UNORM_SRGB,
 154       [MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT] = ISL_FORMAT_BC6H_SF16,
 155       [MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT] = ISL_FORMAT_BC6H_UF16,
 156
 157       [MESA_FORMAT_RGBA_ASTC_4x4]           = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,
 158       [MESA_FORMAT_RGBA_ASTC_5x4]           = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,
 159       [MESA_FORMAT_RGBA_ASTC_5x5]           = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,
 160       [MESA_FORMAT_RGBA_ASTC_6x5]           = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,
 161       [MESA_FORMAT_RGBA_ASTC_6x6]           = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,
 162       [MESA_FORMAT_RGBA_ASTC_8x5]           = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,
 163       [MESA_FORMAT_RGBA_ASTC_8x6]           = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,
 164       [MESA_FORMAT_RGBA_ASTC_8x8]           = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,
 165       [MESA_FORMAT_RGBA_ASTC_10x5]          = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,
 166       [MESA_FORMAT_RGBA_ASTC_10x6]          = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,
 167       [MESA_FORMAT_RGBA_ASTC_10x8]          = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,
 168       [MESA_FORMAT_RGBA_ASTC_10x10]         = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,
 169       [MESA_FORMAT_RGBA_ASTC_12x10]         = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,
 170       [MESA_FORMAT_RGBA_ASTC_12x12]         = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,
 171       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4]   = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,
 172       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4]   = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,
 173       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5]   = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,
 174       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5]   = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
 175       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6]   = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,
 176       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5]   = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,
 177       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6]   = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,
 178       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8]   = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,
 179       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5]  = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,
 180       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6]  = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,
 181       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8]  = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,
 182       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,
 183       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,
 184       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,
 185
 186       [MESA_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,
 187       [MESA_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,
 188
 189       [MESA_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,
 190       [MESA_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,
 191       [MESA_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,
 192
 193       [MESA_FORMAT_B5G5R5X1_UNORM] = ISL_FORMAT_B5G5R5X1_UNORM,
 194       [MESA_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,
 195       [MESA_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,
 196       [MESA_FORMAT_RGBX_UNORM16] = ISL_FORMAT_R16G16B16X16_UNORM,
 197       [MESA_FORMAT_RGBX_FLOAT16] = ISL_FORMAT_R16G16B16X16_FLOAT,
 198       [MESA_FORMAT_RGBX_FLOAT32] = ISL_FORMAT_R32G32B32X32_FLOAT,
 199    };
 200
 201    assert(mesa_format < MESA_FORMAT_COUNT);
 202    return table[mesa_format];
 203 }
 204
 205 void
 206 brw_init_surface_formats(struct brw_context *brw)
 207 {
 208    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 209    struct gl_context *ctx = &brw->ctx;
 210    int gen;
 211    mesa_format format;
 212
 213    memset(&ctx->TextureFormatSupported, 0, sizeof(ctx->TextureFormatSupported));
 214
 215    gen = brw->gen * 10;
 216    if (brw->is_g4x || brw->is_haswell)
 217       gen += 5;
 218
 219    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 220       enum isl_format texture, render;
 221       bool is_integer = _mesa_is_format_integer_color(format);
 222
 223       render = texture = brw_isl_format_for_mesa_format(format);
 224
 225       if (texture == ISL_FORMAT_UNSUPPORTED)
 226          continue;
 227
 228       /* Don't advertise 8 and 16-bit RGB formats to core mesa.  This ensures
 229        * that they are renderable from an API perspective since core mesa will
 230        * fall back to RGBA or RGBX (we can't render to non-power-of-two
 231        * formats).  For 8-bit, formats, this also keeps us from hitting some
 232        * nasty corners in intel_miptree_map_blit if you ever try to map one.
 233        */
 234       int format_size = _mesa_get_format_bytes(format);
 235       if (format_size == 3 || format_size == 6)
 236          continue;
 237
 238       if (isl_format_supports_sampling(devinfo, texture) &&
 239           (isl_format_supports_filtering(devinfo, texture) || is_integer))
 240          ctx->TextureFormatSupported[format] = true;
 241
 242       /* Re-map some render target formats to make them supported when they
 243        * wouldn't be using their format for texturing.
 244        */
 245       switch (render) {
 246          /* For these formats, we just need to read/write the first
 247           * channel into R, which is to say that we just treat them as
 248           * GL_RED.
 249           */
 250       case ISL_FORMAT_I32_FLOAT:
 251       case ISL_FORMAT_L32_FLOAT:
 252          render = ISL_FORMAT_R32_FLOAT;
 253          break;
 254       case ISL_FORMAT_I16_FLOAT:
 255       case ISL_FORMAT_L16_FLOAT:
 256          render = ISL_FORMAT_R16_FLOAT;
 257          break;
 258       case ISL_FORMAT_I8_UNORM:
 259       case ISL_FORMAT_L8_UNORM:
 260          render = ISL_FORMAT_R8_UNORM;
 261          break;
 262       case ISL_FORMAT_I16_UNORM:
 263       case ISL_FORMAT_L16_UNORM:
 264          render = ISL_FORMAT_R16_UNORM;
 265          break;
 266       case ISL_FORMAT_R16G16B16X16_UNORM:
 267          render = ISL_FORMAT_R16G16B16A16_UNORM;
 268          break;
 269       case ISL_FORMAT_R16G16B16X16_FLOAT:
 270          render = ISL_FORMAT_R16G16B16A16_FLOAT;
 271          break;
 272       case ISL_FORMAT_B8G8R8X8_UNORM:
 273          /* XRGB is handled as ARGB because the chips in this family
 274           * cannot render to XRGB targets.  This means that we have to
 275           * mask writes to alpha (ala glColorMask) and reconfigure the
 276           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 277           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 278           * used. On Gen8+ BGRX is actually allowed (but not RGBX).
 279           */
 280          if (!isl_format_supports_rendering(devinfo, texture))
 281             render = ISL_FORMAT_B8G8R8A8_UNORM;
 282          break;
 283       case ISL_FORMAT_B8G8R8X8_UNORM_SRGB:
 284          if (!isl_format_supports_rendering(devinfo, texture))
 285             render = ISL_FORMAT_B8G8R8A8_UNORM_SRGB;
 286          break;
 287       case ISL_FORMAT_R8G8B8X8_UNORM:
 288          render = ISL_FORMAT_R8G8B8A8_UNORM;
 289          break;
 290       case ISL_FORMAT_R8G8B8X8_UNORM_SRGB:
 291          render = ISL_FORMAT_R8G8B8A8_UNORM_SRGB;
 292          break;
 293       default:
 294          break;
 295       }
 296
 297       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 298        * integer, so we don't need hardware support for blending on it.  Other
 299        * than that, GL in general requires alpha blending for render targets,
 300        * even though we don't support it for some formats.
 301        */
 302       if (isl_format_supports_rendering(devinfo, render) &&
 303           (isl_format_supports_alpha_blending(devinfo, render) || is_integer)) {
 304          brw->render_target_format[format] = render;
 305          brw->format_supported_as_render_target[format] = true;
 306       }
 307    }
 308
 309    /* We will check this table for FBO completeness, but the surface format
 310     * table above only covered color rendering.
 311     */
 312    brw->format_supported_as_render_target[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
 313    brw->format_supported_as_render_target[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
 314    brw->format_supported_as_render_target[MESA_FORMAT_S_UINT8] = true;
 315    brw->format_supported_as_render_target[MESA_FORMAT_Z_FLOAT32] = true;
 316    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
 317    if (brw->gen >= 8)
 318       brw->format_supported_as_render_target[MESA_FORMAT_Z_UNORM16] = true;
 319
 320    /* We remap depth formats to a supported texturing format in
 321     * translate_tex_format().
 322     */
 323    ctx->TextureFormatSupported[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
 324    ctx->TextureFormatSupported[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
 325    ctx->TextureFormatSupported[MESA_FORMAT_Z_FLOAT32] = true;
 326    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
 327    ctx->TextureFormatSupported[MESA_FORMAT_S_UINT8] = true;
 328
 329    /* Benchmarking shows that Z16 is slower than Z24, so there's no reason to
 330     * use it unless you're under memory (not memory bandwidth) pressure.
 331     *
 332     * Apparently, the GPU's depth scoreboarding works on a 32-bit granularity,
 333     * which corresponds to one pixel in the depth buffer for Z24 or Z32 formats.
 334     * However, it corresponds to two pixels with Z16, which means both need to
 335     * hit the early depth case in order for it to happen.
 336     *
 337     * Other speculation is that we may be hitting increased fragment shader
 338     * execution from GL_LEQUAL/GL_EQUAL depth tests at reduced precision.
 339     *
 340     * With the PMA stall workaround in place, Z16 is faster than Z24, as it
 341     * should be.
 342     */
 343    if (brw->gen >= 8)
 344       ctx->TextureFormatSupported[MESA_FORMAT_Z_UNORM16] = true;
 345
 346    /* The RGBX formats are not renderable. Normally these get mapped
 347     * internally to RGBA formats when rendering. However on Gen9+ when this
 348     * internal override is used fast clears don't work so they are disabled in
 349     * brw_meta_fast_clear. To avoid this problem we can just pretend not to
 350     * support RGBX formats at all. This will cause the upper layers of Mesa to
 351     * pick the RGBA formats instead. This works fine because when it is used
 352     * as a texture source the swizzle state is programmed to force the alpha
 353     * channel to 1.0 anyway. We could also do this for all gens except that
 354     * it's a bit more difficult when the hardware doesn't support texture
 355     * swizzling. Gens using the blorp have further problems because that
 356     * doesn't implement this swizzle override. We don't need to do this for
 357     * BGRX because that actually is supported natively on Gen8+.
 358     */
 359    if (brw->gen >= 9) {
 360       static const mesa_format rgbx_formats[] = {
 361          MESA_FORMAT_R8G8B8X8_UNORM,
 362          MESA_FORMAT_R8G8B8X8_SRGB,
 363          MESA_FORMAT_RGBX_UNORM16,
 364          MESA_FORMAT_RGBX_FLOAT16,
 365          MESA_FORMAT_RGBX_FLOAT32
 366       };
 367
 368       for (int i = 0; i < ARRAY_SIZE(rgbx_formats); i++) {
 369          ctx->TextureFormatSupported[rgbx_formats[i]] = false;
 370          brw->format_supported_as_render_target[rgbx_formats[i]] = false;
 371       }
 372    }
 373
 374    /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
 375     * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
 376     */
 377    ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
 378
 379    /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
 380     * MESA_FORMAT during glCompressedTexImage2D().
 381     * See intel_mipmap_tree::wraps_etc2.
 382     */
 383    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
 384    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8] = true;
 385    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
 386    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
 387    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_R11_EAC] = true;
 388    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RG11_EAC] = true;
 389    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
 390    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
 391    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
 392    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
 393 }
 394
 395 bool
 396 brw_render_target_supported(struct brw_context *brw,
 397                             struct gl_renderbuffer *rb)
 398 {
 399    mesa_format format = rb->Format;
 400
 401    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 402     * we would consider them renderable even though we don't have surface
 403     * support for their alpha behavior and don't have the blending unit
 404     * available to fake it like we do for XRGB8888.  Force them to being
 405     * unsupported.
 406     */
 407    if (_mesa_is_format_integer_color(format) &&
 408        rb->_BaseFormat != GL_RGBA &&
 409        rb->_BaseFormat != GL_RG &&
 410        rb->_BaseFormat != GL_RED)
 411       return false;
 412
 413    /* Under some conditions, MSAA is not supported for formats whose width is
 414     * more than 64 bits.
 415     */
 416    if (brw->gen < 8 &&
 417        rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
 418       /* Gen6: MSAA on >64 bit formats is unsupported. */
 419       if (brw->gen <= 6)
 420          return false;
 421
 422       /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
 423       if (rb->NumSamples >= 8)
 424          return false;
 425    }
 426
 427    return brw->format_supported_as_render_target[format];
 428 }
 429
 430 enum isl_format
 431 translate_tex_format(struct brw_context *brw,
 432                      mesa_format mesa_format,
 433                      GLenum srgb_decode)
 434 {
 435    struct gl_context *ctx = &brw->ctx;
 436    if (srgb_decode == GL_SKIP_DECODE_EXT)
 437       mesa_format = _mesa_get_srgb_format_linear(mesa_format);
 438
 439    switch( mesa_format ) {
 440
 441    case MESA_FORMAT_Z_UNORM16:
 442       return ISL_FORMAT_R16_UNORM;
 443
 444    case MESA_FORMAT_Z24_UNORM_S8_UINT:
 445    case MESA_FORMAT_Z24_UNORM_X8_UINT:
 446       return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
 447
 448    case MESA_FORMAT_Z_FLOAT32:
 449       return ISL_FORMAT_R32_FLOAT;
 450
 451    case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
 452       return ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS;
 453
 454    case MESA_FORMAT_RGBA_FLOAT32:
 455       /* The value of this ISL surface format is 0, which tricks the
 456        * assertion below.
 457        */
 458       return ISL_FORMAT_R32G32B32A32_FLOAT;
 459
 460    case MESA_FORMAT_RGBA_ASTC_4x4:
 461    case MESA_FORMAT_RGBA_ASTC_5x4:
 462    case MESA_FORMAT_RGBA_ASTC_5x5:
 463    case MESA_FORMAT_RGBA_ASTC_6x5:
 464    case MESA_FORMAT_RGBA_ASTC_6x6:
 465    case MESA_FORMAT_RGBA_ASTC_8x5:
 466    case MESA_FORMAT_RGBA_ASTC_8x6:
 467    case MESA_FORMAT_RGBA_ASTC_8x8:
 468    case MESA_FORMAT_RGBA_ASTC_10x5:
 469    case MESA_FORMAT_RGBA_ASTC_10x6:
 470    case MESA_FORMAT_RGBA_ASTC_10x8:
 471    case MESA_FORMAT_RGBA_ASTC_10x10:
 472    case MESA_FORMAT_RGBA_ASTC_12x10:
 473    case MESA_FORMAT_RGBA_ASTC_12x12: {
 474       enum isl_format isl_fmt =
 475          brw_isl_format_for_mesa_format(mesa_format);
 476
 477       /**
 478        * It is possible to process these formats using the LDR Profile
 479        * or the Full Profile mode of the hardware. Because, it isn't
 480        * possible to determine if an HDR or LDR texture is being rendered, we
 481        * can't determine which mode to enable in the hardware. Therefore, to
 482        * handle all cases, always default to Full profile unless we are
 483        * processing sRGBs, which are incompatible with this mode.
 484        */
 485       if (ctx->Extensions.KHR_texture_compression_astc_hdr)
 486          isl_fmt |= GEN9_SURFACE_ASTC_HDR_FORMAT_BIT;
 487
 488       return isl_fmt;
 489    }
 490
 491    default:
 492       return brw_isl_format_for_mesa_format(mesa_format);
 493    }
 494 }
 495
 496 /**
 497  * Convert a MESA_FORMAT to the corresponding BRW_DEPTHFORMAT enum.
 498  */
 499 uint32_t
 500 brw_depth_format(struct brw_context *brw, mesa_format format)
 501 {
 502    switch (format) {
 503    case MESA_FORMAT_Z_UNORM16:
 504       return BRW_DEPTHFORMAT_D16_UNORM;
 505    case MESA_FORMAT_Z_FLOAT32:
 506       return BRW_DEPTHFORMAT_D32_FLOAT;
 507    case MESA_FORMAT_Z24_UNORM_X8_UINT:
 508       if (brw->gen >= 6) {
 509          return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 510       } else {
 511          /* Use D24_UNORM_S8, not D24_UNORM_X8.
 512           *
 513           * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
 514           * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
 515           * 3DSTATE_DEPTH_BUFFER.Surface_Format).
 516           *
 517           * However, on Gen5, D24_UNORM_X8 may be used only if separate
 518           * stencil is enabled, and we never enable it. From the Ironlake PRM,
 519           * same section as above, 3DSTATE_DEPTH_BUFFER's
 520           * "Separate Stencil Buffer Enable" bit:
 521           *
 522           * "If this field is disabled, the Surface Format of the depth
 523           *  buffer cannot be D24_UNORM_X8_UINT."
 524           */
 525          return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 526       }
 527    case MESA_FORMAT_Z24_UNORM_S8_UINT:
 528       return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 529    case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
 530       return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT;
 531    default:
 532       unreachable("Unexpected depth format.");
 533    }
 534 }