i965: drop brw->gen in favor of devinfo->gen
[mesa.git] / src / mesa / drivers / dri / i965 / brw_tcs.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 /**
25 * \file brw_tcs.c
26 *
27 * Tessellation control shader state upload code.
28 */
29
30 #include "brw_context.h"
31 #include "compiler/brw_nir.h"
32 #include "brw_program.h"
33 #include "brw_state.h"
34 #include "program/prog_parameter.h"
35 #include "nir_builder.h"
36
37 static nir_shader *
38 create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler,
39 const nir_shader_compiler_options *options,
40 const struct brw_tcs_prog_key *key)
41 {
42 nir_builder b;
43 nir_builder_init_simple_shader(&b, mem_ctx, MESA_SHADER_TESS_CTRL,
44 options);
45 nir_shader *nir = b.shader;
46 nir_variable *var;
47 nir_intrinsic_instr *load;
48 nir_intrinsic_instr *store;
49 nir_ssa_def *zero = nir_imm_int(&b, 0);
50 nir_ssa_def *invoc_id =
51 nir_load_system_value(&b, nir_intrinsic_load_invocation_id, 0);
52
53 nir->info.inputs_read = key->outputs_written &
54 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
55 nir->info.outputs_written = key->outputs_written;
56 nir->info.tess.tcs_vertices_out = key->input_vertices;
57 nir->info.name = ralloc_strdup(nir, "passthrough");
58 nir->num_uniforms = 8 * sizeof(uint32_t);
59
60 var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_0");
61 var->data.location = 0;
62 var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_1");
63 var->data.location = 1;
64
65 /* Write the patch URB header. */
66 for (int i = 0; i <= 1; i++) {
67 load = nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform);
68 load->num_components = 4;
69 load->src[0] = nir_src_for_ssa(zero);
70 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
71 nir_intrinsic_set_base(load, i * 4 * sizeof(uint32_t));
72 nir_builder_instr_insert(&b, &load->instr);
73
74 store = nir_intrinsic_instr_create(nir, nir_intrinsic_store_output);
75 store->num_components = 4;
76 store->src[0] = nir_src_for_ssa(&load->dest.ssa);
77 store->src[1] = nir_src_for_ssa(zero);
78 nir_intrinsic_set_base(store, VARYING_SLOT_TESS_LEVEL_INNER - i);
79 nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
80 nir_builder_instr_insert(&b, &store->instr);
81 }
82
83 /* Copy inputs to outputs. */
84 uint64_t varyings = nir->info.inputs_read;
85
86 while (varyings != 0) {
87 const int varying = ffsll(varyings) - 1;
88
89 load = nir_intrinsic_instr_create(nir,
90 nir_intrinsic_load_per_vertex_input);
91 load->num_components = 4;
92 load->src[0] = nir_src_for_ssa(invoc_id);
93 load->src[1] = nir_src_for_ssa(zero);
94 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
95 nir_intrinsic_set_base(load, varying);
96 nir_builder_instr_insert(&b, &load->instr);
97
98 store = nir_intrinsic_instr_create(nir,
99 nir_intrinsic_store_per_vertex_output);
100 store->num_components = 4;
101 store->src[0] = nir_src_for_ssa(&load->dest.ssa);
102 store->src[1] = nir_src_for_ssa(invoc_id);
103 store->src[2] = nir_src_for_ssa(zero);
104 nir_intrinsic_set_base(store, varying);
105 nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
106 nir_builder_instr_insert(&b, &store->instr);
107
108 varyings &= ~BITFIELD64_BIT(varying);
109 }
110
111 nir_validate_shader(nir);
112
113 nir = brw_preprocess_nir(compiler, nir);
114
115 return nir;
116 }
117
118 static void
119 brw_tcs_debug_recompile(struct brw_context *brw, struct gl_program *prog,
120 const struct brw_tcs_prog_key *key)
121 {
122 perf_debug("Recompiling tessellation control shader for program %d\n",
123 prog->Id);
124
125 bool found = false;
126 const struct brw_tcs_prog_key *old_key =
127 brw_find_previous_compile(&brw->cache, BRW_CACHE_TCS_PROG,
128 key->program_string_id);
129
130 if (!old_key) {
131 perf_debug(" Didn't find previous compile in the shader cache for "
132 "debug\n");
133 return;
134 }
135
136 found |= key_debug(brw, "input vertices", old_key->input_vertices,
137 key->input_vertices);
138 found |= key_debug(brw, "outputs written", old_key->outputs_written,
139 key->outputs_written);
140 found |= key_debug(brw, "patch outputs written", old_key->patch_outputs_written,
141 key->patch_outputs_written);
142 found |= key_debug(brw, "TES primitive mode", old_key->tes_primitive_mode,
143 key->tes_primitive_mode);
144 found |= key_debug(brw, "quads and equal_spacing workaround",
145 old_key->quads_workaround, key->quads_workaround);
146 found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex);
147
148 if (!found) {
149 perf_debug(" Something else\n");
150 }
151 }
152
153 static bool
154 brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp,
155 struct brw_program *tep, struct brw_tcs_prog_key *key)
156 {
157 struct gl_context *ctx = &brw->ctx;
158 const struct brw_compiler *compiler = brw->screen->compiler;
159 const struct gen_device_info *devinfo = compiler->devinfo;
160 struct brw_stage_state *stage_state = &brw->tcs.base;
161 nir_shader *nir;
162 struct brw_tcs_prog_data prog_data;
163 bool start_busy = false;
164 double start_time = 0;
165
166 void *mem_ctx = ralloc_context(NULL);
167 if (tcp) {
168 nir = tcp->program.nir;
169 } else {
170 /* Create a dummy nir_shader. We won't actually use NIR code to
171 * generate assembly (it's easier to generate assembly directly),
172 * but the whole compiler assumes one of these exists.
173 */
174 const nir_shader_compiler_options *options =
175 ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions;
176 nir = create_passthrough_tcs(mem_ctx, compiler, options, key);
177 }
178
179 memset(&prog_data, 0, sizeof(prog_data));
180
181 /* Allocate the references to the uniforms that will end up in the
182 * prog_data associated with the compiled program, and which will be freed
183 * by the state cache.
184 *
185 * Note: param_count needs to be num_uniform_components * 4, since we add
186 * padding around uniform values below vec4 size, so the worst case is that
187 * every uniform is a float which gets padded to the size of a vec4.
188 */
189 int param_count = nir->num_uniforms / 4;
190
191 prog_data.base.base.param =
192 rzalloc_array(NULL, const gl_constant_value *, param_count);
193 prog_data.base.base.pull_param =
194 rzalloc_array(NULL, const gl_constant_value *, param_count);
195 prog_data.base.base.nr_params = param_count;
196
197 if (tcp) {
198 brw_assign_common_binding_table_offsets(devinfo, &tcp->program,
199 &prog_data.base.base, 0);
200
201 prog_data.base.base.image_param =
202 rzalloc_array(NULL, struct brw_image_param,
203 tcp->program.info.num_images);
204 prog_data.base.base.nr_image_params = tcp->program.info.num_images;
205
206 brw_nir_setup_glsl_uniforms(nir, &tcp->program, &prog_data.base.base,
207 compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
208 brw_nir_analyze_ubo_ranges(compiler, tcp->program.nir,
209 prog_data.base.base.ubo_ranges);
210 } else {
211 /* Upload the Patch URB Header as the first two uniforms.
212 * Do the annoying scrambling so the shader doesn't have to.
213 */
214 const float **param = (const float **) prog_data.base.base.param;
215 static float zero = 0.0f;
216 for (int i = 0; i < 8; i++)
217 param[i] = &zero;
218
219 if (key->tes_primitive_mode == GL_QUADS) {
220 for (int i = 0; i < 4; i++)
221 param[7 - i] = &ctx->TessCtrlProgram.patch_default_outer_level[i];
222
223 param[3] = &ctx->TessCtrlProgram.patch_default_inner_level[0];
224 param[2] = &ctx->TessCtrlProgram.patch_default_inner_level[1];
225 } else if (key->tes_primitive_mode == GL_TRIANGLES) {
226 for (int i = 0; i < 3; i++)
227 param[7 - i] = &ctx->TessCtrlProgram.patch_default_outer_level[i];
228
229 param[4] = &ctx->TessCtrlProgram.patch_default_inner_level[0];
230 } else {
231 assert(key->tes_primitive_mode == GL_ISOLINES);
232 param[7] = &ctx->TessCtrlProgram.patch_default_outer_level[1];
233 param[6] = &ctx->TessCtrlProgram.patch_default_outer_level[0];
234 }
235 }
236
237 int st_index = -1;
238 if (unlikely((INTEL_DEBUG & DEBUG_SHADER_TIME) && tep))
239 st_index = brw_get_shader_time_index(brw, &tep->program, ST_TCS, true);
240
241 if (unlikely(brw->perf_debug)) {
242 start_busy = brw->batch.last_bo && brw_bo_busy(brw->batch.last_bo);
243 start_time = get_time();
244 }
245
246 unsigned program_size;
247 char *error_str;
248 const unsigned *program =
249 brw_compile_tcs(compiler, brw, mem_ctx, key, &prog_data, nir, st_index,
250 &program_size, &error_str);
251 if (program == NULL) {
252 if (tep) {
253 tep->program.sh.data->LinkStatus = linking_failure;
254 ralloc_strcat(&tep->program.sh.data->InfoLog, error_str);
255 }
256
257 _mesa_problem(NULL, "Failed to compile tessellation control shader: "
258 "%s\n", error_str);
259
260 ralloc_free(mem_ctx);
261 return false;
262 }
263
264 if (unlikely(brw->perf_debug)) {
265 if (tcp) {
266 if (tcp->compiled_once) {
267 brw_tcs_debug_recompile(brw, &tcp->program, key);
268 }
269 tcp->compiled_once = true;
270 }
271
272 if (start_busy && !brw_bo_busy(brw->batch.last_bo)) {
273 perf_debug("TCS compile took %.03f ms and stalled the GPU\n",
274 (get_time() - start_time) * 1000);
275 }
276 }
277
278 /* Scratch space is used for register spilling */
279 brw_alloc_stage_scratch(brw, stage_state,
280 prog_data.base.base.total_scratch,
281 devinfo->max_tcs_threads);
282
283 brw_upload_cache(&brw->cache, BRW_CACHE_TCS_PROG,
284 key, sizeof(*key),
285 program, program_size,
286 &prog_data, sizeof(prog_data),
287 &stage_state->prog_offset, &brw->tcs.base.prog_data);
288 ralloc_free(mem_ctx);
289
290 return true;
291 }
292
293 void
294 brw_tcs_populate_key(struct brw_context *brw,
295 struct brw_tcs_prog_key *key)
296 {
297 const struct gen_device_info *devinfo = &brw->screen->devinfo;
298 struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program;
299 struct brw_program *tep = (struct brw_program *) brw->tess_eval_program;
300 struct gl_program *tes_prog = &tep->program;
301
302 uint64_t per_vertex_slots = tes_prog->info.inputs_read;
303 uint32_t per_patch_slots = tes_prog->info.patch_inputs_read;
304
305 memset(key, 0, sizeof(*key));
306
307 if (tcp) {
308 struct gl_program *prog = &tcp->program;
309 per_vertex_slots |= prog->info.outputs_written;
310 per_patch_slots |= prog->info.patch_outputs_written;
311 }
312
313 if (devinfo->gen < 8 || !tcp)
314 key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices;
315 key->outputs_written = per_vertex_slots;
316 key->patch_outputs_written = per_patch_slots;
317
318 /* We need to specialize our code generation for tessellation levels
319 * based on the domain the DS is expecting to tessellate.
320 */
321 key->tes_primitive_mode = tep->program.info.tess.primitive_mode;
322 key->quads_workaround = devinfo->gen < 9 &&
323 tep->program.info.tess.primitive_mode == GL_QUADS &&
324 tep->program.info.tess.spacing == TESS_SPACING_EQUAL;
325
326 if (tcp) {
327 key->program_string_id = tcp->id;
328
329 /* _NEW_TEXTURE */
330 brw_populate_sampler_prog_key_data(&brw->ctx, &tcp->program, &key->tex);
331 }
332 }
333
334 void
335 brw_upload_tcs_prog(struct brw_context *brw)
336 {
337 struct brw_stage_state *stage_state = &brw->tcs.base;
338 struct brw_tcs_prog_key key;
339 /* BRW_NEW_TESS_PROGRAMS */
340 struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program;
341 MAYBE_UNUSED struct brw_program *tep =
342 (struct brw_program *) brw->tess_eval_program;
343 assert(tep);
344
345 if (!brw_state_dirty(brw,
346 _NEW_TEXTURE,
347 BRW_NEW_PATCH_PRIMITIVE |
348 BRW_NEW_TESS_PROGRAMS))
349 return;
350
351 brw_tcs_populate_key(brw, &key);
352
353 if (!brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG,
354 &key, sizeof(key),
355 &stage_state->prog_offset,
356 &brw->tcs.base.prog_data)) {
357 bool success = brw_codegen_tcs_prog(brw, tcp, tep, &key);
358 assert(success);
359 (void)success;
360 }
361 }
362
363
364 bool
365 brw_tcs_precompile(struct gl_context *ctx,
366 struct gl_shader_program *shader_prog,
367 struct gl_program *prog)
368 {
369 struct brw_context *brw = brw_context(ctx);
370 struct brw_tcs_prog_key key;
371 uint32_t old_prog_offset = brw->tcs.base.prog_offset;
372 struct brw_stage_prog_data *old_prog_data = brw->tcs.base.prog_data;
373 bool success;
374
375 struct brw_program *btcp = brw_program(prog);
376 const struct gl_linked_shader *tes =
377 shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
378 const struct gen_device_info *devinfo = &brw->screen->devinfo;
379
380 memset(&key, 0, sizeof(key));
381
382 key.program_string_id = btcp->id;
383 brw_setup_tex_for_precompile(brw, &key.tex, prog);
384
385 /* Guess that the input and output patches have the same dimensionality. */
386 if (devinfo->gen < 8)
387 key.input_vertices = prog->info.tess.tcs_vertices_out;
388
389 struct brw_program *btep;
390 if (tes) {
391 btep = brw_program(tes->Program);
392 key.tes_primitive_mode = tes->Program->info.tess.primitive_mode;
393 key.quads_workaround = devinfo->gen < 9 &&
394 tes->Program->info.tess.primitive_mode == GL_QUADS &&
395 tes->Program->info.tess.spacing == TESS_SPACING_EQUAL;
396 } else {
397 btep = NULL;
398 key.tes_primitive_mode = GL_TRIANGLES;
399 }
400
401 key.outputs_written = prog->nir->info.outputs_written;
402 key.patch_outputs_written = prog->nir->info.patch_outputs_written;
403
404 success = brw_codegen_tcs_prog(brw, btcp, btep, &key);
405
406 brw->tcs.base.prog_offset = old_prog_offset;
407 brw->tcs.base.prog_data = old_prog_data;
408
409 return success;
410 }