src/mesa/drivers/dri/i965/brw_tcs.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_tcs.c
  26  *
  27  * Tessellation control shader state upload code.
  28  */
  29
  30 #include "brw_context.h"
  31 #include "brw_nir.h"
  32 #include "brw_program.h"
  33 #include "brw_shader.h"
  34 #include "brw_state.h"
  35 #include "program/prog_parameter.h"
  36 #include "nir_builder.h"
  37
  38 static nir_shader *
  39 create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler,
  40                        const nir_shader_compiler_options *options,
  41                        const struct brw_tcs_prog_key *key)
  42 {
  43    nir_builder b;
  44    nir_builder_init_simple_shader(&b, mem_ctx, MESA_SHADER_TESS_CTRL,
  45                                   options);
  46    nir_shader *nir = b.shader;
  47    nir_variable *var;
  48    nir_intrinsic_instr *load;
  49    nir_intrinsic_instr *store;
  50    nir_ssa_def *zero = nir_imm_int(&b, 0);
  51    nir_ssa_def *invoc_id =
  52       nir_load_system_value(&b, nir_intrinsic_load_invocation_id, 0);
  53
  54    nir->info->inputs_read = key->outputs_written;
  55    nir->info->outputs_written = key->outputs_written;
  56    nir->info->tcs.vertices_out = key->input_vertices;
  57    nir->info->name = ralloc_strdup(nir, "passthrough");
  58    nir->num_uniforms = 8 * sizeof(uint32_t);
  59
  60    var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_0");
  61    var->data.location = 0;
  62    var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_1");
  63    var->data.location = 1;
  64
  65    /* Write the patch URB header. */
  66    for (int i = 0; i <= 1; i++) {
  67       load = nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform);
  68       load->num_components = 4;
  69       load->src[0] = nir_src_for_ssa(zero);
  70       nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
  71       nir_intrinsic_set_base(load, i * 4 * sizeof(uint32_t));
  72       nir_builder_instr_insert(&b, &load->instr);
  73
  74       store = nir_intrinsic_instr_create(nir, nir_intrinsic_store_output);
  75       store->num_components = 4;
  76       store->src[0] = nir_src_for_ssa(&load->dest.ssa);
  77       store->src[1] = nir_src_for_ssa(zero);
  78       nir_intrinsic_set_base(store, VARYING_SLOT_TESS_LEVEL_INNER - i);
  79       nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
  80       nir_builder_instr_insert(&b, &store->instr);
  81    }
  82
  83    /* Copy inputs to outputs. */
  84    uint64_t varyings = key->outputs_written;
  85
  86    while (varyings != 0) {
  87       const int varying = ffsll(varyings) - 1;
  88
  89       load = nir_intrinsic_instr_create(nir,
  90                                         nir_intrinsic_load_per_vertex_input);
  91       load->num_components = 4;
  92       load->src[0] = nir_src_for_ssa(invoc_id);
  93       load->src[1] = nir_src_for_ssa(zero);
  94       nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
  95       nir_intrinsic_set_base(load, varying);
  96       nir_builder_instr_insert(&b, &load->instr);
  97
  98       store = nir_intrinsic_instr_create(nir,
  99                                          nir_intrinsic_store_per_vertex_output);
 100       store->num_components = 4;
 101       store->src[0] = nir_src_for_ssa(&load->dest.ssa);
 102       store->src[1] = nir_src_for_ssa(invoc_id);
 103       store->src[2] = nir_src_for_ssa(zero);
 104       nir_intrinsic_set_base(store, varying);
 105       nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
 106       nir_builder_instr_insert(&b, &store->instr);
 107
 108       varyings &= ~BITFIELD64_BIT(varying);
 109    }
 110
 111    nir_validate_shader(nir);
 112
 113    nir = brw_preprocess_nir(compiler, nir);
 114
 115    return nir;
 116 }
 117
 118 static void
 119 brw_tcs_debug_recompile(struct brw_context *brw,
 120                        struct gl_shader_program *shader_prog,
 121                        const struct brw_tcs_prog_key *key)
 122 {
 123    struct brw_cache_item *c = NULL;
 124    const struct brw_tcs_prog_key *old_key = NULL;
 125    bool found = false;
 126
 127    perf_debug("Recompiling tessellation control shader for program %d\n",
 128               shader_prog->Name);
 129
 130    for (unsigned int i = 0; i < brw->cache.size; i++) {
 131       for (c = brw->cache.items[i]; c; c = c->next) {
 132          if (c->cache_id == BRW_CACHE_TCS_PROG) {
 133             old_key = c->key;
 134
 135             if (old_key->program_string_id == key->program_string_id)
 136                break;
 137          }
 138       }
 139       if (c)
 140          break;
 141    }
 142
 143    if (!c) {
 144       perf_debug("  Didn't find previous compile in the shader cache for "
 145                  "debug\n");
 146       return;
 147    }
 148
 149    found |= key_debug(brw, "input vertices", old_key->input_vertices,
 150                       key->input_vertices);
 151    found |= key_debug(brw, "outputs written", old_key->outputs_written,
 152                       key->outputs_written);
 153    found |= key_debug(brw, "patch outputs written", old_key->patch_outputs_written,
 154                       key->patch_outputs_written);
 155    found |= key_debug(brw, "TES primitive mode", old_key->tes_primitive_mode,
 156                       key->tes_primitive_mode);
 157    found |= key_debug(brw, "quads and equal_spacing workaround",
 158                       old_key->quads_workaround, key->quads_workaround);
 159    found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex);
 160
 161    if (!found) {
 162       perf_debug("  Something else\n");
 163    }
 164 }
 165
 166 static bool
 167 brw_codegen_tcs_prog(struct brw_context *brw,
 168                      struct gl_shader_program *shader_prog,
 169                      struct brw_program *tcp,
 170                      struct brw_tcs_prog_key *key)
 171 {
 172    struct gl_context *ctx = &brw->ctx;
 173    const struct brw_compiler *compiler = brw->screen->compiler;
 174    const struct gen_device_info *devinfo = compiler->devinfo;
 175    struct brw_stage_state *stage_state = &brw->tcs.base;
 176    nir_shader *nir;
 177    struct brw_tcs_prog_data prog_data;
 178    bool start_busy = false;
 179    double start_time = 0;
 180
 181    void *mem_ctx = ralloc_context(NULL);
 182    if (tcp) {
 183       nir = tcp->program.nir;
 184    } else {
 185       /* Create a dummy nir_shader.  We won't actually use NIR code to
 186        * generate assembly (it's easier to generate assembly directly),
 187        * but the whole compiler assumes one of these exists.
 188        */
 189       const nir_shader_compiler_options *options =
 190          ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions;
 191       nir = create_passthrough_tcs(mem_ctx, compiler, options, key);
 192    }
 193
 194    memset(&prog_data, 0, sizeof(prog_data));
 195
 196    /* Allocate the references to the uniforms that will end up in the
 197     * prog_data associated with the compiled program, and which will be freed
 198     * by the state cache.
 199     *
 200     * Note: param_count needs to be num_uniform_components * 4, since we add
 201     * padding around uniform values below vec4 size, so the worst case is that
 202     * every uniform is a float which gets padded to the size of a vec4.
 203     */
 204    struct gl_linked_shader *tcs = shader_prog ?
 205       shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] : NULL;
 206    int param_count = nir->num_uniforms / 4;
 207
 208    prog_data.base.base.param =
 209       rzalloc_array(NULL, const gl_constant_value *, param_count);
 210    prog_data.base.base.pull_param =
 211       rzalloc_array(NULL, const gl_constant_value *, param_count);
 212    prog_data.base.base.nr_params = param_count;
 213
 214    if (tcs) {
 215       brw_assign_common_binding_table_offsets(MESA_SHADER_TESS_CTRL, devinfo,
 216                                               shader_prog, &tcp->program,
 217                                               &prog_data.base.base, 0);
 218
 219       prog_data.base.base.image_param =
 220          rzalloc_array(NULL, struct brw_image_param, tcs->NumImages);
 221       prog_data.base.base.nr_image_params = tcs->NumImages;
 222
 223       brw_nir_setup_glsl_uniforms(nir, shader_prog, &tcp->program,
 224                                   &prog_data.base.base,
 225                                   compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
 226    } else {
 227       /* Upload the Patch URB Header as the first two uniforms.
 228        * Do the annoying scrambling so the shader doesn't have to.
 229        */
 230       const float **param = (const float **) prog_data.base.base.param;
 231       static float zero = 0.0f;
 232       for (int i = 0; i < 8; i++)
 233          param[i] = &zero;
 234
 235       if (key->tes_primitive_mode == GL_QUADS) {
 236          for (int i = 0; i < 4; i++)
 237             param[7 - i] = &ctx->TessCtrlProgram.patch_default_outer_level[i];
 238
 239          param[3] = &ctx->TessCtrlProgram.patch_default_inner_level[0];
 240          param[2] = &ctx->TessCtrlProgram.patch_default_inner_level[1];
 241       } else if (key->tes_primitive_mode == GL_TRIANGLES) {
 242          for (int i = 0; i < 3; i++)
 243             param[7 - i] = &ctx->TessCtrlProgram.patch_default_outer_level[i];
 244
 245          param[4] = &ctx->TessCtrlProgram.patch_default_inner_level[0];
 246       } else {
 247          assert(key->tes_primitive_mode == GL_ISOLINES);
 248          param[7] = &ctx->TessCtrlProgram.patch_default_outer_level[1];
 249          param[6] = &ctx->TessCtrlProgram.patch_default_outer_level[0];
 250       }
 251    }
 252
 253    int st_index = -1;
 254    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 255       st_index = brw_get_shader_time_index(brw, shader_prog, NULL, ST_TCS);
 256
 257    if (unlikely(brw->perf_debug)) {
 258       start_busy = brw->batch.last_bo && drm_intel_bo_busy(brw->batch.last_bo);
 259       start_time = get_time();
 260    }
 261
 262    unsigned program_size;
 263    char *error_str;
 264    const unsigned *program =
 265       brw_compile_tcs(compiler, brw, mem_ctx, key, &prog_data, nir, st_index,
 266                       &program_size, &error_str);
 267    if (program == NULL) {
 268       if (shader_prog) {
 269          shader_prog->LinkStatus = false;
 270          ralloc_strcat(&shader_prog->InfoLog, error_str);
 271       }
 272
 273       _mesa_problem(NULL, "Failed to compile tessellation control shader: "
 274                     "%s\n", error_str);
 275
 276       ralloc_free(mem_ctx);
 277       return false;
 278    }
 279
 280    if (unlikely(brw->perf_debug)) {
 281       struct brw_shader *btcs = (struct brw_shader *) tcs;
 282       if (btcs) {
 283          if (btcs->compiled_once) {
 284             brw_tcs_debug_recompile(brw, shader_prog, key);
 285          }
 286          btcs->compiled_once = true;
 287       }
 288       if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
 289          perf_debug("TCS compile took %.03f ms and stalled the GPU\n",
 290                     (get_time() - start_time) * 1000);
 291       }
 292    }
 293
 294    /* Scratch space is used for register spilling */
 295    brw_alloc_stage_scratch(brw, stage_state,
 296                            prog_data.base.base.total_scratch,
 297                            devinfo->max_tcs_threads);
 298
 299    brw_upload_cache(&brw->cache, BRW_CACHE_TCS_PROG,
 300                     key, sizeof(*key),
 301                     program, program_size,
 302                     &prog_data, sizeof(prog_data),
 303                     &stage_state->prog_offset, &brw->tcs.base.prog_data);
 304    ralloc_free(mem_ctx);
 305
 306    return true;
 307 }
 308
 309 void
 310 brw_tcs_populate_key(struct brw_context *brw,
 311                      struct brw_tcs_prog_key *key)
 312 {
 313    struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program;
 314    struct brw_program *tep = (struct brw_program *) brw->tess_eval_program;
 315    struct gl_program *tes_prog = &tep->program;
 316
 317    uint64_t per_vertex_slots = tes_prog->info.inputs_read;
 318    uint32_t per_patch_slots = tes_prog->info.patch_inputs_read;
 319
 320    memset(key, 0, sizeof(*key));
 321
 322    if (tcp) {
 323       struct gl_program *prog = &tcp->program;
 324       per_vertex_slots |= prog->info.outputs_written;
 325       per_patch_slots |= prog->info.patch_outputs_written;
 326    }
 327
 328    if (brw->gen < 8 || !tcp)
 329       key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices;
 330    key->outputs_written = per_vertex_slots;
 331    key->patch_outputs_written = per_patch_slots;
 332
 333    /* We need to specialize our code generation for tessellation levels
 334     * based on the domain the DS is expecting to tessellate.
 335     */
 336    key->tes_primitive_mode = tep->program.info.tes.primitive_mode;
 337    key->quads_workaround = brw->gen < 9 &&
 338                            tep->program.info.tes.primitive_mode == GL_QUADS &&
 339                            tep->program.info.tes.spacing == GL_EQUAL;
 340
 341    if (tcp) {
 342       key->program_string_id = tcp->id;
 343
 344       /* _NEW_TEXTURE */
 345       brw_populate_sampler_prog_key_data(&brw->ctx, &tcp->program, &key->tex);
 346    } else {
 347       key->outputs_written = tes_prog->info.inputs_read;
 348    }
 349 }
 350
 351 void
 352 brw_upload_tcs_prog(struct brw_context *brw)
 353 {
 354    struct gl_shader_program **current = brw->ctx._Shader->CurrentProgram;
 355    struct brw_stage_state *stage_state = &brw->tcs.base;
 356    struct brw_tcs_prog_key key;
 357    /* BRW_NEW_TESS_PROGRAMS */
 358    struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program;
 359    MAYBE_UNUSED struct brw_program *tep =
 360       (struct brw_program *) brw->tess_eval_program;
 361    assert(tep);
 362
 363    if (!brw_state_dirty(brw,
 364                         _NEW_TEXTURE,
 365                         BRW_NEW_PATCH_PRIMITIVE |
 366                         BRW_NEW_TESS_PROGRAMS))
 367       return;
 368
 369    brw_tcs_populate_key(brw, &key);
 370
 371    if (!brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG,
 372                          &key, sizeof(key),
 373                          &stage_state->prog_offset,
 374                          &brw->tcs.base.prog_data)) {
 375       bool success = brw_codegen_tcs_prog(brw, current[MESA_SHADER_TESS_CTRL],
 376                                           tcp, &key);
 377       assert(success);
 378       (void)success;
 379    }
 380 }
 381
 382
 383 bool
 384 brw_tcs_precompile(struct gl_context *ctx,
 385                    struct gl_shader_program *shader_prog,
 386                    struct gl_program *prog)
 387 {
 388    struct brw_context *brw = brw_context(ctx);
 389    struct brw_tcs_prog_key key;
 390    uint32_t old_prog_offset = brw->tcs.base.prog_offset;
 391    struct brw_stage_prog_data *old_prog_data = brw->tcs.base.prog_data;
 392    bool success;
 393
 394    struct brw_program *btcp = brw_program(prog);
 395    const struct gl_linked_shader *tes =
 396       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
 397
 398    memset(&key, 0, sizeof(key));
 399
 400    key.program_string_id = btcp->id;
 401    brw_setup_tex_for_precompile(brw, &key.tex, prog);
 402
 403    /* Guess that the input and output patches have the same dimensionality. */
 404    if (brw->gen < 8) {
 405       key.input_vertices = shader_prog->
 406          _LinkedShaders[MESA_SHADER_TESS_CTRL]->info.TessCtrl.VerticesOut;
 407    }
 408
 409    if (tes) {
 410       key.tes_primitive_mode = tes->info.TessEval.PrimitiveMode;
 411       key.quads_workaround = brw->gen < 9 &&
 412                              tes->info.TessEval.PrimitiveMode == GL_QUADS &&
 413                              tes->info.TessEval.Spacing == GL_EQUAL;
 414    } else {
 415       key.tes_primitive_mode = GL_TRIANGLES;
 416    }
 417
 418    key.outputs_written = prog->nir->info->outputs_written;
 419    key.patch_outputs_written = prog->nir->info->patch_outputs_written;
 420
 421    success = brw_codegen_tcs_prog(brw, shader_prog, btcp, &key);
 422
 423    brw->tcs.base.prog_offset = old_prog_offset;
 424    brw->tcs.base.prog_data = old_prog_data;
 425
 426    return success;
 427 }