2 * Copyright © 2014 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 * DEALINGS IN THE SOFTWARE.
27 * Tessellation control shader state upload code.
30 #include "brw_context.h"
32 #include "brw_program.h"
33 #include "brw_shader.h"
34 #include "brw_state.h"
35 #include "program/prog_parameter.h"
36 #include "nir_builder.h"
39 create_passthrough_tcs(const struct brw_compiler
*compiler
,
40 const nir_shader_compiler_options
*options
,
41 const struct brw_tcs_prog_key
*key
)
44 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_TESS_CTRL
, options
);
45 nir_shader
*nir
= b
.shader
;
47 nir_intrinsic_instr
*load
;
48 nir_intrinsic_instr
*store
;
49 nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
50 nir_ssa_def
*invoc_id
=
51 nir_load_system_value(&b
, nir_intrinsic_load_invocation_id
, 0);
53 nir
->info
.inputs_read
= key
->outputs_written
;
54 nir
->info
.outputs_written
= key
->outputs_written
;
55 nir
->info
.tcs
.vertices_out
= key
->input_vertices
;
56 nir
->info
.name
= ralloc_strdup(nir
, "passthrough");
57 nir
->num_uniforms
= 8 * sizeof(uint32_t);
59 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_0");
60 var
->data
.location
= 0;
61 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_1");
62 var
->data
.location
= 1;
64 /* Write the patch URB header. */
65 for (int i
= 0; i
<= 1; i
++) {
66 load
= nir_intrinsic_instr_create(nir
, nir_intrinsic_load_uniform
);
67 load
->num_components
= 4;
68 load
->src
[0] = nir_src_for_ssa(zero
);
69 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
70 nir_intrinsic_set_base(load
, i
* 4 * sizeof(uint32_t));
71 nir_builder_instr_insert(&b
, &load
->instr
);
73 store
= nir_intrinsic_instr_create(nir
, nir_intrinsic_store_output
);
74 store
->num_components
= 4;
75 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
76 store
->src
[1] = nir_src_for_ssa(zero
);
77 nir_intrinsic_set_base(store
, VARYING_SLOT_TESS_LEVEL_INNER
- i
);
78 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
79 nir_builder_instr_insert(&b
, &store
->instr
);
82 /* Copy inputs to outputs. */
83 uint64_t varyings
= key
->outputs_written
;
85 while (varyings
!= 0) {
86 const int varying
= ffsll(varyings
) - 1;
88 load
= nir_intrinsic_instr_create(nir
,
89 nir_intrinsic_load_per_vertex_input
);
90 load
->num_components
= 4;
91 load
->src
[0] = nir_src_for_ssa(invoc_id
);
92 load
->src
[1] = nir_src_for_ssa(zero
);
93 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
94 nir_intrinsic_set_base(load
, varying
);
95 nir_builder_instr_insert(&b
, &load
->instr
);
97 store
= nir_intrinsic_instr_create(nir
,
98 nir_intrinsic_store_per_vertex_output
);
99 store
->num_components
= 4;
100 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
101 store
->src
[1] = nir_src_for_ssa(invoc_id
);
102 store
->src
[2] = nir_src_for_ssa(zero
);
103 nir_intrinsic_set_base(store
, varying
);
104 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
105 nir_builder_instr_insert(&b
, &store
->instr
);
107 varyings
&= ~BITFIELD64_BIT(varying
);
110 nir_validate_shader(nir
);
112 nir
= brw_preprocess_nir(compiler
, nir
);
118 brw_tcs_debug_recompile(struct brw_context
*brw
,
119 struct gl_shader_program
*shader_prog
,
120 const struct brw_tcs_prog_key
*key
)
122 struct brw_cache_item
*c
= NULL
;
123 const struct brw_tcs_prog_key
*old_key
= NULL
;
126 perf_debug("Recompiling tessellation control shader for program %d\n",
129 for (unsigned int i
= 0; i
< brw
->cache
.size
; i
++) {
130 for (c
= brw
->cache
.items
[i
]; c
; c
= c
->next
) {
131 if (c
->cache_id
== BRW_CACHE_TCS_PROG
) {
134 if (old_key
->program_string_id
== key
->program_string_id
)
143 perf_debug(" Didn't find previous compile in the shader cache for "
148 found
|= key_debug(brw
, "input vertices", old_key
->input_vertices
,
149 key
->input_vertices
);
150 found
|= key_debug(brw
, "outputs written", old_key
->outputs_written
,
151 key
->outputs_written
);
152 found
|= key_debug(brw
, "patch outputs written", old_key
->patch_outputs_written
,
153 key
->patch_outputs_written
);
154 found
|= key_debug(brw
, "TES primitive mode", old_key
->tes_primitive_mode
,
155 key
->tes_primitive_mode
);
156 found
|= brw_debug_recompile_sampler_key(brw
, &old_key
->tex
, &key
->tex
);
159 perf_debug(" Something else\n");
164 brw_codegen_tcs_prog(struct brw_context
*brw
,
165 struct gl_shader_program
*shader_prog
,
166 struct brw_tess_ctrl_program
*tcp
,
167 struct brw_tcs_prog_key
*key
)
169 struct gl_context
*ctx
= &brw
->ctx
;
170 const struct brw_compiler
*compiler
= brw
->intelScreen
->compiler
;
171 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
172 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
174 struct brw_tcs_prog_data prog_data
;
175 bool start_busy
= false;
176 double start_time
= 0;
179 nir
= tcp
->program
.Base
.nir
;
181 /* Create a dummy nir_shader. We won't actually use NIR code to
182 * generate assembly (it's easier to generate assembly directly),
183 * but the whole compiler assumes one of these exists.
185 const nir_shader_compiler_options
*options
=
186 ctx
->Const
.ShaderCompilerOptions
[MESA_SHADER_TESS_CTRL
].NirOptions
;
187 nir
= create_passthrough_tcs(compiler
, options
, key
);
190 memset(&prog_data
, 0, sizeof(prog_data
));
192 /* Allocate the references to the uniforms that will end up in the
193 * prog_data associated with the compiled program, and which will be freed
194 * by the state cache.
196 * Note: param_count needs to be num_uniform_components * 4, since we add
197 * padding around uniform values below vec4 size, so the worst case is that
198 * every uniform is a float which gets padded to the size of a vec4.
200 struct gl_shader
*tcs
= shader_prog
?
201 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_CTRL
] : NULL
;
202 int param_count
= nir
->num_uniforms
/ 4;
204 prog_data
.base
.base
.param
=
205 rzalloc_array(NULL
, const gl_constant_value
*, param_count
);
206 prog_data
.base
.base
.pull_param
=
207 rzalloc_array(NULL
, const gl_constant_value
*, param_count
);
208 prog_data
.base
.base
.nr_params
= param_count
;
211 brw_assign_common_binding_table_offsets(MESA_SHADER_TESS_CTRL
, devinfo
,
212 shader_prog
, &tcp
->program
.Base
,
213 &prog_data
.base
.base
, 0);
215 prog_data
.base
.base
.image_param
=
216 rzalloc_array(NULL
, struct brw_image_param
, tcs
->NumImages
);
217 prog_data
.base
.base
.nr_image_params
= tcs
->NumImages
;
219 brw_nir_setup_glsl_uniforms(nir
, shader_prog
, &tcp
->program
.Base
,
220 &prog_data
.base
.base
,
221 compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
]);
223 /* Upload the Patch URB Header as the first two uniforms.
224 * Do the annoying scrambling so the shader doesn't have to.
226 const float **param
= (const float **) prog_data
.base
.base
.param
;
227 static float zero
= 0.0f
;
228 for (int i
= 0; i
< 8; i
++)
231 if (key
->tes_primitive_mode
== GL_QUADS
) {
232 for (int i
= 0; i
< 4; i
++)
233 param
[7 - i
] = &ctx
->TessCtrlProgram
.patch_default_outer_level
[i
];
235 param
[3] = &ctx
->TessCtrlProgram
.patch_default_inner_level
[0];
236 param
[2] = &ctx
->TessCtrlProgram
.patch_default_inner_level
[1];
237 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
238 for (int i
= 0; i
< 3; i
++)
239 param
[7 - i
] = &ctx
->TessCtrlProgram
.patch_default_outer_level
[i
];
241 param
[4] = &ctx
->TessCtrlProgram
.patch_default_inner_level
[0];
243 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
244 param
[7] = &ctx
->TessCtrlProgram
.patch_default_outer_level
[1];
245 param
[6] = &ctx
->TessCtrlProgram
.patch_default_outer_level
[0];
249 if (unlikely(INTEL_DEBUG
& DEBUG_TCS
) && tcs
)
250 brw_dump_ir("tessellation control", shader_prog
, tcs
, NULL
);
253 if (unlikely(INTEL_DEBUG
& DEBUG_SHADER_TIME
))
254 st_index
= brw_get_shader_time_index(brw
, shader_prog
, NULL
, ST_TCS
);
256 if (unlikely(brw
->perf_debug
)) {
257 start_busy
= brw
->batch
.last_bo
&& drm_intel_bo_busy(brw
->batch
.last_bo
);
258 start_time
= get_time();
261 void *mem_ctx
= ralloc_context(NULL
);
262 unsigned program_size
;
264 const unsigned *program
=
265 brw_compile_tcs(compiler
, brw
, mem_ctx
, key
, &prog_data
, nir
, st_index
,
266 &program_size
, &error_str
);
267 if (program
== NULL
) {
269 shader_prog
->LinkStatus
= false;
270 ralloc_strcat(&shader_prog
->InfoLog
, error_str
);
275 _mesa_problem(NULL
, "Failed to compile tessellation control shader: "
278 ralloc_free(mem_ctx
);
282 if (unlikely(brw
->perf_debug
)) {
283 struct brw_shader
*btcs
= (struct brw_shader
*) tcs
;
285 if (btcs
->compiled_once
) {
286 brw_tcs_debug_recompile(brw
, shader_prog
, key
);
288 btcs
->compiled_once
= true;
290 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
291 perf_debug("TCS compile took %.03f ms and stalled the GPU\n",
292 (get_time() - start_time
) * 1000);
296 /* Scratch space is used for register spilling */
297 brw_alloc_stage_scratch(brw
, stage_state
,
298 prog_data
.base
.base
.total_scratch
,
299 brw
->max_hs_threads
);
301 brw_upload_cache(&brw
->cache
, BRW_CACHE_TCS_PROG
,
303 program
, program_size
,
304 &prog_data
, sizeof(prog_data
),
305 &stage_state
->prog_offset
, &brw
->tcs
.prog_data
);
306 ralloc_free(mem_ctx
);
315 brw_upload_tcs_prog(struct brw_context
*brw
,
316 uint64_t per_vertex_slots
,
317 uint32_t per_patch_slots
)
319 struct gl_context
*ctx
= &brw
->ctx
;
320 struct gl_shader_program
**current
= ctx
->_Shader
->CurrentProgram
;
321 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
322 struct brw_tcs_prog_key key
;
323 /* BRW_NEW_TESS_PROGRAMS */
324 struct brw_tess_ctrl_program
*tcp
=
325 (struct brw_tess_ctrl_program
*) brw
->tess_ctrl_program
;
326 struct brw_tess_eval_program
*tep
=
327 (struct brw_tess_eval_program
*) brw
->tess_eval_program
;
330 if (!brw_state_dirty(brw
,
332 BRW_NEW_PATCH_PRIMITIVE
|
333 BRW_NEW_TESS_PROGRAMS
))
336 struct gl_program
*prog
= &tcp
->program
.Base
;
338 memset(&key
, 0, sizeof(key
));
340 if (brw
->gen
< 8 || !tcp
)
341 key
.input_vertices
= ctx
->TessCtrlProgram
.patch_vertices
;
342 key
.outputs_written
= per_vertex_slots
;
343 key
.patch_outputs_written
= per_patch_slots
;
345 /* We need to specialize our code generation for tessellation levels
346 * based on the domain the DS is expecting to tessellate.
348 key
.tes_primitive_mode
= tep
->program
.PrimitiveMode
;
351 key
.program_string_id
= tcp
->id
;
354 brw_populate_sampler_prog_key_data(ctx
, prog
, stage_state
->sampler_count
,
357 key
.outputs_written
= tep
->program
.Base
.InputsRead
;
361 if (!brw_search_cache(&brw
->cache
, BRW_CACHE_TCS_PROG
,
363 &stage_state
->prog_offset
, &brw
->tcs
.prog_data
)) {
364 bool success
= brw_codegen_tcs_prog(brw
, current
[MESA_SHADER_TESS_CTRL
],
369 brw
->tcs
.base
.prog_data
= &brw
->tcs
.prog_data
->base
.base
;
374 brw_tcs_precompile(struct gl_context
*ctx
,
375 struct gl_shader_program
*shader_prog
,
376 struct gl_program
*prog
)
378 struct brw_context
*brw
= brw_context(ctx
);
379 struct brw_tcs_prog_key key
;
380 uint32_t old_prog_offset
= brw
->tcs
.base
.prog_offset
;
381 struct brw_tcs_prog_data
*old_prog_data
= brw
->tcs
.prog_data
;
384 struct gl_tess_ctrl_program
*tcp
= (struct gl_tess_ctrl_program
*)prog
;
385 struct brw_tess_ctrl_program
*btcp
= brw_tess_ctrl_program(tcp
);
387 memset(&key
, 0, sizeof(key
));
389 key
.program_string_id
= btcp
->id
;
390 brw_setup_tex_for_precompile(brw
, &key
.tex
, prog
);
392 /* Guess that the input and output patches have the same dimensionality. */
394 key
.input_vertices
= shader_prog
->TessCtrl
.VerticesOut
;
396 key
.tes_primitive_mode
=
397 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_EVAL
] ?
398 shader_prog
->TessEval
.PrimitiveMode
: GL_TRIANGLES
;
400 key
.outputs_written
= prog
->OutputsWritten
;
401 key
.patch_outputs_written
= prog
->PatchOutputsWritten
;
403 success
= brw_codegen_tcs_prog(brw
, shader_prog
, btcp
, &key
);
405 brw
->tcs
.base
.prog_offset
= old_prog_offset
;
406 brw
->tcs
.prog_data
= old_prog_data
;