2 * Copyright © 2014 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 * DEALINGS IN THE SOFTWARE.
27 * Tessellation control shader state upload code.
30 #include "brw_context.h"
32 #include "brw_program.h"
33 #include "brw_shader.h"
34 #include "brw_state.h"
35 #include "program/prog_parameter.h"
36 #include "nir_builder.h"
39 create_passthrough_tcs(void *mem_ctx
, const struct brw_compiler
*compiler
,
40 const nir_shader_compiler_options
*options
,
41 const struct brw_tcs_prog_key
*key
)
44 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_TESS_CTRL
,
46 nir_shader
*nir
= b
.shader
;
48 nir_intrinsic_instr
*load
;
49 nir_intrinsic_instr
*store
;
50 nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
51 nir_ssa_def
*invoc_id
=
52 nir_load_system_value(&b
, nir_intrinsic_load_invocation_id
, 0);
54 nir
->info
->inputs_read
= key
->outputs_written
;
55 nir
->info
->outputs_written
= key
->outputs_written
;
56 nir
->info
->tcs
.vertices_out
= key
->input_vertices
;
57 nir
->info
->name
= ralloc_strdup(nir
, "passthrough");
58 nir
->num_uniforms
= 8 * sizeof(uint32_t);
60 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_0");
61 var
->data
.location
= 0;
62 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_1");
63 var
->data
.location
= 1;
65 /* Write the patch URB header. */
66 for (int i
= 0; i
<= 1; i
++) {
67 load
= nir_intrinsic_instr_create(nir
, nir_intrinsic_load_uniform
);
68 load
->num_components
= 4;
69 load
->src
[0] = nir_src_for_ssa(zero
);
70 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
71 nir_intrinsic_set_base(load
, i
* 4 * sizeof(uint32_t));
72 nir_builder_instr_insert(&b
, &load
->instr
);
74 store
= nir_intrinsic_instr_create(nir
, nir_intrinsic_store_output
);
75 store
->num_components
= 4;
76 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
77 store
->src
[1] = nir_src_for_ssa(zero
);
78 nir_intrinsic_set_base(store
, VARYING_SLOT_TESS_LEVEL_INNER
- i
);
79 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
80 nir_builder_instr_insert(&b
, &store
->instr
);
83 /* Copy inputs to outputs. */
84 uint64_t varyings
= key
->outputs_written
;
86 while (varyings
!= 0) {
87 const int varying
= ffsll(varyings
) - 1;
89 load
= nir_intrinsic_instr_create(nir
,
90 nir_intrinsic_load_per_vertex_input
);
91 load
->num_components
= 4;
92 load
->src
[0] = nir_src_for_ssa(invoc_id
);
93 load
->src
[1] = nir_src_for_ssa(zero
);
94 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
95 nir_intrinsic_set_base(load
, varying
);
96 nir_builder_instr_insert(&b
, &load
->instr
);
98 store
= nir_intrinsic_instr_create(nir
,
99 nir_intrinsic_store_per_vertex_output
);
100 store
->num_components
= 4;
101 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
102 store
->src
[1] = nir_src_for_ssa(invoc_id
);
103 store
->src
[2] = nir_src_for_ssa(zero
);
104 nir_intrinsic_set_base(store
, varying
);
105 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
106 nir_builder_instr_insert(&b
, &store
->instr
);
108 varyings
&= ~BITFIELD64_BIT(varying
);
111 nir_validate_shader(nir
);
113 nir
= brw_preprocess_nir(compiler
, nir
);
119 brw_tcs_debug_recompile(struct brw_context
*brw
, struct gl_program
*prog
,
120 const struct brw_tcs_prog_key
*key
)
122 struct brw_cache_item
*c
= NULL
;
123 const struct brw_tcs_prog_key
*old_key
= NULL
;
126 perf_debug("Recompiling tessellation control shader for program %d\n",
129 for (unsigned int i
= 0; i
< brw
->cache
.size
; i
++) {
130 for (c
= brw
->cache
.items
[i
]; c
; c
= c
->next
) {
131 if (c
->cache_id
== BRW_CACHE_TCS_PROG
) {
134 if (old_key
->program_string_id
== key
->program_string_id
)
143 perf_debug(" Didn't find previous compile in the shader cache for "
148 found
|= key_debug(brw
, "input vertices", old_key
->input_vertices
,
149 key
->input_vertices
);
150 found
|= key_debug(brw
, "outputs written", old_key
->outputs_written
,
151 key
->outputs_written
);
152 found
|= key_debug(brw
, "patch outputs written", old_key
->patch_outputs_written
,
153 key
->patch_outputs_written
);
154 found
|= key_debug(brw
, "TES primitive mode", old_key
->tes_primitive_mode
,
155 key
->tes_primitive_mode
);
156 found
|= key_debug(brw
, "quads and equal_spacing workaround",
157 old_key
->quads_workaround
, key
->quads_workaround
);
158 found
|= brw_debug_recompile_sampler_key(brw
, &old_key
->tex
, &key
->tex
);
161 perf_debug(" Something else\n");
166 brw_codegen_tcs_prog(struct brw_context
*brw
, struct brw_program
*tcp
,
167 struct brw_program
*tep
, struct brw_tcs_prog_key
*key
)
169 struct gl_context
*ctx
= &brw
->ctx
;
170 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
171 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
172 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
174 struct brw_tcs_prog_data prog_data
;
175 bool start_busy
= false;
176 double start_time
= 0;
178 void *mem_ctx
= ralloc_context(NULL
);
180 nir
= tcp
->program
.nir
;
182 /* Create a dummy nir_shader. We won't actually use NIR code to
183 * generate assembly (it's easier to generate assembly directly),
184 * but the whole compiler assumes one of these exists.
186 const nir_shader_compiler_options
*options
=
187 ctx
->Const
.ShaderCompilerOptions
[MESA_SHADER_TESS_CTRL
].NirOptions
;
188 nir
= create_passthrough_tcs(mem_ctx
, compiler
, options
, key
);
191 memset(&prog_data
, 0, sizeof(prog_data
));
193 /* Allocate the references to the uniforms that will end up in the
194 * prog_data associated with the compiled program, and which will be freed
195 * by the state cache.
197 * Note: param_count needs to be num_uniform_components * 4, since we add
198 * padding around uniform values below vec4 size, so the worst case is that
199 * every uniform is a float which gets padded to the size of a vec4.
201 int param_count
= nir
->num_uniforms
/ 4;
203 prog_data
.base
.base
.param
=
204 rzalloc_array(NULL
, const gl_constant_value
*, param_count
);
205 prog_data
.base
.base
.pull_param
=
206 rzalloc_array(NULL
, const gl_constant_value
*, param_count
);
207 prog_data
.base
.base
.nr_params
= param_count
;
210 brw_assign_common_binding_table_offsets(devinfo
, &tcp
->program
,
211 &prog_data
.base
.base
, 0);
213 prog_data
.base
.base
.image_param
=
214 rzalloc_array(NULL
, struct brw_image_param
,
215 tcp
->program
.info
.num_images
);
216 prog_data
.base
.base
.nr_image_params
= tcp
->program
.info
.num_images
;
218 brw_nir_setup_glsl_uniforms(nir
, &tcp
->program
, &prog_data
.base
.base
,
219 compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
]);
221 /* Upload the Patch URB Header as the first two uniforms.
222 * Do the annoying scrambling so the shader doesn't have to.
224 const float **param
= (const float **) prog_data
.base
.base
.param
;
225 static float zero
= 0.0f
;
226 for (int i
= 0; i
< 8; i
++)
229 if (key
->tes_primitive_mode
== GL_QUADS
) {
230 for (int i
= 0; i
< 4; i
++)
231 param
[7 - i
] = &ctx
->TessCtrlProgram
.patch_default_outer_level
[i
];
233 param
[3] = &ctx
->TessCtrlProgram
.patch_default_inner_level
[0];
234 param
[2] = &ctx
->TessCtrlProgram
.patch_default_inner_level
[1];
235 } else if (key
->tes_primitive_mode
== GL_TRIANGLES
) {
236 for (int i
= 0; i
< 3; i
++)
237 param
[7 - i
] = &ctx
->TessCtrlProgram
.patch_default_outer_level
[i
];
239 param
[4] = &ctx
->TessCtrlProgram
.patch_default_inner_level
[0];
241 assert(key
->tes_primitive_mode
== GL_ISOLINES
);
242 param
[7] = &ctx
->TessCtrlProgram
.patch_default_outer_level
[1];
243 param
[6] = &ctx
->TessCtrlProgram
.patch_default_outer_level
[0];
248 if (unlikely((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && tep
))
249 st_index
= brw_get_shader_time_index(brw
, &tep
->program
, ST_TCS
, true);
251 if (unlikely(brw
->perf_debug
)) {
252 start_busy
= brw
->batch
.last_bo
&& drm_intel_bo_busy(brw
->batch
.last_bo
);
253 start_time
= get_time();
256 unsigned program_size
;
258 const unsigned *program
=
259 brw_compile_tcs(compiler
, brw
, mem_ctx
, key
, &prog_data
, nir
, st_index
,
260 &program_size
, &error_str
);
261 if (program
== NULL
) {
263 tep
->program
.sh
.data
->LinkStatus
= false;
264 ralloc_strcat(&tep
->program
.sh
.data
->InfoLog
, error_str
);
267 _mesa_problem(NULL
, "Failed to compile tessellation control shader: "
270 ralloc_free(mem_ctx
);
274 if (unlikely(brw
->perf_debug
)) {
276 if (tcp
->compiled_once
) {
277 brw_tcs_debug_recompile(brw
, &tcp
->program
, key
);
279 tcp
->compiled_once
= true;
282 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
283 perf_debug("TCS compile took %.03f ms and stalled the GPU\n",
284 (get_time() - start_time
) * 1000);
288 /* Scratch space is used for register spilling */
289 brw_alloc_stage_scratch(brw
, stage_state
,
290 prog_data
.base
.base
.total_scratch
,
291 devinfo
->max_tcs_threads
);
293 brw_upload_cache(&brw
->cache
, BRW_CACHE_TCS_PROG
,
295 program
, program_size
,
296 &prog_data
, sizeof(prog_data
),
297 &stage_state
->prog_offset
, &brw
->tcs
.base
.prog_data
);
298 ralloc_free(mem_ctx
);
304 brw_tcs_populate_key(struct brw_context
*brw
,
305 struct brw_tcs_prog_key
*key
)
307 struct brw_program
*tcp
= (struct brw_program
*) brw
->tess_ctrl_program
;
308 struct brw_program
*tep
= (struct brw_program
*) brw
->tess_eval_program
;
309 struct gl_program
*tes_prog
= &tep
->program
;
311 uint64_t per_vertex_slots
= tes_prog
->info
.inputs_read
;
312 uint32_t per_patch_slots
= tes_prog
->info
.patch_inputs_read
;
314 memset(key
, 0, sizeof(*key
));
317 struct gl_program
*prog
= &tcp
->program
;
318 per_vertex_slots
|= prog
->info
.outputs_written
;
319 per_patch_slots
|= prog
->info
.patch_outputs_written
;
322 if (brw
->gen
< 8 || !tcp
)
323 key
->input_vertices
= brw
->ctx
.TessCtrlProgram
.patch_vertices
;
324 key
->outputs_written
= per_vertex_slots
;
325 key
->patch_outputs_written
= per_patch_slots
;
327 /* We need to specialize our code generation for tessellation levels
328 * based on the domain the DS is expecting to tessellate.
330 key
->tes_primitive_mode
= tep
->program
.info
.tes
.primitive_mode
;
331 key
->quads_workaround
= brw
->gen
< 9 &&
332 tep
->program
.info
.tes
.primitive_mode
== GL_QUADS
&&
333 tep
->program
.info
.tes
.spacing
== GL_EQUAL
;
336 key
->program_string_id
= tcp
->id
;
339 brw_populate_sampler_prog_key_data(&brw
->ctx
, &tcp
->program
, &key
->tex
);
344 brw_upload_tcs_prog(struct brw_context
*brw
)
346 struct brw_stage_state
*stage_state
= &brw
->tcs
.base
;
347 struct brw_tcs_prog_key key
;
348 /* BRW_NEW_TESS_PROGRAMS */
349 struct brw_program
*tcp
= (struct brw_program
*) brw
->tess_ctrl_program
;
350 MAYBE_UNUSED
struct brw_program
*tep
=
351 (struct brw_program
*) brw
->tess_eval_program
;
354 if (!brw_state_dirty(brw
,
356 BRW_NEW_PATCH_PRIMITIVE
|
357 BRW_NEW_TESS_PROGRAMS
))
360 brw_tcs_populate_key(brw
, &key
);
362 if (!brw_search_cache(&brw
->cache
, BRW_CACHE_TCS_PROG
,
364 &stage_state
->prog_offset
,
365 &brw
->tcs
.base
.prog_data
)) {
366 bool success
= brw_codegen_tcs_prog(brw
, tcp
, tep
, &key
);
374 brw_tcs_precompile(struct gl_context
*ctx
,
375 struct gl_shader_program
*shader_prog
,
376 struct gl_program
*prog
)
378 struct brw_context
*brw
= brw_context(ctx
);
379 struct brw_tcs_prog_key key
;
380 uint32_t old_prog_offset
= brw
->tcs
.base
.prog_offset
;
381 struct brw_stage_prog_data
*old_prog_data
= brw
->tcs
.base
.prog_data
;
384 struct brw_program
*btcp
= brw_program(prog
);
385 const struct gl_linked_shader
*tes
=
386 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_EVAL
];
388 memset(&key
, 0, sizeof(key
));
390 key
.program_string_id
= btcp
->id
;
391 brw_setup_tex_for_precompile(brw
, &key
.tex
, prog
);
393 /* Guess that the input and output patches have the same dimensionality. */
395 key
.input_vertices
= shader_prog
->
396 _LinkedShaders
[MESA_SHADER_TESS_CTRL
]->info
.TessCtrl
.VerticesOut
;
399 struct brw_program
*btep
;
401 btep
= brw_program(tes
->Program
);
402 key
.tes_primitive_mode
= tes
->info
.TessEval
.PrimitiveMode
;
403 key
.quads_workaround
= brw
->gen
< 9 &&
404 tes
->info
.TessEval
.PrimitiveMode
== GL_QUADS
&&
405 tes
->info
.TessEval
.Spacing
== GL_EQUAL
;
408 key
.tes_primitive_mode
= GL_TRIANGLES
;
411 key
.outputs_written
= prog
->nir
->info
->outputs_written
;
412 key
.patch_outputs_written
= prog
->nir
->info
->patch_outputs_written
;
414 success
= brw_codegen_tcs_prog(brw
, btcp
, btep
, &key
);
416 brw
->tcs
.base
.prog_offset
= old_prog_offset
;
417 brw
->tcs
.base
.prog_data
= old_prog_data
;