i965: Calculate thread_count in brw_alloc_stage_scratch
[mesa.git] / src / mesa / drivers / dri / i965 / brw_tes.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 /**
25 * \file brw_tes.c
26 *
27 * Tessellation evaluation shader state upload code.
28 */
29
30 #include "brw_context.h"
31 #include "compiler/brw_nir.h"
32 #include "brw_program.h"
33 #include "brw_state.h"
34 #include "program/prog_parameter.h"
35
36 static void
37 brw_tes_debug_recompile(struct brw_context *brw, struct gl_program *prog,
38 const struct brw_tes_prog_key *key)
39 {
40 perf_debug("Recompiling tessellation evaluation shader for program %d\n",
41 prog->Id);
42
43 bool found = false;
44 const struct brw_tes_prog_key *old_key =
45 brw_find_previous_compile(&brw->cache, BRW_CACHE_TES_PROG,
46 key->program_string_id);
47
48 if (!old_key) {
49 perf_debug(" Didn't find previous compile in the shader cache for "
50 "debug\n");
51 return;
52 }
53
54 found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex);
55 found |= key_debug(brw, "inputs read", old_key->inputs_read,
56 key->inputs_read);
57 found |= key_debug(brw, "patch inputs read", old_key->patch_inputs_read,
58 key->patch_inputs_read);
59
60 if (!found) {
61 perf_debug(" Something else\n");
62 }
63 }
64
65 static bool
66 brw_codegen_tes_prog(struct brw_context *brw,
67 struct brw_program *tep,
68 struct brw_tes_prog_key *key)
69 {
70 const struct brw_compiler *compiler = brw->screen->compiler;
71 const struct gen_device_info *devinfo = &brw->screen->devinfo;
72 struct brw_stage_state *stage_state = &brw->tes.base;
73 nir_shader *nir = tep->program.nir;
74 struct brw_tes_prog_data prog_data;
75 bool start_busy = false;
76 double start_time = 0;
77
78 memset(&prog_data, 0, sizeof(prog_data));
79
80 void *mem_ctx = ralloc_context(NULL);
81
82 brw_assign_common_binding_table_offsets(devinfo, &tep->program,
83 &prog_data.base.base, 0);
84
85 brw_nir_setup_glsl_uniforms(mem_ctx, nir, &tep->program,
86 &prog_data.base.base,
87 compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
88 brw_nir_analyze_ubo_ranges(compiler, tep->program.nir,
89 prog_data.base.base.ubo_ranges);
90
91 int st_index = -1;
92 if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
93 st_index = brw_get_shader_time_index(brw, &tep->program, ST_TES, true);
94
95 if (unlikely(brw->perf_debug)) {
96 start_busy = brw->batch.last_bo && brw_bo_busy(brw->batch.last_bo);
97 start_time = get_time();
98 }
99
100 struct brw_vue_map input_vue_map;
101 brw_compute_tess_vue_map(&input_vue_map, key->inputs_read,
102 key->patch_inputs_read);
103
104 char *error_str;
105 const unsigned *program =
106 brw_compile_tes(compiler, brw, mem_ctx, key, &input_vue_map, &prog_data,
107 nir, &tep->program, st_index, &error_str);
108 if (program == NULL) {
109 tep->program.sh.data->LinkStatus = linking_failure;
110 ralloc_strcat(&tep->program.sh.data->InfoLog, error_str);
111
112 _mesa_problem(NULL, "Failed to compile tessellation evaluation shader: "
113 "%s\n", error_str);
114
115 ralloc_free(mem_ctx);
116 return false;
117 }
118
119 if (unlikely(brw->perf_debug)) {
120 if (tep->compiled_once) {
121 brw_tes_debug_recompile(brw, &tep->program, key);
122 }
123 if (start_busy && !brw_bo_busy(brw->batch.last_bo)) {
124 perf_debug("TES compile took %.03f ms and stalled the GPU\n",
125 (get_time() - start_time) * 1000);
126 }
127 tep->compiled_once = true;
128 }
129
130 /* Scratch space is used for register spilling */
131 brw_alloc_stage_scratch(brw, stage_state,
132 prog_data.base.base.total_scratch);
133
134 /* The param and pull_param arrays will be freed by the shader cache. */
135 ralloc_steal(NULL, prog_data.base.base.param);
136 ralloc_steal(NULL, prog_data.base.base.pull_param);
137 brw_upload_cache(&brw->cache, BRW_CACHE_TES_PROG,
138 key, sizeof(*key),
139 program, prog_data.base.base.program_size,
140 &prog_data, sizeof(prog_data),
141 &stage_state->prog_offset, &brw->tes.base.prog_data);
142 ralloc_free(mem_ctx);
143
144 return true;
145 }
146
147 void
148 brw_tes_populate_key(struct brw_context *brw,
149 struct brw_tes_prog_key *key)
150 {
151 struct brw_program *tcp =
152 (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
153 struct brw_program *tep =
154 (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
155 struct gl_program *prog = &tep->program;
156
157 uint64_t per_vertex_slots = prog->info.inputs_read;
158 uint32_t per_patch_slots = prog->info.patch_inputs_read;
159
160 memset(key, 0, sizeof(*key));
161
162 key->program_string_id = tep->id;
163
164 /* The TCS may have additional outputs which aren't read by the
165 * TES (possibly for cross-thread communication). These need to
166 * be stored in the Patch URB Entry as well.
167 */
168 if (tcp) {
169 struct gl_program *tcp_prog = &tcp->program;
170 per_vertex_slots |= tcp_prog->info.outputs_written &
171 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
172 per_patch_slots |= tcp_prog->info.patch_outputs_written;
173 }
174
175 key->inputs_read = per_vertex_slots;
176 key->patch_inputs_read = per_patch_slots;
177
178 /* _NEW_TEXTURE */
179 brw_populate_sampler_prog_key_data(&brw->ctx, prog, &key->tex);
180 }
181
182 void
183 brw_upload_tes_prog(struct brw_context *brw)
184 {
185 struct brw_stage_state *stage_state = &brw->tes.base;
186 struct brw_tes_prog_key key;
187 /* BRW_NEW_TESS_PROGRAMS */
188 struct brw_program *tep =
189 (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
190
191 if (!brw_state_dirty(brw,
192 _NEW_TEXTURE,
193 BRW_NEW_TESS_PROGRAMS))
194 return;
195
196 brw_tes_populate_key(brw, &key);
197
198 if (!brw_search_cache(&brw->cache, BRW_CACHE_TES_PROG,
199 &key, sizeof(key),
200 &stage_state->prog_offset,
201 &brw->tes.base.prog_data)) {
202 bool success = brw_codegen_tes_prog(brw, tep, &key);
203 assert(success);
204 (void)success;
205 }
206 }
207
208
209 bool
210 brw_tes_precompile(struct gl_context *ctx,
211 struct gl_shader_program *shader_prog,
212 struct gl_program *prog)
213 {
214 struct brw_context *brw = brw_context(ctx);
215 struct brw_tes_prog_key key;
216 uint32_t old_prog_offset = brw->tes.base.prog_offset;
217 struct brw_stage_prog_data *old_prog_data = brw->tes.base.prog_data;
218 bool success;
219
220 struct brw_program *btep = brw_program(prog);
221
222 memset(&key, 0, sizeof(key));
223
224 key.program_string_id = btep->id;
225 key.inputs_read = prog->nir->info.inputs_read;
226 key.patch_inputs_read = prog->nir->info.patch_inputs_read;
227
228 if (shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]) {
229 struct gl_program *tcp =
230 shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]->Program;
231 key.inputs_read |= tcp->nir->info.outputs_written &
232 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
233 key.patch_inputs_read |= tcp->nir->info.patch_outputs_written;
234 }
235
236 brw_setup_tex_for_precompile(brw, &key.tex, prog);
237
238 success = brw_codegen_tes_prog(brw, btep, &key);
239
240 brw->tes.base.prog_offset = old_prog_offset;
241 brw->tes.base.prog_data = old_prog_data;
242
243 return success;
244 }