2 * Copyright 2006 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * \file brw_tex_layout.cpp
29 * Code to lay out images in a mipmap tree.
31 * \author Keith Whitwell <keithw@vmware.com>
32 * \author Michel Dänzer <daenzer@vmware.com>
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
38 #include "main/glformats.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 intel_horizontal_texture_alignment_unit(struct brw_context
*brw
,
47 * From the "Alignment Unit Size" section of various specs, namely:
48 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
49 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
50 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
51 * - BSpec (for Ivybridge and slight variations in separate stencil)
53 * +----------------------------------------------------------------------+
54 * | | alignment unit width ("i") |
55 * | Surface Property |-----------------------------|
56 * | | 915 | 965 | ILK | SNB | IVB |
57 * +----------------------------------------------------------------------+
58 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
59 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
60 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
61 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
62 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
63 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
64 * | All Others | 4 | 4 | 4 | 4 | 4 |
65 * +----------------------------------------------------------------------+
67 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
68 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
70 if (_mesa_is_format_compressed(format
)) {
71 /* The hardware alignment requirements for compressed textures
72 * happen to match the block boundaries.
75 _mesa_get_format_block_size(format
, &i
, &j
);
79 if (format
== MESA_FORMAT_S_UINT8
)
82 if (brw
->gen
>= 7 && format
== MESA_FORMAT_Z_UNORM16
)
89 intel_vertical_texture_alignment_unit(struct brw_context
*brw
,
90 mesa_format format
, bool multisampled
)
93 * From the "Alignment Unit Size" section of various specs, namely:
94 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
95 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
96 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
97 * - BSpec (for Ivybridge and slight variations in separate stencil)
99 * +----------------------------------------------------------------------+
100 * | | alignment unit height ("j") |
101 * | Surface Property |-----------------------------|
102 * | | 915 | 965 | ILK | SNB | IVB |
103 * +----------------------------------------------------------------------+
104 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
105 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
106 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
107 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
108 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
109 * | All Others | 2 | 2 | 2 | * | * |
110 * +----------------------------------------------------------------------+
112 * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
113 * the SURFACE_STATE "Surface Vertical Alignment" field.
115 if (_mesa_is_format_compressed(format
))
118 if (format
== MESA_FORMAT_S_UINT8
)
119 return brw
->gen
>= 7 ? 8 : 4;
121 /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
122 * should always be used, except for stencil buffers, which should be 8.
130 GLenum base_format
= _mesa_get_format_base_format(format
);
133 (base_format
== GL_DEPTH_COMPONENT
||
134 base_format
== GL_DEPTH_STENCIL
)) {
139 /* On Gen7, we prefer a vertical alignment of 4 when possible, because
140 * that allows Y tiled render targets.
142 * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
143 * messages), on p64, under the heading "Surface Vertical Alignment":
145 * Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
146 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
149 * VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
151 if (base_format
== GL_YCBCR_MESA
|| format
== MESA_FORMAT_RGB_FLOAT32
)
161 brw_miptree_layout_2d(struct intel_mipmap_tree
*mt
)
165 unsigned width
= mt
->physical_width0
;
166 unsigned height
= mt
->physical_height0
;
167 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
169 mt
->total_width
= mt
->physical_width0
;
171 if (mt
->compressed
) {
172 mt
->total_width
= ALIGN(mt
->physical_width0
, mt
->align_w
);
175 /* May need to adjust width to accomodate the placement of
176 * the 2nd mipmap. This occurs when the alignment
177 * constraints of mipmap placement push the right edge of the
178 * 2nd mipmap out past the width of its parent.
180 if (mt
->first_level
!= mt
->last_level
) {
183 if (mt
->compressed
) {
184 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
185 ALIGN(minify(mt
->physical_width0
, 2), mt
->align_w
);
187 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
188 minify(mt
->physical_width0
, 2);
191 if (mip1_width
> mt
->total_width
) {
192 mt
->total_width
= mip1_width
;
196 mt
->total_height
= 0;
198 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
201 intel_miptree_set_level_info(mt
, level
, x
, y
, depth
);
203 img_height
= ALIGN(height
, mt
->align_h
);
205 img_height
/= mt
->align_h
;
207 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
208 /* Compact arrays with separated miplevels */
212 /* Because the images are packed better, the final offset
213 * might not be the maximal one:
215 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
217 /* Layout_below: step right after second mipmap.
219 if (level
== mt
->first_level
+ 1) {
220 x
+= ALIGN(width
, mt
->align_w
);
225 width
= minify(width
, 1);
226 height
= minify(height
, 1);
231 align_cube(struct intel_mipmap_tree
*mt
)
233 /* The 965's sampler lays cachelines out according to how accesses
234 * in the texture surfaces run, so they may be "vertical" through
235 * memory. As a result, the docs say in Surface Padding Requirements:
236 * Sampling Engine Surfaces that two extra rows of padding are required.
238 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
239 mt
->total_height
+= 2;
243 brw_miptree_layout_texture_array(struct brw_context
*brw
,
244 struct intel_mipmap_tree
*mt
)
247 unsigned height
= mt
->physical_height0
;
249 h0
= ALIGN(mt
->physical_height0
, mt
->align_h
);
250 h1
= ALIGN(minify(mt
->physical_height0
, 1), mt
->align_h
);
251 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
)
254 mt
->qpitch
= (h0
+ h1
+ (brw
->gen
>= 7 ? 12 : 11) * mt
->align_h
);
256 int physical_qpitch
= mt
->compressed
? mt
->qpitch
/ 4 : mt
->qpitch
;
258 brw_miptree_layout_2d(mt
);
260 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
262 img_height
= ALIGN(height
, mt
->align_h
);
264 img_height
/= mt
->align_h
;
266 for (int q
= 0; q
< mt
->physical_depth0
; q
++) {
267 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
268 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* img_height
);
270 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* physical_qpitch
);
273 height
= minify(height
, 1);
275 if (mt
->array_layout
== ALL_LOD_IN_EACH_SLICE
)
276 mt
->total_height
= physical_qpitch
* mt
->physical_depth0
;
282 brw_miptree_layout_texture_3d(struct brw_context
*brw
,
283 struct intel_mipmap_tree
*mt
)
285 unsigned yscale
= mt
->compressed
? 4 : 1;
288 mt
->total_height
= 0;
291 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
292 unsigned WL
= MAX2(mt
->physical_width0
>> level
, 1);
293 unsigned HL
= MAX2(mt
->physical_height0
>> level
, 1);
294 unsigned DL
= MAX2(mt
->physical_depth0
>> level
, 1);
295 unsigned wL
= ALIGN(WL
, mt
->align_w
);
296 unsigned hL
= ALIGN(HL
, mt
->align_h
);
298 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
301 intel_miptree_set_level_info(mt
, level
, 0, 0, DL
);
303 for (unsigned q
= 0; q
< DL
; q
++) {
304 unsigned x
= (q
% (1 << level
)) * wL
;
305 unsigned y
= ysum
+ (q
>> level
) * hL
;
307 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
/ yscale
);
308 mt
->total_width
= MAX2(mt
->total_width
, x
+ wL
);
309 mt
->total_height
= MAX2(mt
->total_height
, (y
+ hL
) / yscale
);
312 ysum
+= ALIGN(DL
, 1 << level
) / (1 << level
) * hL
;
319 brw_miptree_layout(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
321 bool multisampled
= mt
->num_samples
> 1;
322 bool gen6_hiz_or_stencil
= false;
324 if (brw
->gen
== 6 && mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
325 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
326 gen6_hiz_or_stencil
= _mesa_is_depth_or_stencil_format(base_format
);
329 if (gen6_hiz_or_stencil
) {
330 /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
331 * hardware doesn't support multiple mip levels on stencil/hiz.
333 * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
334 * "The hierarchical depth buffer does not support the LOD field"
336 * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
337 * "The stencil depth buffer does not support the LOD field"
339 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
340 /* Stencil uses W tiling, so we force W tiling alignment for the
341 * ALL_SLICES_AT_EACH_LOD miptree layout.
346 /* Depth uses Y tiling, so we force need Y tiling alignment for the
347 * ALL_SLICES_AT_EACH_LOD miptree layout.
349 mt
->align_w
= 128 / mt
->cpp
;
353 mt
->align_w
= intel_horizontal_texture_alignment_unit(brw
, mt
->format
);
355 intel_vertical_texture_alignment_unit(brw
, mt
->format
, multisampled
);
358 switch (mt
->target
) {
359 case GL_TEXTURE_CUBE_MAP
:
361 /* Gen4 stores cube maps as 3D textures. */
362 assert(mt
->physical_depth0
== 6);
363 brw_miptree_layout_texture_3d(brw
, mt
);
365 /* All other hardware stores cube maps as 2D arrays. */
366 brw_miptree_layout_texture_array(brw
, mt
);
371 brw_miptree_layout_texture_3d(brw
, mt
);
374 case GL_TEXTURE_1D_ARRAY
:
375 case GL_TEXTURE_2D_ARRAY
:
376 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
377 case GL_TEXTURE_CUBE_MAP_ARRAY
:
378 brw_miptree_layout_texture_array(brw
, mt
);
382 switch (mt
->msaa_layout
) {
383 case INTEL_MSAA_LAYOUT_UMS
:
384 case INTEL_MSAA_LAYOUT_CMS
:
385 brw_miptree_layout_texture_array(brw
, mt
);
387 case INTEL_MSAA_LAYOUT_NONE
:
388 case INTEL_MSAA_LAYOUT_IMS
:
389 brw_miptree_layout_2d(mt
);
394 DBG("%s: %dx%dx%d\n", __FUNCTION__
,
395 mt
->total_width
, mt
->total_height
, mt
->cpp
);