src/mesa/drivers/dri/i965/brw_tex_layout.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 /* Code to layout images in a mipmap tree for i965.
  33  */
  34
  35 #include "intel_mipmap_tree.h"
  36 #include "intel_tex_layout.h"
  37 #include "intel_context.h"
  38 #include "main/macros.h"
  39
  40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
  41
  42 static void
  43 brw_miptree_layout_texture_array(struct intel_context *intel,
  44                                  struct intel_mipmap_tree *mt)
  45 {
  46    GLuint level;
  47    GLuint qpitch = 0;
  48    int h0, h1, q;
  49
  50    h0 = ALIGN(mt->physical_height0, mt->align_h);
  51    h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
  52    if (mt->array_spacing_lod0)
  53       qpitch = h0;
  54    else
  55       qpitch = (h0 + h1 + (intel->gen >= 7 ? 12 : 11) * mt->align_h);
  56    if (mt->compressed)
  57       qpitch /= 4;
  58
  59    i945_miptree_layout_2d(mt);
  60
  61    for (level = mt->first_level; level <= mt->last_level; level++) {
  62       for (q = 0; q < mt->physical_depth0; q++) {
  63          intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
  64       }
  65    }
  66    mt->total_height = qpitch * mt->physical_depth0;
  67 }
  68
  69 static void
  70 brw_miptree_layout_texture_3d(struct intel_context *intel,
  71                               struct intel_mipmap_tree *mt)
  72 {
  73    GLuint width  = mt->physical_width0;
  74    GLuint height = mt->physical_height0;
  75    GLuint depth = mt->physical_depth0;
  76    GLuint pack_x_pitch, pack_x_nr;
  77    GLuint pack_y_pitch;
  78    GLuint level;
  79
  80    mt->total_height = 0;
  81
  82    if (mt->compressed) {
  83        mt->total_width = ALIGN(width, mt->align_w);
  84        pack_y_pitch = (height + 3) / 4;
  85    } else {
  86       mt->total_width = mt->physical_width0;
  87       pack_y_pitch = ALIGN(mt->physical_height0, mt->align_h);
  88    }
  89
  90    pack_x_pitch = width;
  91    pack_x_nr = 1;
  92
  93    for (level = mt->first_level ; level <= mt->last_level ; level++) {
  94       GLint x = 0;
  95       GLint y = 0;
  96       GLint q, j;
  97
  98       intel_miptree_set_level_info(mt, level,
  99                                    0, mt->total_height,
 100                                    width, height, depth);
 101
 102       for (q = 0; q < depth; /* empty */) {
 103          for (j = 0; j < pack_x_nr && q < depth; j++, q++) {
 104             intel_miptree_set_image_offset(mt, level, q, x, y);
 105             x += pack_x_pitch;
 106          }
 107          if (x > mt->total_width)
 108             mt->total_width = x;
 109
 110          x = 0;
 111          y += pack_y_pitch;
 112       }
 113
 114       mt->total_height += y;
 115       width  = minify(width, 1);
 116       height = minify(height, 1);
 117       if (mt->target == GL_TEXTURE_3D)
 118          depth = minify(depth, 1);
 119
 120       if (mt->compressed) {
 121          pack_y_pitch = (height + 3) / 4;
 122
 123          if (pack_x_pitch > ALIGN(width, mt->align_w)) {
 124             pack_x_pitch = ALIGN(width, mt->align_w);
 125             pack_x_nr <<= 1;
 126          }
 127       } else {
 128          pack_x_nr <<= 1;
 129          if (pack_x_pitch > 4) {
 130             pack_x_pitch >>= 1;
 131          }
 132
 133          if (pack_y_pitch > 2) {
 134             pack_y_pitch >>= 1;
 135             pack_y_pitch = ALIGN(pack_y_pitch, mt->align_h);
 136          }
 137       }
 138    }
 139
 140    /* The 965's sampler lays cachelines out according to how accesses
 141     * in the texture surfaces run, so they may be "vertical" through
 142     * memory.  As a result, the docs say in Surface Padding Requirements:
 143     * Sampling Engine Surfaces that two extra rows of padding are required.
 144     */
 145    if (mt->target == GL_TEXTURE_CUBE_MAP)
 146       mt->total_height += 2;
 147 }
 148
 149 void
 150 brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
 151 {
 152    switch (mt->target) {
 153    case GL_TEXTURE_CUBE_MAP:
 154       if (intel->gen >= 5) {
 155          /* On Ironlake, cube maps are finally represented as just a series of
 156           * MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated by a
 157           * pitch of qpitch rows, where qpitch is defined by the equation given
 158           * in Volume 1 of the BSpec.
 159           */
 160          brw_miptree_layout_texture_array(intel, mt);
 161          break;
 162       }
 163       assert(mt->physical_depth0 == 6);
 164       /* FALLTHROUGH */
 165
 166    case GL_TEXTURE_3D:
 167       brw_miptree_layout_texture_3d(intel, mt);
 168       break;
 169
 170    case GL_TEXTURE_1D_ARRAY:
 171    case GL_TEXTURE_2D_ARRAY:
 172    case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
 173    case GL_TEXTURE_CUBE_MAP_ARRAY:
 174       brw_miptree_layout_texture_array(intel, mt);
 175       break;
 176
 177    default:
 178       switch (mt->msaa_layout) {
 179       case INTEL_MSAA_LAYOUT_UMS:
 180       case INTEL_MSAA_LAYOUT_CMS:
 181          brw_miptree_layout_texture_array(intel, mt);
 182          break;
 183       case INTEL_MSAA_LAYOUT_NONE:
 184       case INTEL_MSAA_LAYOUT_IMS:
 185          i945_miptree_layout_2d(mt);
 186          break;
 187       }
 188       break;
 189    }
 190    DBG("%s: %dx%dx%d\n", __FUNCTION__,
 191        mt->total_width, mt->total_height, mt->cpp);
 192 }
 193