2 * Copyright 2006 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * \file brw_tex_layout.cpp
29 * Code to lay out images in a mipmap tree.
31 * \author Keith Whitwell <keithw@vmware.com>
32 * \author Michel Dänzer <daenzer@vmware.com>
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
38 #include "main/glformats.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 tr_mode_horizontal_texture_alignment(const struct intel_mipmap_tree
*mt
)
45 unsigned ret_align
, divisor
, multiplier_ys
;
47 /* Values in below tables specifiy the horizontal alignment requirement
48 * in elements for TRMODE_YF surface. An element is defined as a pixel in
49 * uncompressed surface formats, and as a compression block in compressed
50 * surface formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
51 * element is a sample.
53 const unsigned align_1d_yf
[] = {4096, 2048, 1024, 512, 256};
54 const unsigned align_2d_yf
[] = {64, 64, 32, 32, 16};
55 const unsigned align_3d_yf
[] = {16, 8, 8, 8, 4};
57 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
59 /* Alignment computations below assume a power of 2 cpp. */
60 assert (mt
->cpp
>= 1 && mt
->cpp
<= 16 && _mesa_is_pow_two(mt
->cpp
));
61 /* Compute array index. */
62 const int i
= ffs(mt
->cpp
) - 1;
66 case GL_TEXTURE_1D_ARRAY
:
67 ret_align
= align_1d_yf
[i
];
71 case GL_TEXTURE_RECTANGLE
:
72 case GL_TEXTURE_2D_ARRAY
:
73 case GL_TEXTURE_CUBE_MAP
:
74 case GL_TEXTURE_CUBE_MAP_ARRAY
:
75 case GL_TEXTURE_2D_MULTISAMPLE
:
76 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
77 ret_align
= align_2d_yf
[i
];
81 ret_align
= align_3d_yf
[i
];
85 unreachable("not reached");
88 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
89 ret_align
*= multiplier_ys
;
91 assert(_mesa_is_pow_two(mt
->num_samples
));
93 switch (mt
->num_samples
) {
106 return ret_align
/ divisor
;
111 intel_horizontal_texture_alignment_unit(struct brw_context
*brw
,
112 struct intel_mipmap_tree
*mt
,
113 uint32_t layout_flags
)
115 if (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
)
119 * +----------------------------------------------------------------------+
120 * | | alignment unit width ("i") |
121 * | Surface Property |-----------------------------|
122 * | | 915 | 965 | ILK | SNB | IVB |
123 * +----------------------------------------------------------------------+
124 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
125 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
126 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
127 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
128 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
129 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
130 * | All Others | 4 | 4 | 4 | 4 | 4 |
131 * +----------------------------------------------------------------------+
133 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
134 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
137 if (brw
->gen
>= 7 && mt
->format
== MESA_FORMAT_Z_UNORM16
)
144 tr_mode_vertical_texture_alignment(const struct intel_mipmap_tree
*mt
)
146 unsigned ret_align
, divisor
, multiplier_ys
;
148 /* Vertical alignment tables for TRMODE_YF */
149 const unsigned align_2d_yf
[] = {64, 32, 32, 16, 16};
150 const unsigned align_3d_yf
[] = {16, 16, 16, 8, 8};
152 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
154 /* Alignment computations below assume a power of 2 cpp. */
155 assert (mt
->cpp
>= 1 && mt
->cpp
<= 16 && _mesa_is_pow_two(mt
->cpp
)) ;
156 /* Compute array index. */
157 const int i
= ffs(mt
->cpp
) - 1;
161 case GL_TEXTURE_RECTANGLE
:
162 case GL_TEXTURE_2D_ARRAY
:
163 case GL_TEXTURE_CUBE_MAP
:
164 case GL_TEXTURE_CUBE_MAP_ARRAY
:
165 case GL_TEXTURE_2D_MULTISAMPLE
:
166 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
167 ret_align
= align_2d_yf
[i
];
171 ret_align
= align_3d_yf
[i
];
175 case GL_TEXTURE_1D_ARRAY
:
177 unreachable("Unexpected miptree target");
180 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
181 ret_align
*= multiplier_ys
;
183 assert(_mesa_is_pow_two(mt
->num_samples
));
185 switch (mt
->num_samples
) {
197 return ret_align
/ divisor
;
201 intel_vertical_texture_alignment_unit(struct brw_context
*brw
,
202 const struct intel_mipmap_tree
*mt
)
205 * +----------------------------------------------------------------------+
206 * | | alignment unit height ("j") |
207 * | Surface Property |-----------------------------|
208 * | | 915 | 965 | ILK | SNB | IVB |
209 * +----------------------------------------------------------------------+
210 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
211 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
212 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
213 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
214 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
215 * | All Others | 2 | 2 | 2 | * | * |
216 * +----------------------------------------------------------------------+
218 * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
219 * the SURFACE_STATE "Surface Vertical Alignment" field.
222 /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
223 * should always be used, except for stencil buffers, which should be 8.
228 if (mt
->num_samples
> 1)
231 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
234 (base_format
== GL_DEPTH_COMPONENT
||
235 base_format
== GL_DEPTH_STENCIL
)) {
240 /* On Gen7, we prefer a vertical alignment of 4 when possible, because
241 * that allows Y tiled render targets.
243 * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
244 * messages), on p64, under the heading "Surface Vertical Alignment":
246 * Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
247 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
250 * VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
252 if (base_format
== GL_YCBCR_MESA
|| mt
->format
== MESA_FORMAT_RGB_FLOAT32
)
262 gen9_miptree_layout_1d(struct intel_mipmap_tree
*mt
)
265 unsigned width
= mt
->physical_width0
;
266 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
268 /* When this layout is used the horizontal alignment is fixed at 64 and the
269 * hardware ignores the value given in the surface state
271 const unsigned int halign
= 64;
273 mt
->total_height
= mt
->physical_height0
;
276 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
279 intel_miptree_set_level_info(mt
, level
, x
, 0, depth
);
281 img_width
= ALIGN(width
, halign
);
283 mt
->total_width
= MAX2(mt
->total_width
, x
+ img_width
);
287 width
= minify(width
, 1);
292 brw_miptree_layout_2d(struct intel_mipmap_tree
*mt
)
296 unsigned width
= mt
->physical_width0
;
297 unsigned height
= mt
->physical_height0
;
298 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
301 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
303 mt
->total_width
= mt
->physical_width0
;
306 mt
->total_width
= ALIGN_NPOT(mt
->total_width
, bw
);
308 /* May need to adjust width to accommodate the placement of
309 * the 2nd mipmap. This occurs when the alignment
310 * constraints of mipmap placement push the right edge of the
311 * 2nd mipmap out past the width of its parent.
313 if (mt
->first_level
!= mt
->last_level
) {
316 if (mt
->compressed
) {
317 mip1_width
= ALIGN_NPOT(minify(mt
->physical_width0
, 1), mt
->halign
) +
318 ALIGN_NPOT(minify(mt
->physical_width0
, 2), bw
);
320 mip1_width
= ALIGN_NPOT(minify(mt
->physical_width0
, 1), mt
->halign
) +
321 minify(mt
->physical_width0
, 2);
324 if (mip1_width
> mt
->total_width
) {
325 mt
->total_width
= mip1_width
;
329 mt
->total_width
/= bw
;
330 mt
->total_height
= 0;
332 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
335 intel_miptree_set_level_info(mt
, level
, x
, y
, depth
);
337 img_height
= ALIGN_NPOT(height
, mt
->valign
);
341 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
342 /* Compact arrays with separated miplevels */
346 /* Because the images are packed better, the final offset
347 * might not be the maximal one:
349 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
351 /* Layout_below: step right after second mipmap.
353 if (level
== mt
->first_level
+ 1) {
354 x
+= ALIGN_NPOT(width
, mt
->halign
) / bw
;
359 width
= minify(width
, 1);
360 height
= minify(height
, 1);
362 if (mt
->target
== GL_TEXTURE_3D
)
363 depth
= minify(depth
, 1);
368 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
369 const struct intel_mipmap_tree
*mt
,
372 if ((brw
->gen
< 9 && mt
->target
== GL_TEXTURE_3D
) ||
373 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
)) {
374 return ALIGN_NPOT(minify(mt
->physical_width0
, level
), mt
->halign
);
381 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
382 const struct intel_mipmap_tree
*mt
,
386 /* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
387 * effectively end up with a packed qpitch anyway whenever
388 * mt->first_level == mt->last_level.
390 assert(mt
->array_layout
!= ALL_SLICES_AT_EACH_LOD
);
392 /* On Gen9 we can pick whatever qpitch we like as long as it's aligned
393 * to the vertical alignment so we don't need to add any extra rows.
395 unsigned qpitch
= mt
->total_height
;
397 /* If the surface might be used as a stencil buffer or HiZ buffer then
398 * it needs to be a multiple of 8.
400 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
401 if (_mesa_is_depth_or_stencil_format(base_format
))
402 qpitch
= ALIGN(qpitch
, 8);
404 /* 3D textures need to be aligned to the tile height. At this point we
405 * don't know which tiling will be used so let's just align it to 32
407 if (mt
->target
== GL_TEXTURE_3D
)
408 qpitch
= ALIGN(qpitch
, 32);
412 } else if (mt
->target
== GL_TEXTURE_3D
||
413 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
) ||
414 mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
415 return ALIGN_NPOT(minify(mt
->physical_height0
, level
), mt
->valign
);
418 const unsigned h0
= ALIGN_NPOT(mt
->physical_height0
, mt
->valign
);
419 const unsigned h1
= ALIGN_NPOT(minify(mt
->physical_height0
, 1), mt
->valign
);
421 return h0
+ h1
+ (brw
->gen
>= 7 ? 12 : 11) * mt
->valign
;
426 align_cube(struct intel_mipmap_tree
*mt
)
428 /* The 965's sampler lays cachelines out according to how accesses
429 * in the texture surfaces run, so they may be "vertical" through
430 * memory. As a result, the docs say in Surface Padding Requirements:
431 * Sampling Engine Surfaces that two extra rows of padding are required.
433 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
434 mt
->total_height
+= 2;
438 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
439 const struct intel_mipmap_tree
*mt
)
441 /* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
442 * horizontal line. This isn't done for depth/stencil buffers however
443 * because those will be using a tiled layout
446 (mt
->target
== GL_TEXTURE_1D
||
447 mt
->target
== GL_TEXTURE_1D_ARRAY
)) {
448 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
450 if (base_format
!= GL_DEPTH_COMPONENT
&&
451 base_format
!= GL_DEPTH_STENCIL
&&
452 base_format
!= GL_STENCIL_INDEX
)
460 brw_miptree_layout_texture_array(struct brw_context
*brw
,
461 struct intel_mipmap_tree
*mt
)
463 unsigned height
= mt
->physical_height0
;
464 bool layout_1d
= gen9_use_linear_1d_layout(brw
, mt
);
468 gen9_miptree_layout_1d(mt
);
470 brw_miptree_layout_2d(mt
);
474 /* When using the horizontal layout the qpitch specifies the distance in
475 * pixels between array slices. The total_width is forced to be a
476 * multiple of the horizontal alignment in brw_miptree_layout_1d (in
477 * this case it's always 64). The vertical alignment is ignored.
479 mt
->qpitch
= mt
->total_width
;
481 mt
->qpitch
= brw_miptree_get_vertical_slice_pitch(brw
, mt
, 0);
482 /* Unlike previous generations the qpitch is a multiple of the
483 * compressed block size on Gen9 so physical_qpitch matches mt->qpitch.
485 physical_qpitch
= (mt
->compressed
&& brw
->gen
< 9 ? mt
->qpitch
/ 4 :
489 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
491 img_height
= ALIGN_NPOT(height
, mt
->valign
);
493 img_height
/= mt
->valign
;
495 for (unsigned q
= 0; q
< mt
->level
[level
].depth
; q
++) {
496 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
497 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* img_height
);
499 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* physical_qpitch
);
502 height
= minify(height
, 1);
504 if (mt
->array_layout
== ALL_LOD_IN_EACH_SLICE
)
505 mt
->total_height
= physical_qpitch
* mt
->physical_depth0
;
511 brw_miptree_layout_texture_3d(struct brw_context
*brw
,
512 struct intel_mipmap_tree
*mt
)
515 mt
->total_height
= 0;
520 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
522 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
523 unsigned WL
= MAX2(mt
->physical_width0
>> level
, 1);
524 unsigned HL
= MAX2(mt
->physical_height0
>> level
, 1);
525 unsigned DL
= MAX2(mt
->physical_depth0
>> level
, 1);
526 unsigned wL
= ALIGN_NPOT(WL
, mt
->halign
);
527 unsigned hL
= ALIGN_NPOT(HL
, mt
->valign
);
529 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
532 intel_miptree_set_level_info(mt
, level
, 0, 0, DL
);
534 for (unsigned q
= 0; q
< DL
; q
++) {
535 unsigned x
= (q
% (1 << level
)) * wL
;
536 unsigned y
= ysum
+ (q
>> level
) * hL
;
538 intel_miptree_set_image_offset(mt
, level
, q
, x
/ bw
, y
/ bh
);
539 mt
->total_width
= MAX2(mt
->total_width
, (x
+ wL
) / bw
);
540 mt
->total_height
= MAX2(mt
->total_height
, (y
+ hL
) / bh
);
543 ysum
+= ALIGN(DL
, 1 << level
) / (1 << level
) * hL
;
550 * \brief Helper function for intel_miptree_create().
553 brw_miptree_choose_tiling(struct brw_context
*brw
,
554 const struct intel_mipmap_tree
*mt
,
555 uint32_t layout_flags
)
557 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
558 /* The stencil buffer is W tiled. However, we request from the kernel a
559 * non-tiled buffer because the GTT is incapable of W fencing.
561 return I915_TILING_NONE
;
564 /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
565 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
567 /* Some usages may want only one type of tiling, like depth miptrees (Y
568 * tiled), or temporary BOs for uploading data once (linear).
570 switch (layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) {
571 case MIPTREE_LAYOUT_TILING_ANY
:
573 case MIPTREE_LAYOUT_TILING_Y
:
574 return I915_TILING_Y
;
575 case MIPTREE_LAYOUT_TILING_NONE
:
576 return I915_TILING_NONE
;
579 if (mt
->num_samples
> 1) {
580 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
583 * [DevSNB+]: For multi-sample render targets, this field must be
584 * 1. MSRTs can only be tiled.
586 * Our usual reason for preferring X tiling (fast blits using the
587 * blitting engine) doesn't apply to MSAA, since we'll generally be
588 * downsampling or upsampling when blitting between the MSAA buffer
589 * and another buffer, and the blitting engine doesn't support that.
590 * So use Y tiling, since it makes better use of the cache.
592 return I915_TILING_Y
;
595 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
596 if (base_format
== GL_DEPTH_COMPONENT
||
597 base_format
== GL_DEPTH_STENCIL_EXT
)
598 return I915_TILING_Y
;
600 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
601 * in fact it leads to a less efficient use of memory space and bandwidth
602 * due to tile alignment.
604 if (mt
->logical_height0
== 1)
605 return I915_TILING_NONE
;
607 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
609 /* If the width is much smaller than a tile, don't bother tiling. */
610 if (minimum_pitch
< 64)
611 return I915_TILING_NONE
;
613 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
614 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
615 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
616 mt
->total_width
, mt
->total_height
);
617 return I915_TILING_NONE
;
620 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
622 return I915_TILING_X
;
624 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
625 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
627 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
628 * all the way back to 965, but is permitted on Gen7+.
630 if (brw
->gen
< 7 && mt
->cpp
>= 16)
631 return I915_TILING_X
;
633 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
634 * messages), on p64, under the heading "Surface Vertical Alignment":
636 * This field must be set to VALIGN_4 for all tiled Y Render Target
639 * So if the surface is renderable and uses a vertical alignment of 2,
640 * force it to be X tiled. This is somewhat conservative (it's possible
641 * that the client won't ever render to this surface), but it's difficult
642 * to know that ahead of time. And besides, since we use a vertical
643 * alignment of 4 as often as we can, this shouldn't happen very often.
645 if (brw
->gen
== 7 && mt
->valign
== 2 &&
646 brw
->format_supported_as_render_target
[mt
->format
]) {
647 return I915_TILING_X
;
650 return I915_TILING_Y
| I915_TILING_X
;
654 intel_miptree_set_total_width_height(struct brw_context
*brw
,
655 struct intel_mipmap_tree
*mt
)
657 switch (mt
->target
) {
658 case GL_TEXTURE_CUBE_MAP
:
660 /* Gen4 stores cube maps as 3D textures. */
661 assert(mt
->physical_depth0
== 6);
662 brw_miptree_layout_texture_3d(brw
, mt
);
664 /* All other hardware stores cube maps as 2D arrays. */
665 brw_miptree_layout_texture_array(brw
, mt
);
671 brw_miptree_layout_texture_array(brw
, mt
);
673 brw_miptree_layout_texture_3d(brw
, mt
);
676 case GL_TEXTURE_1D_ARRAY
:
677 case GL_TEXTURE_2D_ARRAY
:
678 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
679 case GL_TEXTURE_CUBE_MAP_ARRAY
:
680 brw_miptree_layout_texture_array(brw
, mt
);
684 switch (mt
->msaa_layout
) {
685 case INTEL_MSAA_LAYOUT_UMS
:
686 case INTEL_MSAA_LAYOUT_CMS
:
687 brw_miptree_layout_texture_array(brw
, mt
);
689 case INTEL_MSAA_LAYOUT_NONE
:
690 case INTEL_MSAA_LAYOUT_IMS
:
691 if (gen9_use_linear_1d_layout(brw
, mt
))
692 gen9_miptree_layout_1d(mt
);
694 brw_miptree_layout_2d(mt
);
700 DBG("%s: %dx%dx%d\n", __func__
,
701 mt
->total_width
, mt
->total_height
, mt
->cpp
);
705 intel_miptree_set_alignment(struct brw_context
*brw
,
706 struct intel_mipmap_tree
*mt
,
707 uint32_t layout_flags
)
710 * From the "Alignment Unit Size" section of various specs, namely:
711 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
712 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
713 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
714 * - BSpec (for Ivybridge and slight variations in separate stencil)
716 bool gen6_hiz_or_stencil
= false;
718 if (brw
->gen
== 6 && mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
719 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
720 gen6_hiz_or_stencil
= _mesa_is_depth_or_stencil_format(base_format
);
723 if (gen6_hiz_or_stencil
) {
724 /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
725 * hardware doesn't support multiple mip levels on stencil/hiz.
727 * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
728 * "The hierarchical depth buffer does not support the LOD field"
730 * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
731 * "The stencil depth buffer does not support the LOD field"
733 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
734 /* Stencil uses W tiling, so we force W tiling alignment for the
735 * ALL_SLICES_AT_EACH_LOD miptree layout.
739 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
741 /* Depth uses Y tiling, so we force need Y tiling alignment for the
742 * ALL_SLICES_AT_EACH_LOD miptree layout.
744 mt
->halign
= 128 / mt
->cpp
;
747 } else if (mt
->compressed
) {
748 /* The hardware alignment requirements for compressed textures
749 * happen to match the block boundaries.
751 _mesa_get_format_block_size(mt
->format
, &mt
->halign
, &mt
->valign
);
753 /* On Gen9+ we can pick our own alignment for compressed textures but it
754 * has to be a multiple of the block size. The minimum alignment we can
755 * pick is 4 so we effectively have to align to 4 times the block
762 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
764 mt
->valign
= brw
->gen
>= 7 ? 8 : 4;
765 } else if (brw
->gen
>= 9 && mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
766 mt
->halign
= tr_mode_horizontal_texture_alignment(mt
);
767 mt
->valign
= tr_mode_vertical_texture_alignment(mt
);
770 intel_horizontal_texture_alignment_unit(brw
, mt
, layout_flags
);
771 mt
->valign
= intel_vertical_texture_alignment_unit(brw
, mt
);
776 brw_miptree_layout(struct brw_context
*brw
,
777 struct intel_mipmap_tree
*mt
,
778 uint32_t layout_flags
)
780 mt
->tr_mode
= INTEL_MIPTREE_TRMODE_NONE
;
782 intel_miptree_set_alignment(brw
, mt
, layout_flags
);
783 intel_miptree_set_total_width_height(brw
, mt
);
785 if (!mt
->total_width
|| !mt
->total_height
) {
786 intel_miptree_release(&mt
);
790 /* On Gen9+ the alignment values are expressed in multiples of the block
795 _mesa_get_format_block_size(mt
->format
, &i
, &j
);
800 if ((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0)
801 mt
->tiling
= brw_miptree_choose_tiling(brw
, mt
, layout_flags
);