2 * Copyright 2006 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * \file brw_tex_layout.cpp
29 * Code to lay out images in a mipmap tree.
31 * \author Keith Whitwell <keithw@vmware.com>
32 * \author Michel Dänzer <daenzer@vmware.com>
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
38 #include "main/glformats.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 tr_mode_horizontal_texture_alignment(const struct brw_context
*brw
,
44 const struct intel_mipmap_tree
*mt
)
46 const unsigned *align_yf
, *align_ys
;
47 const unsigned bpp
= _mesa_get_format_bytes(mt
->format
) * 8;
48 unsigned ret_align
, divisor
;
50 /* Horizontal alignment tables for TRMODE_{YF,YS}. Value in below
51 * tables specifies the horizontal alignment requirement in elements
52 * for the surface. An element is defined as a pixel in uncompressed
53 * surface formats, and as a compression block in compressed surface
54 * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
55 * element is a sample.
57 const unsigned align_1d_yf
[] = {4096, 2048, 1024, 512, 256};
58 const unsigned align_1d_ys
[] = {65536, 32768, 16384, 8192, 4096};
59 const unsigned align_2d_yf
[] = {64, 64, 32, 32, 16};
60 const unsigned align_2d_ys
[] = {256, 256, 128, 128, 64};
61 const unsigned align_3d_yf
[] = {16, 8, 8, 8, 4};
62 const unsigned align_3d_ys
[] = {64, 32, 32, 32, 16};
65 /* Alignment computations below assume bpp >= 8 and a power of 2. */
66 assert (bpp
>= 8 && bpp
<= 128 && is_power_of_two(bpp
));
70 case GL_TEXTURE_1D_ARRAY
:
71 align_yf
= align_1d_yf
;
72 align_ys
= align_1d_ys
;
75 case GL_TEXTURE_RECTANGLE
:
76 case GL_TEXTURE_2D_ARRAY
:
77 case GL_TEXTURE_CUBE_MAP
:
78 case GL_TEXTURE_CUBE_MAP_ARRAY
:
79 case GL_TEXTURE_2D_MULTISAMPLE
:
80 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
81 align_yf
= align_2d_yf
;
82 align_ys
= align_2d_ys
;
85 align_yf
= align_3d_yf
;
86 align_ys
= align_3d_ys
;
89 unreachable("not reached");
92 /* Compute array index. */
95 ret_align
= mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
96 align_yf
[i
] : align_ys
[i
];
98 assert(is_power_of_two(mt
->num_samples
));
100 switch (mt
->num_samples
) {
113 return ret_align
/ divisor
;
118 intel_horizontal_texture_alignment_unit(struct brw_context
*brw
,
119 struct intel_mipmap_tree
*mt
)
122 * From the "Alignment Unit Size" section of various specs, namely:
123 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
124 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
125 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
126 * - BSpec (for Ivybridge and slight variations in separate stencil)
128 * +----------------------------------------------------------------------+
129 * | | alignment unit width ("i") |
130 * | Surface Property |-----------------------------|
131 * | | 915 | 965 | ILK | SNB | IVB |
132 * +----------------------------------------------------------------------+
133 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
134 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
135 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
136 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
137 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
138 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
139 * | All Others | 4 | 4 | 4 | 4 | 4 |
140 * +----------------------------------------------------------------------+
142 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
143 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
145 if (_mesa_is_format_compressed(mt
->format
)) {
146 /* The hardware alignment requirements for compressed textures
147 * happen to match the block boundaries.
150 _mesa_get_format_block_size(mt
->format
, &i
, &j
);
152 /* On Gen9+ we can pick our own alignment for compressed textures but it
153 * has to be a multiple of the block size. The minimum alignment we can
154 * pick is 4 so we effectively have to align to 4 times the block
163 if (mt
->format
== MESA_FORMAT_S_UINT8
)
166 if (brw
->gen
>= 9 && mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
167 uint32_t align
= tr_mode_horizontal_texture_alignment(brw
, mt
);
168 /* XY_FAST_COPY_BLT doesn't support horizontal alignment < 32. */
169 return align
< 32 ? 32 : align
;
172 if (brw
->gen
>= 7 && mt
->format
== MESA_FORMAT_Z_UNORM16
)
175 if (brw
->gen
== 8 && mt
->mcs_mt
&& mt
->num_samples
<= 1)
182 intel_vertical_texture_alignment_unit(struct brw_context
*brw
,
183 const struct intel_mipmap_tree
*mt
)
186 * From the "Alignment Unit Size" section of various specs, namely:
187 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
188 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
189 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
190 * - BSpec (for Ivybridge and slight variations in separate stencil)
192 * +----------------------------------------------------------------------+
193 * | | alignment unit height ("j") |
194 * | Surface Property |-----------------------------|
195 * | | 915 | 965 | ILK | SNB | IVB |
196 * +----------------------------------------------------------------------+
197 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
198 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
199 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
200 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
201 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
202 * | All Others | 2 | 2 | 2 | * | * |
203 * +----------------------------------------------------------------------+
205 * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
206 * the SURFACE_STATE "Surface Vertical Alignment" field.
208 if (_mesa_is_format_compressed(mt
->format
))
209 /* See comment above for the horizontal alignment */
210 return brw
->gen
>= 9 ? 16 : 4;
212 if (mt
->format
== MESA_FORMAT_S_UINT8
)
213 return brw
->gen
>= 7 ? 8 : 4;
215 /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
216 * should always be used, except for stencil buffers, which should be 8.
221 if (mt
->num_samples
> 1)
224 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
227 (base_format
== GL_DEPTH_COMPONENT
||
228 base_format
== GL_DEPTH_STENCIL
)) {
233 /* On Gen7, we prefer a vertical alignment of 4 when possible, because
234 * that allows Y tiled render targets.
236 * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
237 * messages), on p64, under the heading "Surface Vertical Alignment":
239 * Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
240 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
243 * VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
245 if (base_format
== GL_YCBCR_MESA
|| mt
->format
== MESA_FORMAT_RGB_FLOAT32
)
255 gen9_miptree_layout_1d(struct intel_mipmap_tree
*mt
)
258 unsigned width
= mt
->physical_width0
;
259 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
261 /* When this layout is used the horizontal alignment is fixed at 64 and the
262 * hardware ignores the value given in the surface state
264 const unsigned int align_w
= 64;
266 mt
->total_height
= mt
->physical_height0
;
269 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
272 intel_miptree_set_level_info(mt
, level
, x
, 0, depth
);
274 img_width
= ALIGN(width
, align_w
);
276 mt
->total_width
= MAX2(mt
->total_width
, x
+ img_width
);
280 width
= minify(width
, 1);
285 brw_miptree_layout_2d(struct intel_mipmap_tree
*mt
)
289 unsigned width
= mt
->physical_width0
;
290 unsigned height
= mt
->physical_height0
;
291 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
294 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
296 mt
->total_width
= mt
->physical_width0
;
298 if (mt
->compressed
) {
299 mt
->total_width
= ALIGN(mt
->physical_width0
, mt
->align_w
);
302 /* May need to adjust width to accommodate the placement of
303 * the 2nd mipmap. This occurs when the alignment
304 * constraints of mipmap placement push the right edge of the
305 * 2nd mipmap out past the width of its parent.
307 if (mt
->first_level
!= mt
->last_level
) {
310 if (mt
->compressed
) {
311 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
312 ALIGN(minify(mt
->physical_width0
, 2), bw
);
314 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
315 minify(mt
->physical_width0
, 2);
318 if (mip1_width
> mt
->total_width
) {
319 mt
->total_width
= mip1_width
;
323 mt
->total_height
= 0;
325 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
328 intel_miptree_set_level_info(mt
, level
, x
, y
, depth
);
330 img_height
= ALIGN(height
, mt
->align_h
);
334 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
335 /* Compact arrays with separated miplevels */
339 /* Because the images are packed better, the final offset
340 * might not be the maximal one:
342 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
344 /* Layout_below: step right after second mipmap.
346 if (level
== mt
->first_level
+ 1) {
347 x
+= ALIGN(width
, mt
->align_w
);
352 width
= minify(width
, 1);
353 height
= minify(height
, 1);
355 if (mt
->target
== GL_TEXTURE_3D
)
356 depth
= minify(depth
, 1);
361 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
362 const struct intel_mipmap_tree
*mt
,
365 assert(brw
->gen
< 9);
367 if (mt
->target
== GL_TEXTURE_3D
||
368 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
)) {
369 return ALIGN(minify(mt
->physical_width0
, level
), mt
->align_w
);
376 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
377 const struct intel_mipmap_tree
*mt
,
381 /* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
382 * effectively end up with a packed qpitch anyway whenever
383 * mt->first_level == mt->last_level.
385 assert(mt
->array_layout
!= ALL_SLICES_AT_EACH_LOD
);
387 /* On Gen9 we can pick whatever qpitch we like as long as it's aligned
388 * to the vertical alignment so we don't need to add any extra rows.
390 unsigned qpitch
= mt
->total_height
;
392 /* If the surface might be used as a stencil buffer or HiZ buffer then
393 * it needs to be a multiple of 8.
395 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
396 if (_mesa_is_depth_or_stencil_format(base_format
))
397 qpitch
= ALIGN(qpitch
, 8);
399 /* 3D textures need to be aligned to the tile height. At this point we
400 * don't know which tiling will be used so let's just align it to 32
402 if (mt
->target
== GL_TEXTURE_3D
)
403 qpitch
= ALIGN(qpitch
, 32);
407 } else if (mt
->target
== GL_TEXTURE_3D
||
408 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
) ||
409 mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
410 return ALIGN(minify(mt
->physical_height0
, level
), mt
->align_h
);
413 const unsigned h0
= ALIGN(mt
->physical_height0
, mt
->align_h
);
414 const unsigned h1
= ALIGN(minify(mt
->physical_height0
, 1), mt
->align_h
);
416 return h0
+ h1
+ (brw
->gen
>= 7 ? 12 : 11) * mt
->align_h
;
421 align_cube(struct intel_mipmap_tree
*mt
)
423 /* The 965's sampler lays cachelines out according to how accesses
424 * in the texture surfaces run, so they may be "vertical" through
425 * memory. As a result, the docs say in Surface Padding Requirements:
426 * Sampling Engine Surfaces that two extra rows of padding are required.
428 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
429 mt
->total_height
+= 2;
433 use_linear_1d_layout(struct brw_context
*brw
,
434 struct intel_mipmap_tree
*mt
)
436 /* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
437 * horizontal line. This isn't done for depth/stencil buffers however
438 * because those will be using a tiled layout
441 (mt
->target
== GL_TEXTURE_1D
||
442 mt
->target
== GL_TEXTURE_1D_ARRAY
)) {
443 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
445 if (base_format
!= GL_DEPTH_COMPONENT
&&
446 base_format
!= GL_DEPTH_STENCIL
&&
447 base_format
!= GL_STENCIL_INDEX
)
455 brw_miptree_layout_texture_array(struct brw_context
*brw
,
456 struct intel_mipmap_tree
*mt
)
458 unsigned height
= mt
->physical_height0
;
459 bool layout_1d
= use_linear_1d_layout(brw
, mt
);
463 gen9_miptree_layout_1d(mt
);
465 brw_miptree_layout_2d(mt
);
469 /* When using the horizontal layout the qpitch specifies the distance in
470 * pixels between array slices. The total_width is forced to be a
471 * multiple of the horizontal alignment in brw_miptree_layout_1d (in
472 * this case it's always 64). The vertical alignment is ignored.
474 mt
->qpitch
= mt
->total_width
;
476 mt
->qpitch
= brw_miptree_get_vertical_slice_pitch(brw
, mt
, 0);
477 /* Unlike previous generations the qpitch is a multiple of the
478 * compressed block size on Gen9 so physical_qpitch matches mt->qpitch.
480 physical_qpitch
= (mt
->compressed
&& brw
->gen
< 9 ? mt
->qpitch
/ 4 :
484 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
486 img_height
= ALIGN(height
, mt
->align_h
);
488 img_height
/= mt
->align_h
;
490 for (int q
= 0; q
< mt
->level
[level
].depth
; q
++) {
491 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
492 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* img_height
);
494 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* physical_qpitch
);
497 height
= minify(height
, 1);
499 if (mt
->array_layout
== ALL_LOD_IN_EACH_SLICE
)
500 mt
->total_height
= physical_qpitch
* mt
->physical_depth0
;
506 brw_miptree_layout_texture_3d(struct brw_context
*brw
,
507 struct intel_mipmap_tree
*mt
)
509 unsigned yscale
= mt
->compressed
? 4 : 1;
512 mt
->total_height
= 0;
515 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
516 unsigned WL
= MAX2(mt
->physical_width0
>> level
, 1);
517 unsigned HL
= MAX2(mt
->physical_height0
>> level
, 1);
518 unsigned DL
= MAX2(mt
->physical_depth0
>> level
, 1);
519 unsigned wL
= ALIGN(WL
, mt
->align_w
);
520 unsigned hL
= ALIGN(HL
, mt
->align_h
);
522 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
525 intel_miptree_set_level_info(mt
, level
, 0, 0, DL
);
527 for (unsigned q
= 0; q
< DL
; q
++) {
528 unsigned x
= (q
% (1 << level
)) * wL
;
529 unsigned y
= ysum
+ (q
>> level
) * hL
;
531 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
/ yscale
);
532 mt
->total_width
= MAX2(mt
->total_width
, x
+ wL
);
533 mt
->total_height
= MAX2(mt
->total_height
, (y
+ hL
) / yscale
);
536 ysum
+= ALIGN(DL
, 1 << level
) / (1 << level
) * hL
;
543 * \brief Helper function for intel_miptree_create().
546 brw_miptree_choose_tiling(struct brw_context
*brw
,
547 enum intel_miptree_tiling_mode requested
,
548 const struct intel_mipmap_tree
*mt
)
550 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
551 /* The stencil buffer is W tiled. However, we request from the kernel a
552 * non-tiled buffer because the GTT is incapable of W fencing.
554 return I915_TILING_NONE
;
557 /* Some usages may want only one type of tiling, like depth miptrees (Y
558 * tiled), or temporary BOs for uploading data once (linear).
561 case INTEL_MIPTREE_TILING_ANY
:
563 case INTEL_MIPTREE_TILING_Y
:
564 return I915_TILING_Y
;
565 case INTEL_MIPTREE_TILING_NONE
:
566 return I915_TILING_NONE
;
569 if (mt
->num_samples
> 1) {
570 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
573 * [DevSNB+]: For multi-sample render targets, this field must be
574 * 1. MSRTs can only be tiled.
576 * Our usual reason for preferring X tiling (fast blits using the
577 * blitting engine) doesn't apply to MSAA, since we'll generally be
578 * downsampling or upsampling when blitting between the MSAA buffer
579 * and another buffer, and the blitting engine doesn't support that.
580 * So use Y tiling, since it makes better use of the cache.
582 return I915_TILING_Y
;
585 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
586 if (base_format
== GL_DEPTH_COMPONENT
||
587 base_format
== GL_DEPTH_STENCIL_EXT
)
588 return I915_TILING_Y
;
590 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
591 * in fact it leads to a less efficient use of memory space and bandwidth
592 * due to tile alignment.
594 if (mt
->logical_height0
== 1)
595 return I915_TILING_NONE
;
597 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
599 /* If the width is much smaller than a tile, don't bother tiling. */
600 if (minimum_pitch
< 64)
601 return I915_TILING_NONE
;
603 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
604 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
605 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
606 mt
->total_width
, mt
->total_height
);
607 return I915_TILING_NONE
;
610 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
612 return I915_TILING_X
;
614 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
615 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
617 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
618 * all the way back to 965, but is permitted on Gen7+.
620 if (brw
->gen
< 7 && mt
->cpp
>= 16)
621 return I915_TILING_X
;
623 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
624 * messages), on p64, under the heading "Surface Vertical Alignment":
626 * This field must be set to VALIGN_4 for all tiled Y Render Target
629 * So if the surface is renderable and uses a vertical alignment of 2,
630 * force it to be X tiled. This is somewhat conservative (it's possible
631 * that the client won't ever render to this surface), but it's difficult
632 * to know that ahead of time. And besides, since we use a vertical
633 * alignment of 4 as often as we can, this shouldn't happen very often.
635 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
636 brw
->format_supported_as_render_target
[mt
->format
]) {
637 return I915_TILING_X
;
640 return I915_TILING_Y
| I915_TILING_X
;
645 brw_miptree_layout(struct brw_context
*brw
,
647 enum intel_miptree_tiling_mode requested
,
648 struct intel_mipmap_tree
*mt
)
650 bool gen6_hiz_or_stencil
= false;
652 mt
->tr_mode
= INTEL_MIPTREE_TRMODE_NONE
;
654 if (brw
->gen
== 6 && mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
655 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
656 gen6_hiz_or_stencil
= _mesa_is_depth_or_stencil_format(base_format
);
659 if (gen6_hiz_or_stencil
) {
660 /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
661 * hardware doesn't support multiple mip levels on stencil/hiz.
663 * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
664 * "The hierarchical depth buffer does not support the LOD field"
666 * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
667 * "The stencil depth buffer does not support the LOD field"
669 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
670 /* Stencil uses W tiling, so we force W tiling alignment for the
671 * ALL_SLICES_AT_EACH_LOD miptree layout.
676 /* Depth uses Y tiling, so we force need Y tiling alignment for the
677 * ALL_SLICES_AT_EACH_LOD miptree layout.
679 mt
->align_w
= 128 / mt
->cpp
;
683 mt
->align_w
= intel_horizontal_texture_alignment_unit(brw
, mt
);
684 mt
->align_h
= intel_vertical_texture_alignment_unit(brw
, mt
);
687 switch (mt
->target
) {
688 case GL_TEXTURE_CUBE_MAP
:
690 /* Gen4 stores cube maps as 3D textures. */
691 assert(mt
->physical_depth0
== 6);
692 brw_miptree_layout_texture_3d(brw
, mt
);
694 /* All other hardware stores cube maps as 2D arrays. */
695 brw_miptree_layout_texture_array(brw
, mt
);
701 brw_miptree_layout_texture_array(brw
, mt
);
703 brw_miptree_layout_texture_3d(brw
, mt
);
706 case GL_TEXTURE_1D_ARRAY
:
707 case GL_TEXTURE_2D_ARRAY
:
708 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
709 case GL_TEXTURE_CUBE_MAP_ARRAY
:
710 brw_miptree_layout_texture_array(brw
, mt
);
714 switch (mt
->msaa_layout
) {
715 case INTEL_MSAA_LAYOUT_UMS
:
716 case INTEL_MSAA_LAYOUT_CMS
:
717 brw_miptree_layout_texture_array(brw
, mt
);
719 case INTEL_MSAA_LAYOUT_NONE
:
720 case INTEL_MSAA_LAYOUT_IMS
:
721 if (use_linear_1d_layout(brw
, mt
))
722 gen9_miptree_layout_1d(mt
);
724 brw_miptree_layout_2d(mt
);
729 DBG("%s: %dx%dx%d\n", __func__
,
730 mt
->total_width
, mt
->total_height
, mt
->cpp
);
732 if (!mt
->total_width
|| !mt
->total_height
) {
733 intel_miptree_release(&mt
);
737 /* On Gen9+ the alignment values are expressed in multiples of the block
742 _mesa_get_format_block_size(mt
->format
, &i
, &j
);
748 mt
->tiling
= brw_miptree_choose_tiling(brw
, requested
, mt
);