src/mesa/drivers/dri/i965/brw_tex_layout.c

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * Copyright © 2006 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /**
  27  * \file brw_tex_layout.cpp
  28  *
  29  * Code to lay out images in a mipmap tree.
  30  *
  31  * \author Keith Whitwell <keithw@vmware.com>
  32  * \author Michel Dänzer <daenzer@vmware.com>
  33  */
  34
  35 #include "intel_mipmap_tree.h"
  36 #include "brw_context.h"
  37 #include "main/macros.h"
  38 #include "main/glformats.h"
  39
  40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
  41
  42 static unsigned int
  43 intel_horizontal_texture_alignment_unit(struct brw_context *brw,
  44                                         struct intel_mipmap_tree *mt)
  45 {
  46    /**
  47     * From the "Alignment Unit Size" section of various specs, namely:
  48     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
  49     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
  50     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
  51     * - BSpec (for Ivybridge and slight variations in separate stencil)
  52     *
  53     * +----------------------------------------------------------------------+
  54     * |                                        | alignment unit width  ("i") |
  55     * | Surface Property                       |-----------------------------|
  56     * |                                        | 915 | 965 | ILK | SNB | IVB |
  57     * +----------------------------------------------------------------------+
  58     * | YUV 4:2:2 format                       |  8  |  4  |  4  |  4  |  4  |
  59     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
  60     * | FXT1  compressed format                |  8  |  8  |  8  |  8  |  8  |
  61     * | Depth Buffer (16-bit)                  |  4  |  4  |  4  |  4  |  8  |
  62     * | Depth Buffer (other)                   |  4  |  4  |  4  |  4  |  4  |
  63     * | Separate Stencil Buffer                | N/A | N/A |  8  |  8  |  8  |
  64     * | All Others                             |  4  |  4  |  4  |  4  |  4  |
  65     * +----------------------------------------------------------------------+
  66     *
  67     * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
  68     * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
  69     */
  70     if (_mesa_is_format_compressed(mt->format)) {
  71        /* The hardware alignment requirements for compressed textures
  72         * happen to match the block boundaries.
  73         */
  74       unsigned int i, j;
  75       _mesa_get_format_block_size(mt->format, &i, &j);
  76       return i;
  77     }
  78
  79    if (mt->format == MESA_FORMAT_S_UINT8)
  80       return 8;
  81
  82    if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
  83       return 8;
  84
  85    if (brw->gen == 8 && mt->mcs_mt && mt->num_samples <= 1)
  86       return 16;
  87
  88    return 4;
  89 }
  90
  91 static unsigned int
  92 intel_vertical_texture_alignment_unit(struct brw_context *brw,
  93                                       mesa_format format, bool multisampled)
  94 {
  95    /**
  96     * From the "Alignment Unit Size" section of various specs, namely:
  97     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
  98     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
  99     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
 100     * - BSpec (for Ivybridge and slight variations in separate stencil)
 101     *
 102     * +----------------------------------------------------------------------+
 103     * |                                        | alignment unit height ("j") |
 104     * | Surface Property                       |-----------------------------|
 105     * |                                        | 915 | 965 | ILK | SNB | IVB |
 106     * +----------------------------------------------------------------------+
 107     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
 108     * | FXT1  compressed format                |  4  |  4  |  4  |  4  |  4  |
 109     * | Depth Buffer                           |  2  |  2  |  2  |  4  |  4  |
 110     * | Separate Stencil Buffer                | N/A | N/A | N/A |  4  |  8  |
 111     * | Multisampled (4x or 8x) render target  | N/A | N/A | N/A |  4  |  4  |
 112     * | All Others                             |  2  |  2  |  2  |  *  |  *  |
 113     * +----------------------------------------------------------------------+
 114     *
 115     * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
 116     * the SURFACE_STATE "Surface Vertical Alignment" field.
 117     */
 118    if (_mesa_is_format_compressed(format))
 119       return 4;
 120
 121    if (format == MESA_FORMAT_S_UINT8)
 122       return brw->gen >= 7 ? 8 : 4;
 123
 124    /* Broadwell only supports VALIGN of 4, 8, and 16.  The BSpec says 4
 125     * should always be used, except for stencil buffers, which should be 8.
 126     */
 127    if (brw->gen >= 8)
 128       return 4;
 129
 130    if (multisampled)
 131       return 4;
 132
 133    GLenum base_format = _mesa_get_format_base_format(format);
 134
 135    if (brw->gen >= 6 &&
 136        (base_format == GL_DEPTH_COMPONENT ||
 137         base_format == GL_DEPTH_STENCIL)) {
 138       return 4;
 139    }
 140
 141    if (brw->gen == 7) {
 142       /* On Gen7, we prefer a vertical alignment of 4 when possible, because
 143        * that allows Y tiled render targets.
 144        *
 145        * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
 146        * messages), on p64, under the heading "Surface Vertical Alignment":
 147        *
 148        *     Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
 149        *     (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
 150        *     (0x190)
 151        *
 152        *     VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
 153        */
 154       if (base_format == GL_YCBCR_MESA || format == MESA_FORMAT_RGB_FLOAT32)
 155          return 2;
 156
 157       return 4;
 158    }
 159
 160    return 2;
 161 }
 162
 163 static void
 164 gen9_miptree_layout_1d(struct intel_mipmap_tree *mt)
 165 {
 166    unsigned x = 0;
 167    unsigned width = mt->physical_width0;
 168    unsigned depth = mt->physical_depth0; /* number of array layers. */
 169
 170    /* When this layout is used the horizontal alignment is fixed at 64 and the
 171     * hardware ignores the value given in the surface state
 172     */
 173    const unsigned int align_w = 64;
 174
 175    mt->total_height = mt->physical_height0;
 176    mt->total_width = 0;
 177
 178    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 179       unsigned img_width;
 180
 181       intel_miptree_set_level_info(mt, level, x, 0, depth);
 182
 183       img_width = ALIGN(width, align_w);
 184
 185       mt->total_width = MAX2(mt->total_width, x + img_width);
 186
 187       x += img_width;
 188
 189       width = minify(width, 1);
 190    }
 191 }
 192
 193 static void
 194 brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 195 {
 196    unsigned x = 0;
 197    unsigned y = 0;
 198    unsigned width = mt->physical_width0;
 199    unsigned height = mt->physical_height0;
 200    unsigned depth = mt->physical_depth0; /* number of array layers. */
 201
 202    mt->total_width = mt->physical_width0;
 203
 204    if (mt->compressed) {
 205        mt->total_width = ALIGN(mt->physical_width0, mt->align_w);
 206    }
 207
 208    /* May need to adjust width to accomodate the placement of
 209     * the 2nd mipmap.  This occurs when the alignment
 210     * constraints of mipmap placement push the right edge of the
 211     * 2nd mipmap out past the width of its parent.
 212     */
 213    if (mt->first_level != mt->last_level) {
 214        unsigned mip1_width;
 215
 216        if (mt->compressed) {
 217           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 218              ALIGN(minify(mt->physical_width0, 2), mt->align_w);
 219        } else {
 220           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 221              minify(mt->physical_width0, 2);
 222        }
 223
 224        if (mip1_width > mt->total_width) {
 225            mt->total_width = mip1_width;
 226        }
 227    }
 228
 229    mt->total_height = 0;
 230
 231    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 232       unsigned img_height;
 233
 234       intel_miptree_set_level_info(mt, level, x, y, depth);
 235
 236       img_height = ALIGN(height, mt->align_h);
 237       if (mt->compressed)
 238          img_height /= mt->align_h;
 239
 240       if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 241          /* Compact arrays with separated miplevels */
 242          img_height *= depth;
 243       }
 244
 245       /* Because the images are packed better, the final offset
 246        * might not be the maximal one:
 247        */
 248       mt->total_height = MAX2(mt->total_height, y + img_height);
 249
 250       /* Layout_below: step right after second mipmap.
 251        */
 252       if (level == mt->first_level + 1) {
 253          x += ALIGN(width, mt->align_w);
 254       } else {
 255          y += img_height;
 256       }
 257
 258       width  = minify(width, 1);
 259       height = minify(height, 1);
 260
 261       if (mt->target == GL_TEXTURE_3D)
 262          depth = minify(depth, 1);
 263    }
 264 }
 265
 266 static void
 267 align_cube(struct intel_mipmap_tree *mt)
 268 {
 269    /* The 965's sampler lays cachelines out according to how accesses
 270     * in the texture surfaces run, so they may be "vertical" through
 271     * memory.  As a result, the docs say in Surface Padding Requirements:
 272     * Sampling Engine Surfaces that two extra rows of padding are required.
 273     */
 274    if (mt->target == GL_TEXTURE_CUBE_MAP)
 275       mt->total_height += 2;
 276 }
 277
 278 static bool
 279 use_linear_1d_layout(struct brw_context *brw,
 280                      struct intel_mipmap_tree *mt)
 281 {
 282    /* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
 283     * horizontal line. This isn't done for depth/stencil buffers however
 284     * because those will be using a tiled layout
 285     */
 286    if (brw->gen >= 9 &&
 287        (mt->target == GL_TEXTURE_1D ||
 288         mt->target == GL_TEXTURE_1D_ARRAY)) {
 289       GLenum base_format = _mesa_get_format_base_format(mt->format);
 290
 291       if (base_format != GL_DEPTH_COMPONENT &&
 292           base_format != GL_DEPTH_STENCIL)
 293          return true;
 294    }
 295
 296    return false;
 297 }
 298
 299 static void
 300 brw_miptree_layout_texture_array(struct brw_context *brw,
 301                                  struct intel_mipmap_tree *mt)
 302 {
 303    int h0, h1;
 304    unsigned height = mt->physical_height0;
 305    bool layout_1d = use_linear_1d_layout(brw, mt);
 306
 307    h0 = ALIGN(mt->physical_height0, mt->align_h);
 308    h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
 309    if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
 310       mt->qpitch = h0;
 311    else
 312       mt->qpitch = (h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->align_h);
 313
 314    int physical_qpitch = mt->compressed ? mt->qpitch / 4 : mt->qpitch;
 315
 316    if (layout_1d)
 317       gen9_miptree_layout_1d(mt);
 318    else
 319       brw_miptree_layout_2d(mt);
 320
 321    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 322       unsigned img_height;
 323       img_height = ALIGN(height, mt->align_h);
 324       if (mt->compressed)
 325          img_height /= mt->align_h;
 326
 327       for (int q = 0; q < mt->level[level].depth; q++) {
 328          if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 329             intel_miptree_set_image_offset(mt, level, q, 0, q * img_height);
 330          } else {
 331             intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch);
 332          }
 333       }
 334       height = minify(height, 1);
 335    }
 336    if (mt->array_layout == ALL_LOD_IN_EACH_SLICE)
 337       mt->total_height = physical_qpitch * mt->physical_depth0;
 338
 339    align_cube(mt);
 340 }
 341
 342 static void
 343 brw_miptree_layout_texture_3d(struct brw_context *brw,
 344                               struct intel_mipmap_tree *mt)
 345 {
 346    unsigned yscale = mt->compressed ? 4 : 1;
 347
 348    mt->total_width = 0;
 349    mt->total_height = 0;
 350
 351    unsigned ysum = 0;
 352    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 353       unsigned WL = MAX2(mt->physical_width0 >> level, 1);
 354       unsigned HL = MAX2(mt->physical_height0 >> level, 1);
 355       unsigned DL = MAX2(mt->physical_depth0 >> level, 1);
 356       unsigned wL = ALIGN(WL, mt->align_w);
 357       unsigned hL = ALIGN(HL, mt->align_h);
 358
 359       if (mt->target == GL_TEXTURE_CUBE_MAP)
 360          DL = 6;
 361
 362       intel_miptree_set_level_info(mt, level, 0, 0, DL);
 363
 364       for (unsigned q = 0; q < DL; q++) {
 365          unsigned x = (q % (1 << level)) * wL;
 366          unsigned y = ysum + (q >> level) * hL;
 367
 368          intel_miptree_set_image_offset(mt, level, q, x, y / yscale);
 369          mt->total_width = MAX2(mt->total_width, x + wL);
 370          mt->total_height = MAX2(mt->total_height, (y + hL) / yscale);
 371       }
 372
 373       ysum += ALIGN(DL, 1 << level) / (1 << level) * hL;
 374    }
 375
 376    align_cube(mt);
 377 }
 378
 379 void
 380 brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
 381 {
 382    bool multisampled = mt->num_samples > 1;
 383    bool gen6_hiz_or_stencil = false;
 384
 385    if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 386       const GLenum base_format = _mesa_get_format_base_format(mt->format);
 387       gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
 388    }
 389
 390    if (gen6_hiz_or_stencil) {
 391       /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
 392        * hardware doesn't support multiple mip levels on stencil/hiz.
 393        *
 394        * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
 395        * "The hierarchical depth buffer does not support the LOD field"
 396        *
 397        * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
 398        * "The stencil depth buffer does not support the LOD field"
 399        */
 400       if (mt->format == MESA_FORMAT_S_UINT8) {
 401          /* Stencil uses W tiling, so we force W tiling alignment for the
 402           * ALL_SLICES_AT_EACH_LOD miptree layout.
 403           */
 404          mt->align_w = 64;
 405          mt->align_h = 64;
 406       } else {
 407          /* Depth uses Y tiling, so we force need Y tiling alignment for the
 408           * ALL_SLICES_AT_EACH_LOD miptree layout.
 409           */
 410          mt->align_w = 128 / mt->cpp;
 411          mt->align_h = 32;
 412       }
 413    } else {
 414       mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
 415       mt->align_h =
 416          intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
 417    }
 418
 419    switch (mt->target) {
 420    case GL_TEXTURE_CUBE_MAP:
 421       if (brw->gen == 4) {
 422          /* Gen4 stores cube maps as 3D textures. */
 423          assert(mt->physical_depth0 == 6);
 424          brw_miptree_layout_texture_3d(brw, mt);
 425       } else {
 426          /* All other hardware stores cube maps as 2D arrays. */
 427          brw_miptree_layout_texture_array(brw, mt);
 428       }
 429       break;
 430
 431    case GL_TEXTURE_3D:
 432       if (brw->gen >= 9)
 433          brw_miptree_layout_texture_array(brw, mt);
 434       else
 435          brw_miptree_layout_texture_3d(brw, mt);
 436       break;
 437
 438    case GL_TEXTURE_1D_ARRAY:
 439    case GL_TEXTURE_2D_ARRAY:
 440    case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
 441    case GL_TEXTURE_CUBE_MAP_ARRAY:
 442       brw_miptree_layout_texture_array(brw, mt);
 443       break;
 444
 445    default:
 446       switch (mt->msaa_layout) {
 447       case INTEL_MSAA_LAYOUT_UMS:
 448       case INTEL_MSAA_LAYOUT_CMS:
 449          brw_miptree_layout_texture_array(brw, mt);
 450          break;
 451       case INTEL_MSAA_LAYOUT_NONE:
 452       case INTEL_MSAA_LAYOUT_IMS:
 453          if (use_linear_1d_layout(brw, mt))
 454             gen9_miptree_layout_1d(mt);
 455          else
 456             brw_miptree_layout_2d(mt);
 457          break;
 458       }
 459       break;
 460    }
 461    DBG("%s: %dx%dx%d\n", __FUNCTION__,
 462        mt->total_width, mt->total_height, mt->cpp);
 463 }
 464