src/mesa/drivers/dri/i965/brw_tex_layout.c

   1 /*
   2  * Copyright 2006 VMware, Inc.
   3  * Copyright © 2006 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /**
  27  * \file brw_tex_layout.cpp
  28  *
  29  * Code to lay out images in a mipmap tree.
  30  *
  31  * \author Keith Whitwell <keithw@vmware.com>
  32  * \author Michel Dänzer <daenzer@vmware.com>
  33  */
  34
  35 #include "intel_mipmap_tree.h"
  36 #include "brw_context.h"
  37 #include "main/macros.h"
  38 #include "main/glformats.h"
  39
  40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
  41
  42 static unsigned int
  43 intel_horizontal_texture_alignment_unit(struct brw_context *brw,
  44                                         struct intel_mipmap_tree *mt)
  45 {
  46    /**
  47     * From the "Alignment Unit Size" section of various specs, namely:
  48     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
  49     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
  50     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
  51     * - BSpec (for Ivybridge and slight variations in separate stencil)
  52     *
  53     * +----------------------------------------------------------------------+
  54     * |                                        | alignment unit width  ("i") |
  55     * | Surface Property                       |-----------------------------|
  56     * |                                        | 915 | 965 | ILK | SNB | IVB |
  57     * +----------------------------------------------------------------------+
  58     * | YUV 4:2:2 format                       |  8  |  4  |  4  |  4  |  4  |
  59     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
  60     * | FXT1  compressed format                |  8  |  8  |  8  |  8  |  8  |
  61     * | Depth Buffer (16-bit)                  |  4  |  4  |  4  |  4  |  8  |
  62     * | Depth Buffer (other)                   |  4  |  4  |  4  |  4  |  4  |
  63     * | Separate Stencil Buffer                | N/A | N/A |  8  |  8  |  8  |
  64     * | All Others                             |  4  |  4  |  4  |  4  |  4  |
  65     * +----------------------------------------------------------------------+
  66     *
  67     * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
  68     * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
  69     */
  70     if (_mesa_is_format_compressed(mt->format)) {
  71        /* The hardware alignment requirements for compressed textures
  72         * happen to match the block boundaries.
  73         */
  74       unsigned int i, j;
  75       _mesa_get_format_block_size(mt->format, &i, &j);
  76       return i;
  77     }
  78
  79    if (mt->format == MESA_FORMAT_S_UINT8)
  80       return 8;
  81
  82    if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
  83       return 8;
  84
  85    if (brw->gen == 8 && mt->mcs_mt && mt->num_samples <= 1)
  86       return 16;
  87
  88    return 4;
  89 }
  90
  91 static unsigned int
  92 intel_vertical_texture_alignment_unit(struct brw_context *brw,
  93                                       mesa_format format, bool multisampled)
  94 {
  95    /**
  96     * From the "Alignment Unit Size" section of various specs, namely:
  97     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
  98     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
  99     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
 100     * - BSpec (for Ivybridge and slight variations in separate stencil)
 101     *
 102     * +----------------------------------------------------------------------+
 103     * |                                        | alignment unit height ("j") |
 104     * | Surface Property                       |-----------------------------|
 105     * |                                        | 915 | 965 | ILK | SNB | IVB |
 106     * +----------------------------------------------------------------------+
 107     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
 108     * | FXT1  compressed format                |  4  |  4  |  4  |  4  |  4  |
 109     * | Depth Buffer                           |  2  |  2  |  2  |  4  |  4  |
 110     * | Separate Stencil Buffer                | N/A | N/A | N/A |  4  |  8  |
 111     * | Multisampled (4x or 8x) render target  | N/A | N/A | N/A |  4  |  4  |
 112     * | All Others                             |  2  |  2  |  2  |  *  |  *  |
 113     * +----------------------------------------------------------------------+
 114     *
 115     * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
 116     * the SURFACE_STATE "Surface Vertical Alignment" field.
 117     */
 118    if (_mesa_is_format_compressed(format))
 119       return 4;
 120
 121    if (format == MESA_FORMAT_S_UINT8)
 122       return brw->gen >= 7 ? 8 : 4;
 123
 124    /* Broadwell only supports VALIGN of 4, 8, and 16.  The BSpec says 4
 125     * should always be used, except for stencil buffers, which should be 8.
 126     */
 127    if (brw->gen >= 8)
 128       return 4;
 129
 130    if (multisampled)
 131       return 4;
 132
 133    GLenum base_format = _mesa_get_format_base_format(format);
 134
 135    if (brw->gen >= 6 &&
 136        (base_format == GL_DEPTH_COMPONENT ||
 137         base_format == GL_DEPTH_STENCIL)) {
 138       return 4;
 139    }
 140
 141    if (brw->gen == 7) {
 142       /* On Gen7, we prefer a vertical alignment of 4 when possible, because
 143        * that allows Y tiled render targets.
 144        *
 145        * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
 146        * messages), on p64, under the heading "Surface Vertical Alignment":
 147        *
 148        *     Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
 149        *     (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
 150        *     (0x190)
 151        *
 152        *     VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
 153        */
 154       if (base_format == GL_YCBCR_MESA || format == MESA_FORMAT_RGB_FLOAT32)
 155          return 2;
 156
 157       return 4;
 158    }
 159
 160    return 2;
 161 }
 162
 163 static void
 164 brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 165 {
 166    unsigned x = 0;
 167    unsigned y = 0;
 168    unsigned width = mt->physical_width0;
 169    unsigned height = mt->physical_height0;
 170    unsigned depth = mt->physical_depth0; /* number of array layers. */
 171
 172    mt->total_width = mt->physical_width0;
 173
 174    if (mt->compressed) {
 175        mt->total_width = ALIGN(mt->physical_width0, mt->align_w);
 176    }
 177
 178    /* May need to adjust width to accomodate the placement of
 179     * the 2nd mipmap.  This occurs when the alignment
 180     * constraints of mipmap placement push the right edge of the
 181     * 2nd mipmap out past the width of its parent.
 182     */
 183    if (mt->first_level != mt->last_level) {
 184        unsigned mip1_width;
 185
 186        if (mt->compressed) {
 187           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 188              ALIGN(minify(mt->physical_width0, 2), mt->align_w);
 189        } else {
 190           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 191              minify(mt->physical_width0, 2);
 192        }
 193
 194        if (mip1_width > mt->total_width) {
 195            mt->total_width = mip1_width;
 196        }
 197    }
 198
 199    mt->total_height = 0;
 200
 201    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 202       unsigned img_height;
 203
 204       intel_miptree_set_level_info(mt, level, x, y, depth);
 205
 206       img_height = ALIGN(height, mt->align_h);
 207       if (mt->compressed)
 208          img_height /= mt->align_h;
 209
 210       if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 211          /* Compact arrays with separated miplevels */
 212          img_height *= depth;
 213       }
 214
 215       /* Because the images are packed better, the final offset
 216        * might not be the maximal one:
 217        */
 218       mt->total_height = MAX2(mt->total_height, y + img_height);
 219
 220       /* Layout_below: step right after second mipmap.
 221        */
 222       if (level == mt->first_level + 1) {
 223          x += ALIGN(width, mt->align_w);
 224       } else {
 225          y += img_height;
 226       }
 227
 228       width  = minify(width, 1);
 229       height = minify(height, 1);
 230
 231       if (mt->target == GL_TEXTURE_3D)
 232          depth = minify(depth, 1);
 233    }
 234 }
 235
 236 static void
 237 align_cube(struct intel_mipmap_tree *mt)
 238 {
 239    /* The 965's sampler lays cachelines out according to how accesses
 240     * in the texture surfaces run, so they may be "vertical" through
 241     * memory.  As a result, the docs say in Surface Padding Requirements:
 242     * Sampling Engine Surfaces that two extra rows of padding are required.
 243     */
 244    if (mt->target == GL_TEXTURE_CUBE_MAP)
 245       mt->total_height += 2;
 246 }
 247
 248 static void
 249 brw_miptree_layout_texture_array(struct brw_context *brw,
 250                                  struct intel_mipmap_tree *mt)
 251 {
 252    int h0, h1;
 253    unsigned height = mt->physical_height0;
 254
 255    h0 = ALIGN(mt->physical_height0, mt->align_h);
 256    h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
 257    if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
 258       mt->qpitch = h0;
 259    else
 260       mt->qpitch = (h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->align_h);
 261
 262    int physical_qpitch = mt->compressed ? mt->qpitch / 4 : mt->qpitch;
 263
 264    brw_miptree_layout_2d(mt);
 265
 266    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 267       unsigned img_height;
 268       img_height = ALIGN(height, mt->align_h);
 269       if (mt->compressed)
 270          img_height /= mt->align_h;
 271
 272       for (int q = 0; q < mt->level[level].depth; q++) {
 273          if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 274             intel_miptree_set_image_offset(mt, level, q, 0, q * img_height);
 275          } else {
 276             intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch);
 277          }
 278       }
 279       height = minify(height, 1);
 280    }
 281    if (mt->array_layout == ALL_LOD_IN_EACH_SLICE)
 282       mt->total_height = physical_qpitch * mt->physical_depth0;
 283
 284    align_cube(mt);
 285 }
 286
 287 static void
 288 brw_miptree_layout_texture_3d(struct brw_context *brw,
 289                               struct intel_mipmap_tree *mt)
 290 {
 291    unsigned yscale = mt->compressed ? 4 : 1;
 292
 293    mt->total_width = 0;
 294    mt->total_height = 0;
 295
 296    unsigned ysum = 0;
 297    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 298       unsigned WL = MAX2(mt->physical_width0 >> level, 1);
 299       unsigned HL = MAX2(mt->physical_height0 >> level, 1);
 300       unsigned DL = MAX2(mt->physical_depth0 >> level, 1);
 301       unsigned wL = ALIGN(WL, mt->align_w);
 302       unsigned hL = ALIGN(HL, mt->align_h);
 303
 304       if (mt->target == GL_TEXTURE_CUBE_MAP)
 305          DL = 6;
 306
 307       intel_miptree_set_level_info(mt, level, 0, 0, DL);
 308
 309       for (unsigned q = 0; q < DL; q++) {
 310          unsigned x = (q % (1 << level)) * wL;
 311          unsigned y = ysum + (q >> level) * hL;
 312
 313          intel_miptree_set_image_offset(mt, level, q, x, y / yscale);
 314          mt->total_width = MAX2(mt->total_width, x + wL);
 315          mt->total_height = MAX2(mt->total_height, (y + hL) / yscale);
 316       }
 317
 318       ysum += ALIGN(DL, 1 << level) / (1 << level) * hL;
 319    }
 320
 321    align_cube(mt);
 322 }
 323
 324 void
 325 brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
 326 {
 327    bool multisampled = mt->num_samples > 1;
 328    bool gen6_hiz_or_stencil = false;
 329
 330    if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
 331       const GLenum base_format = _mesa_get_format_base_format(mt->format);
 332       gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
 333    }
 334
 335    if (gen6_hiz_or_stencil) {
 336       /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
 337        * hardware doesn't support multiple mip levels on stencil/hiz.
 338        *
 339        * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
 340        * "The hierarchical depth buffer does not support the LOD field"
 341        *
 342        * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
 343        * "The stencil depth buffer does not support the LOD field"
 344        */
 345       if (mt->format == MESA_FORMAT_S_UINT8) {
 346          /* Stencil uses W tiling, so we force W tiling alignment for the
 347           * ALL_SLICES_AT_EACH_LOD miptree layout.
 348           */
 349          mt->align_w = 64;
 350          mt->align_h = 64;
 351       } else {
 352          /* Depth uses Y tiling, so we force need Y tiling alignment for the
 353           * ALL_SLICES_AT_EACH_LOD miptree layout.
 354           */
 355          mt->align_w = 128 / mt->cpp;
 356          mt->align_h = 32;
 357       }
 358    } else {
 359       mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
 360       mt->align_h =
 361          intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
 362    }
 363
 364    switch (mt->target) {
 365    case GL_TEXTURE_CUBE_MAP:
 366       if (brw->gen == 4) {
 367          /* Gen4 stores cube maps as 3D textures. */
 368          assert(mt->physical_depth0 == 6);
 369          brw_miptree_layout_texture_3d(brw, mt);
 370       } else {
 371          /* All other hardware stores cube maps as 2D arrays. */
 372          brw_miptree_layout_texture_array(brw, mt);
 373       }
 374       break;
 375
 376    case GL_TEXTURE_3D:
 377       if (brw->gen >= 9)
 378          brw_miptree_layout_texture_array(brw, mt);
 379       else
 380          brw_miptree_layout_texture_3d(brw, mt);
 381       break;
 382
 383    case GL_TEXTURE_1D_ARRAY:
 384    case GL_TEXTURE_2D_ARRAY:
 385    case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
 386    case GL_TEXTURE_CUBE_MAP_ARRAY:
 387       brw_miptree_layout_texture_array(brw, mt);
 388       break;
 389
 390    default:
 391       switch (mt->msaa_layout) {
 392       case INTEL_MSAA_LAYOUT_UMS:
 393       case INTEL_MSAA_LAYOUT_CMS:
 394          brw_miptree_layout_texture_array(brw, mt);
 395          break;
 396       case INTEL_MSAA_LAYOUT_NONE:
 397       case INTEL_MSAA_LAYOUT_IMS:
 398          brw_miptree_layout_2d(mt);
 399          break;
 400       }
 401       break;
 402    }
 403    DBG("%s: %dx%dx%d\n", __FUNCTION__,
 404        mt->total_width, mt->total_height, mt->cpp);
 405 }
 406