2 * Copyright 2006 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * \file brw_tex_layout.cpp
29 * Code to lay out images in a mipmap tree.
31 * \author Keith Whitwell <keithw@vmware.com>
32 * \author Michel Dänzer <daenzer@vmware.com>
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
38 #include "main/glformats.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 intel_horizontal_texture_alignment_unit(struct brw_context
*brw
,
44 struct intel_mipmap_tree
*mt
)
47 * From the "Alignment Unit Size" section of various specs, namely:
48 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
49 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
50 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
51 * - BSpec (for Ivybridge and slight variations in separate stencil)
53 * +----------------------------------------------------------------------+
54 * | | alignment unit width ("i") |
55 * | Surface Property |-----------------------------|
56 * | | 915 | 965 | ILK | SNB | IVB |
57 * +----------------------------------------------------------------------+
58 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
59 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
60 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
61 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
62 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
63 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
64 * | All Others | 4 | 4 | 4 | 4 | 4 |
65 * +----------------------------------------------------------------------+
67 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
68 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
70 if (_mesa_is_format_compressed(mt
->format
)) {
71 /* The hardware alignment requirements for compressed textures
72 * happen to match the block boundaries.
75 _mesa_get_format_block_size(mt
->format
, &i
, &j
);
77 /* On Gen9+ we can pick our own alignment for compressed textures but it
78 * has to be a multiple of the block size. The minimum alignment we can
79 * pick is 4 so we effectively have to align to 4 times the block
88 if (mt
->format
== MESA_FORMAT_S_UINT8
)
91 if (brw
->gen
>= 7 && mt
->format
== MESA_FORMAT_Z_UNORM16
)
94 if (brw
->gen
== 8 && mt
->mcs_mt
&& mt
->num_samples
<= 1)
101 intel_vertical_texture_alignment_unit(struct brw_context
*brw
,
102 mesa_format format
, bool multisampled
)
105 * From the "Alignment Unit Size" section of various specs, namely:
106 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
107 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
108 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
109 * - BSpec (for Ivybridge and slight variations in separate stencil)
111 * +----------------------------------------------------------------------+
112 * | | alignment unit height ("j") |
113 * | Surface Property |-----------------------------|
114 * | | 915 | 965 | ILK | SNB | IVB |
115 * +----------------------------------------------------------------------+
116 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
117 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
118 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
119 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
120 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
121 * | All Others | 2 | 2 | 2 | * | * |
122 * +----------------------------------------------------------------------+
124 * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
125 * the SURFACE_STATE "Surface Vertical Alignment" field.
127 if (_mesa_is_format_compressed(format
))
128 /* See comment above for the horizontal alignment */
129 return brw
->gen
>= 9 ? 16 : 4;
131 if (format
== MESA_FORMAT_S_UINT8
)
132 return brw
->gen
>= 7 ? 8 : 4;
134 /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
135 * should always be used, except for stencil buffers, which should be 8.
143 GLenum base_format
= _mesa_get_format_base_format(format
);
146 (base_format
== GL_DEPTH_COMPONENT
||
147 base_format
== GL_DEPTH_STENCIL
)) {
152 /* On Gen7, we prefer a vertical alignment of 4 when possible, because
153 * that allows Y tiled render targets.
155 * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
156 * messages), on p64, under the heading "Surface Vertical Alignment":
158 * Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
159 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
162 * VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
164 if (base_format
== GL_YCBCR_MESA
|| format
== MESA_FORMAT_RGB_FLOAT32
)
174 gen9_miptree_layout_1d(struct intel_mipmap_tree
*mt
)
177 unsigned width
= mt
->physical_width0
;
178 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
180 /* When this layout is used the horizontal alignment is fixed at 64 and the
181 * hardware ignores the value given in the surface state
183 const unsigned int align_w
= 64;
185 mt
->total_height
= mt
->physical_height0
;
188 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
191 intel_miptree_set_level_info(mt
, level
, x
, 0, depth
);
193 img_width
= ALIGN(width
, align_w
);
195 mt
->total_width
= MAX2(mt
->total_width
, x
+ img_width
);
199 width
= minify(width
, 1);
204 brw_miptree_layout_2d(struct intel_mipmap_tree
*mt
)
208 unsigned width
= mt
->physical_width0
;
209 unsigned height
= mt
->physical_height0
;
210 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
213 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
215 mt
->total_width
= mt
->physical_width0
;
217 if (mt
->compressed
) {
218 mt
->total_width
= ALIGN(mt
->physical_width0
, mt
->align_w
);
221 /* May need to adjust width to accommodate the placement of
222 * the 2nd mipmap. This occurs when the alignment
223 * constraints of mipmap placement push the right edge of the
224 * 2nd mipmap out past the width of its parent.
226 if (mt
->first_level
!= mt
->last_level
) {
229 if (mt
->compressed
) {
230 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
231 ALIGN(minify(mt
->physical_width0
, 2), bw
);
233 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
234 minify(mt
->physical_width0
, 2);
237 if (mip1_width
> mt
->total_width
) {
238 mt
->total_width
= mip1_width
;
242 mt
->total_height
= 0;
244 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
247 intel_miptree_set_level_info(mt
, level
, x
, y
, depth
);
249 img_height
= ALIGN(height
, mt
->align_h
);
253 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
254 /* Compact arrays with separated miplevels */
258 /* Because the images are packed better, the final offset
259 * might not be the maximal one:
261 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
263 /* Layout_below: step right after second mipmap.
265 if (level
== mt
->first_level
+ 1) {
266 x
+= ALIGN(width
, mt
->align_w
);
271 width
= minify(width
, 1);
272 height
= minify(height
, 1);
274 if (mt
->target
== GL_TEXTURE_3D
)
275 depth
= minify(depth
, 1);
280 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
281 const struct intel_mipmap_tree
*mt
,
284 assert(brw
->gen
< 9);
286 if (mt
->target
== GL_TEXTURE_3D
||
287 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
)) {
288 return ALIGN(minify(mt
->physical_width0
, level
), mt
->align_w
);
295 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
296 const struct intel_mipmap_tree
*mt
,
300 /* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
301 * effectively end up with a packed qpitch anyway whenever
302 * mt->first_level == mt->last_level.
304 assert(mt
->array_layout
!= ALL_SLICES_AT_EACH_LOD
);
306 /* On Gen9 we can pick whatever qpitch we like as long as it's aligned
307 * to the vertical alignment so we don't need to add any extra rows.
309 unsigned qpitch
= mt
->total_height
;
311 /* If the surface might be used as a stencil buffer or HiZ buffer then
312 * it needs to be a multiple of 8.
314 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
315 if (_mesa_is_depth_or_stencil_format(base_format
))
316 qpitch
= ALIGN(qpitch
, 8);
318 /* 3D textures need to be aligned to the tile height. At this point we
319 * don't know which tiling will be used so let's just align it to 32
321 if (mt
->target
== GL_TEXTURE_3D
)
322 qpitch
= ALIGN(qpitch
, 32);
326 } else if (mt
->target
== GL_TEXTURE_3D
||
327 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
) ||
328 mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
329 return ALIGN(minify(mt
->physical_height0
, level
), mt
->align_h
);
332 const unsigned h0
= ALIGN(mt
->physical_height0
, mt
->align_h
);
333 const unsigned h1
= ALIGN(minify(mt
->physical_height0
, 1), mt
->align_h
);
335 return h0
+ h1
+ (brw
->gen
>= 7 ? 12 : 11) * mt
->align_h
;
340 align_cube(struct intel_mipmap_tree
*mt
)
342 /* The 965's sampler lays cachelines out according to how accesses
343 * in the texture surfaces run, so they may be "vertical" through
344 * memory. As a result, the docs say in Surface Padding Requirements:
345 * Sampling Engine Surfaces that two extra rows of padding are required.
347 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
348 mt
->total_height
+= 2;
352 use_linear_1d_layout(struct brw_context
*brw
,
353 struct intel_mipmap_tree
*mt
)
355 /* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
356 * horizontal line. This isn't done for depth/stencil buffers however
357 * because those will be using a tiled layout
360 (mt
->target
== GL_TEXTURE_1D
||
361 mt
->target
== GL_TEXTURE_1D_ARRAY
)) {
362 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
364 if (base_format
!= GL_DEPTH_COMPONENT
&&
365 base_format
!= GL_DEPTH_STENCIL
&&
366 base_format
!= GL_STENCIL_INDEX
)
374 brw_miptree_layout_texture_array(struct brw_context
*brw
,
375 struct intel_mipmap_tree
*mt
)
377 unsigned height
= mt
->physical_height0
;
378 bool layout_1d
= use_linear_1d_layout(brw
, mt
);
382 gen9_miptree_layout_1d(mt
);
384 brw_miptree_layout_2d(mt
);
388 /* When using the horizontal layout the qpitch specifies the distance in
389 * pixels between array slices. The total_width is forced to be a
390 * multiple of the horizontal alignment in brw_miptree_layout_1d (in
391 * this case it's always 64). The vertical alignment is ignored.
393 mt
->qpitch
= mt
->total_width
;
395 mt
->qpitch
= brw_miptree_get_vertical_slice_pitch(brw
, mt
, 0);
396 /* Unlike previous generations the qpitch is a multiple of the
397 * compressed block size on Gen9 so physical_qpitch matches mt->qpitch.
399 physical_qpitch
= (mt
->compressed
&& brw
->gen
< 9 ? mt
->qpitch
/ 4 :
403 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
405 img_height
= ALIGN(height
, mt
->align_h
);
407 img_height
/= mt
->align_h
;
409 for (int q
= 0; q
< mt
->level
[level
].depth
; q
++) {
410 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
411 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* img_height
);
413 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* physical_qpitch
);
416 height
= minify(height
, 1);
418 if (mt
->array_layout
== ALL_LOD_IN_EACH_SLICE
)
419 mt
->total_height
= physical_qpitch
* mt
->physical_depth0
;
425 brw_miptree_layout_texture_3d(struct brw_context
*brw
,
426 struct intel_mipmap_tree
*mt
)
428 unsigned yscale
= mt
->compressed
? 4 : 1;
431 mt
->total_height
= 0;
434 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
435 unsigned WL
= MAX2(mt
->physical_width0
>> level
, 1);
436 unsigned HL
= MAX2(mt
->physical_height0
>> level
, 1);
437 unsigned DL
= MAX2(mt
->physical_depth0
>> level
, 1);
438 unsigned wL
= ALIGN(WL
, mt
->align_w
);
439 unsigned hL
= ALIGN(HL
, mt
->align_h
);
441 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
444 intel_miptree_set_level_info(mt
, level
, 0, 0, DL
);
446 for (unsigned q
= 0; q
< DL
; q
++) {
447 unsigned x
= (q
% (1 << level
)) * wL
;
448 unsigned y
= ysum
+ (q
>> level
) * hL
;
450 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
/ yscale
);
451 mt
->total_width
= MAX2(mt
->total_width
, x
+ wL
);
452 mt
->total_height
= MAX2(mt
->total_height
, (y
+ hL
) / yscale
);
455 ysum
+= ALIGN(DL
, 1 << level
) / (1 << level
) * hL
;
462 brw_miptree_layout(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
464 bool multisampled
= mt
->num_samples
> 1;
465 bool gen6_hiz_or_stencil
= false;
467 if (brw
->gen
== 6 && mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
468 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
469 gen6_hiz_or_stencil
= _mesa_is_depth_or_stencil_format(base_format
);
472 if (gen6_hiz_or_stencil
) {
473 /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
474 * hardware doesn't support multiple mip levels on stencil/hiz.
476 * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
477 * "The hierarchical depth buffer does not support the LOD field"
479 * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
480 * "The stencil depth buffer does not support the LOD field"
482 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
483 /* Stencil uses W tiling, so we force W tiling alignment for the
484 * ALL_SLICES_AT_EACH_LOD miptree layout.
489 /* Depth uses Y tiling, so we force need Y tiling alignment for the
490 * ALL_SLICES_AT_EACH_LOD miptree layout.
492 mt
->align_w
= 128 / mt
->cpp
;
496 mt
->align_w
= intel_horizontal_texture_alignment_unit(brw
, mt
);
498 intel_vertical_texture_alignment_unit(brw
, mt
->format
, multisampled
);
501 switch (mt
->target
) {
502 case GL_TEXTURE_CUBE_MAP
:
504 /* Gen4 stores cube maps as 3D textures. */
505 assert(mt
->physical_depth0
== 6);
506 brw_miptree_layout_texture_3d(brw
, mt
);
508 /* All other hardware stores cube maps as 2D arrays. */
509 brw_miptree_layout_texture_array(brw
, mt
);
515 brw_miptree_layout_texture_array(brw
, mt
);
517 brw_miptree_layout_texture_3d(brw
, mt
);
520 case GL_TEXTURE_1D_ARRAY
:
521 case GL_TEXTURE_2D_ARRAY
:
522 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
523 case GL_TEXTURE_CUBE_MAP_ARRAY
:
524 brw_miptree_layout_texture_array(brw
, mt
);
528 switch (mt
->msaa_layout
) {
529 case INTEL_MSAA_LAYOUT_UMS
:
530 case INTEL_MSAA_LAYOUT_CMS
:
531 brw_miptree_layout_texture_array(brw
, mt
);
533 case INTEL_MSAA_LAYOUT_NONE
:
534 case INTEL_MSAA_LAYOUT_IMS
:
535 if (use_linear_1d_layout(brw
, mt
))
536 gen9_miptree_layout_1d(mt
);
538 brw_miptree_layout_2d(mt
);
543 DBG("%s: %dx%dx%d\n", __func__
,
544 mt
->total_width
, mt
->total_height
, mt
->cpp
);
546 /* On Gen9+ the alignment values are expressed in multiples of the block
551 _mesa_get_format_block_size(mt
->format
, &i
, &j
);