2 * Copyright 2006 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * \file brw_tex_layout.cpp
29 * Code to lay out images in a mipmap tree.
31 * \author Keith Whitwell <keithw@vmware.com>
32 * \author Michel Dänzer <daenzer@vmware.com>
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
39 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
42 intel_horizontal_texture_alignment_unit(struct brw_context
*brw
,
46 * From the "Alignment Unit Size" section of various specs, namely:
47 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
48 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
49 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
50 * - BSpec (for Ivybridge and slight variations in separate stencil)
52 * +----------------------------------------------------------------------+
53 * | | alignment unit width ("i") |
54 * | Surface Property |-----------------------------|
55 * | | 915 | 965 | ILK | SNB | IVB |
56 * +----------------------------------------------------------------------+
57 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
58 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
59 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
60 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
61 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
62 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
63 * | All Others | 4 | 4 | 4 | 4 | 4 |
64 * +----------------------------------------------------------------------+
66 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
67 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
69 if (_mesa_is_format_compressed(format
)) {
70 /* The hardware alignment requirements for compressed textures
71 * happen to match the block boundaries.
74 _mesa_get_format_block_size(format
, &i
, &j
);
78 if (format
== MESA_FORMAT_S_UINT8
)
81 if (brw
->gen
>= 7 && format
== MESA_FORMAT_Z_UNORM16
)
88 intel_vertical_texture_alignment_unit(struct brw_context
*brw
,
89 mesa_format format
, bool multisampled
)
92 * From the "Alignment Unit Size" section of various specs, namely:
93 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
94 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
95 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
96 * - BSpec (for Ivybridge and slight variations in separate stencil)
98 * +----------------------------------------------------------------------+
99 * | | alignment unit height ("j") |
100 * | Surface Property |-----------------------------|
101 * | | 915 | 965 | ILK | SNB | IVB |
102 * +----------------------------------------------------------------------+
103 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
104 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
105 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
106 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
107 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
108 * | All Others | 2 | 2 | 2 | * | * |
109 * +----------------------------------------------------------------------+
111 * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
112 * the SURFACE_STATE "Surface Vertical Alignment" field.
114 if (_mesa_is_format_compressed(format
))
117 if (format
== MESA_FORMAT_S_UINT8
)
118 return brw
->gen
>= 7 ? 8 : 4;
120 /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
121 * should always be used, except for stencil buffers, which should be 8.
129 GLenum base_format
= _mesa_get_format_base_format(format
);
132 (base_format
== GL_DEPTH_COMPONENT
||
133 base_format
== GL_DEPTH_STENCIL
)) {
138 /* On Gen7, we prefer a vertical alignment of 4 when possible, because
139 * that allows Y tiled render targets.
141 * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
142 * messages), on p64, under the heading "Surface Vertical Alignment":
144 * Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
145 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
148 * VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
150 if (base_format
== GL_YCBCR_MESA
|| format
== MESA_FORMAT_RGB_FLOAT32
)
160 brw_miptree_layout_2d(struct intel_mipmap_tree
*mt
)
164 unsigned width
= mt
->physical_width0
;
165 unsigned height
= mt
->physical_height0
;
166 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
168 mt
->total_width
= mt
->physical_width0
;
170 if (mt
->compressed
) {
171 mt
->total_width
= ALIGN(mt
->physical_width0
, mt
->align_w
);
174 /* May need to adjust width to accomodate the placement of
175 * the 2nd mipmap. This occurs when the alignment
176 * constraints of mipmap placement push the right edge of the
177 * 2nd mipmap out past the width of its parent.
179 if (mt
->first_level
!= mt
->last_level
) {
182 if (mt
->compressed
) {
183 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
184 ALIGN(minify(mt
->physical_width0
, 2), mt
->align_w
);
186 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
187 minify(mt
->physical_width0
, 2);
190 if (mip1_width
> mt
->total_width
) {
191 mt
->total_width
= mip1_width
;
195 mt
->total_height
= 0;
197 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
200 intel_miptree_set_level_info(mt
, level
, x
, y
, depth
);
202 img_height
= ALIGN(height
, mt
->align_h
);
204 img_height
/= mt
->align_h
;
206 /* Because the images are packed better, the final offset
207 * might not be the maximal one:
209 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
211 /* Layout_below: step right after second mipmap.
213 if (level
== mt
->first_level
+ 1) {
214 x
+= ALIGN(width
, mt
->align_w
);
219 width
= minify(width
, 1);
220 height
= minify(height
, 1);
225 align_cube(struct intel_mipmap_tree
*mt
)
227 /* The 965's sampler lays cachelines out according to how accesses
228 * in the texture surfaces run, so they may be "vertical" through
229 * memory. As a result, the docs say in Surface Padding Requirements:
230 * Sampling Engine Surfaces that two extra rows of padding are required.
232 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
233 mt
->total_height
+= 2;
237 brw_miptree_layout_texture_array(struct brw_context
*brw
,
238 struct intel_mipmap_tree
*mt
)
242 h0
= ALIGN(mt
->physical_height0
, mt
->align_h
);
243 h1
= ALIGN(minify(mt
->physical_height0
, 1), mt
->align_h
);
244 if (mt
->array_spacing_lod0
)
247 mt
->qpitch
= (h0
+ h1
+ (brw
->gen
>= 7 ? 12 : 11) * mt
->align_h
);
249 int physical_qpitch
= mt
->compressed
? mt
->qpitch
/ 4 : mt
->qpitch
;
251 brw_miptree_layout_2d(mt
);
253 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
254 for (int q
= 0; q
< mt
->physical_depth0
; q
++) {
255 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* physical_qpitch
);
258 mt
->total_height
= physical_qpitch
* mt
->physical_depth0
;
264 brw_miptree_layout_texture_3d(struct brw_context
*brw
,
265 struct intel_mipmap_tree
*mt
)
267 unsigned yscale
= mt
->compressed
? 4 : 1;
270 mt
->total_height
= 0;
273 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
274 unsigned WL
= MAX2(mt
->physical_width0
>> level
, 1);
275 unsigned HL
= MAX2(mt
->physical_height0
>> level
, 1);
276 unsigned DL
= MAX2(mt
->physical_depth0
>> level
, 1);
277 unsigned wL
= ALIGN(WL
, mt
->align_w
);
278 unsigned hL
= ALIGN(HL
, mt
->align_h
);
280 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
283 intel_miptree_set_level_info(mt
, level
, 0, 0, DL
);
285 for (unsigned q
= 0; q
< DL
; q
++) {
286 unsigned x
= (q
% (1 << level
)) * wL
;
287 unsigned y
= ysum
+ (q
>> level
) * hL
;
289 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
/ yscale
);
290 mt
->total_width
= MAX2(mt
->total_width
, x
+ wL
);
291 mt
->total_height
= MAX2(mt
->total_height
, (y
+ hL
) / yscale
);
294 ysum
+= ALIGN(DL
, 1 << level
) / (1 << level
) * hL
;
301 brw_miptree_layout(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
303 bool multisampled
= mt
->num_samples
> 1;
304 mt
->align_w
= intel_horizontal_texture_alignment_unit(brw
, mt
->format
);
306 intel_vertical_texture_alignment_unit(brw
, mt
->format
, multisampled
);
308 switch (mt
->target
) {
309 case GL_TEXTURE_CUBE_MAP
:
311 /* Gen4 stores cube maps as 3D textures. */
312 assert(mt
->physical_depth0
== 6);
313 brw_miptree_layout_texture_3d(brw
, mt
);
315 /* All other hardware stores cube maps as 2D arrays. */
316 brw_miptree_layout_texture_array(brw
, mt
);
321 brw_miptree_layout_texture_3d(brw
, mt
);
324 case GL_TEXTURE_1D_ARRAY
:
325 case GL_TEXTURE_2D_ARRAY
:
326 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
327 case GL_TEXTURE_CUBE_MAP_ARRAY
:
328 brw_miptree_layout_texture_array(brw
, mt
);
332 switch (mt
->msaa_layout
) {
333 case INTEL_MSAA_LAYOUT_UMS
:
334 case INTEL_MSAA_LAYOUT_CMS
:
335 brw_miptree_layout_texture_array(brw
, mt
);
337 case INTEL_MSAA_LAYOUT_NONE
:
338 case INTEL_MSAA_LAYOUT_IMS
:
339 brw_miptree_layout_2d(mt
);
344 DBG("%s: %dx%dx%d\n", __FUNCTION__
,
345 mt
->total_width
, mt
->total_height
, mt
->cpp
);