src/mesa/drivers/dri/i965/brw_tex_layout.c

   1 /*
   2  * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
   3  * Copyright © 2006 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 /**
  27  * \file brw_tex_layout.cpp
  28  *
  29  * Code to lay out images in a mipmap tree.
  30  *
  31  * \author Keith Whitwell <keith@tungstengraphics.com>
  32  * \author Michel Dänzer <michel@tungstengraphics.com>
  33  */
  34
  35 #include "intel_mipmap_tree.h"
  36 #include "brw_context.h"
  37 #include "main/macros.h"
  38
  39 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
  40
  41 static unsigned int
  42 intel_horizontal_texture_alignment_unit(struct intel_context *intel,
  43                                        gl_format format)
  44 {
  45    /**
  46     * From the "Alignment Unit Size" section of various specs, namely:
  47     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
  48     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
  49     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
  50     * - BSpec (for Ivybridge and slight variations in separate stencil)
  51     *
  52     * +----------------------------------------------------------------------+
  53     * |                                        | alignment unit width  ("i") |
  54     * | Surface Property                       |-----------------------------|
  55     * |                                        | 915 | 965 | ILK | SNB | IVB |
  56     * +----------------------------------------------------------------------+
  57     * | YUV 4:2:2 format                       |  8  |  4  |  4  |  4  |  4  |
  58     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
  59     * | FXT1  compressed format                |  8  |  8  |  8  |  8  |  8  |
  60     * | Depth Buffer (16-bit)                  |  4  |  4  |  4  |  4  |  8  |
  61     * | Depth Buffer (other)                   |  4  |  4  |  4  |  4  |  4  |
  62     * | Separate Stencil Buffer                | N/A | N/A |  8  |  8  |  8  |
  63     * | All Others                             |  4  |  4  |  4  |  4  |  4  |
  64     * +----------------------------------------------------------------------+
  65     *
  66     * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
  67     * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
  68     */
  69     if (_mesa_is_format_compressed(format)) {
  70        /* The hardware alignment requirements for compressed textures
  71         * happen to match the block boundaries.
  72         */
  73       unsigned int i, j;
  74       _mesa_get_format_block_size(format, &i, &j);
  75       return i;
  76     }
  77
  78    if (format == MESA_FORMAT_S8)
  79       return 8;
  80
  81    /* The depth alignment requirements in the table above are for rendering to
  82     * depth miplevels using the LOD control fields.  We don't use LOD control
  83     * fields, and instead use page offsets plus intra-tile x/y offsets, which
  84     * require that the low 3 bits are zero.  To reduce the number of x/y
  85     * offset workaround blits we do, align the X to 8, which depth texturing
  86     * can handle (sadly, it can't handle 8 in the Y direction).
  87     */
  88    if (intel->gen >= 7 &&
  89        _mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT)
  90       return 8;
  91
  92    return 4;
  93 }
  94
  95 static unsigned int
  96 intel_vertical_texture_alignment_unit(struct intel_context *intel,
  97                                      gl_format format)
  98 {
  99    /**
 100     * From the "Alignment Unit Size" section of various specs, namely:
 101     * - Gen3 Spec: "Memory Data Formats" Volume,         Section 1.20.1.4
 102     * - i965 and G45 PRMs:             Volume 1,         Section 6.17.3.4.
 103     * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
 104     * - BSpec (for Ivybridge and slight variations in separate stencil)
 105     *
 106     * +----------------------------------------------------------------------+
 107     * |                                        | alignment unit height ("j") |
 108     * | Surface Property                       |-----------------------------|
 109     * |                                        | 915 | 965 | ILK | SNB | IVB |
 110     * +----------------------------------------------------------------------+
 111     * | BC1-5 compressed format (DXTn/S3TC)    |  4  |  4  |  4  |  4  |  4  |
 112     * | FXT1  compressed format                |  4  |  4  |  4  |  4  |  4  |
 113     * | Depth Buffer                           |  2  |  2  |  2  |  4  |  4  |
 114     * | Separate Stencil Buffer                | N/A | N/A | N/A |  4  |  8  |
 115     * | Multisampled (4x or 8x) render target  | N/A | N/A | N/A |  4  |  4  |
 116     * | All Others                             |  2  |  2  |  2  |  2  |  2  |
 117     * +----------------------------------------------------------------------+
 118     *
 119     * On SNB+, non-special cases can be overridden by setting the SURFACE_STATE
 120     * "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4.
 121     *
 122     * We currently don't support multisampling.
 123     */
 124    if (_mesa_is_format_compressed(format))
 125       return 4;
 126
 127    if (format == MESA_FORMAT_S8)
 128       return intel->gen >= 7 ? 8 : 4;
 129
 130    GLenum base_format = _mesa_get_format_base_format(format);
 131
 132    if (intel->gen >= 6 &&
 133        (base_format == GL_DEPTH_COMPONENT ||
 134         base_format == GL_DEPTH_STENCIL)) {
 135       return 4;
 136    }
 137
 138    return 2;
 139 }
 140
 141 static void
 142 brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 143 {
 144    unsigned x = 0;
 145    unsigned y = 0;
 146    unsigned width = mt->physical_width0;
 147    unsigned height = mt->physical_height0;
 148    unsigned depth = mt->physical_depth0; /* number of array layers. */
 149
 150    mt->total_width = mt->physical_width0;
 151
 152    if (mt->compressed) {
 153        mt->total_width = ALIGN(mt->physical_width0, mt->align_w);
 154    }
 155
 156    /* May need to adjust width to accomodate the placement of
 157     * the 2nd mipmap.  This occurs when the alignment
 158     * constraints of mipmap placement push the right edge of the
 159     * 2nd mipmap out past the width of its parent.
 160     */
 161    if (mt->first_level != mt->last_level) {
 162        unsigned mip1_width;
 163
 164        if (mt->compressed) {
 165           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 166              ALIGN(minify(mt->physical_width0, 2), mt->align_w);
 167        } else {
 168           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
 169              minify(mt->physical_width0, 2);
 170        }
 171
 172        if (mip1_width > mt->total_width) {
 173            mt->total_width = mip1_width;
 174        }
 175    }
 176
 177    mt->total_height = 0;
 178
 179    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 180       unsigned img_height;
 181
 182       intel_miptree_set_level_info(mt, level, x, y, width,
 183                                    height, depth);
 184
 185       img_height = ALIGN(height, mt->align_h);
 186       if (mt->compressed)
 187          img_height /= mt->align_h;
 188
 189       /* Because the images are packed better, the final offset
 190        * might not be the maximal one:
 191        */
 192       mt->total_height = MAX2(mt->total_height, y + img_height);
 193
 194       /* Layout_below: step right after second mipmap.
 195        */
 196       if (level == mt->first_level + 1) {
 197          x += ALIGN(width, mt->align_w);
 198       } else {
 199          y += img_height;
 200       }
 201
 202       width  = minify(width, 1);
 203       height = minify(height, 1);
 204    }
 205 }
 206
 207 static void
 208 brw_miptree_layout_texture_array(struct intel_context *intel,
 209                                  struct intel_mipmap_tree *mt)
 210 {
 211    unsigned qpitch = 0;
 212    int h0, h1;
 213
 214    h0 = ALIGN(mt->physical_height0, mt->align_h);
 215    h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
 216    if (mt->array_spacing_lod0)
 217       qpitch = h0;
 218    else
 219       qpitch = (h0 + h1 + (intel->gen >= 7 ? 12 : 11) * mt->align_h);
 220    if (mt->compressed)
 221       qpitch /= 4;
 222
 223    brw_miptree_layout_2d(mt);
 224
 225    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 226       for (int q = 0; q < mt->physical_depth0; q++) {
 227          intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
 228       }
 229    }
 230    mt->total_height = qpitch * mt->physical_depth0;
 231 }
 232
 233 static void
 234 brw_miptree_layout_texture_3d(struct intel_context *intel,
 235                               struct intel_mipmap_tree *mt)
 236 {
 237    unsigned width  = mt->physical_width0;
 238    unsigned height = mt->physical_height0;
 239    unsigned depth = mt->physical_depth0;
 240    unsigned pack_x_pitch, pack_x_nr;
 241    unsigned pack_y_pitch;
 242
 243    mt->total_height = 0;
 244
 245    if (mt->compressed) {
 246        mt->total_width = ALIGN(width, mt->align_w);
 247        pack_y_pitch = (height + 3) / 4;
 248    } else {
 249       mt->total_width = mt->physical_width0;
 250       pack_y_pitch = ALIGN(mt->physical_height0, mt->align_h);
 251    }
 252
 253    pack_x_pitch = width;
 254    pack_x_nr = 1;
 255
 256    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
 257       int x = 0;
 258       int y = 0;
 259
 260       intel_miptree_set_level_info(mt, level,
 261                                    0, mt->total_height,
 262                                    width, height, depth);
 263
 264       for (int q = 0; q < depth; /* empty */) {
 265          for (int j = 0; j < pack_x_nr && q < depth; j++, q++) {
 266             intel_miptree_set_image_offset(mt, level, q, x, y);
 267             x += pack_x_pitch;
 268          }
 269          if (x > mt->total_width)
 270             mt->total_width = x;
 271
 272          x = 0;
 273          y += pack_y_pitch;
 274       }
 275
 276       mt->total_height += y;
 277       width  = minify(width, 1);
 278       height = minify(height, 1);
 279       if (mt->target == GL_TEXTURE_3D)
 280          depth = minify(depth, 1);
 281
 282       if (mt->compressed) {
 283          pack_y_pitch = (height + 3) / 4;
 284
 285          if (pack_x_pitch > ALIGN(width, mt->align_w)) {
 286             pack_x_pitch = ALIGN(width, mt->align_w);
 287             pack_x_nr <<= 1;
 288          }
 289       } else {
 290          pack_x_nr <<= 1;
 291          if (pack_x_pitch > 4) {
 292             pack_x_pitch >>= 1;
 293          }
 294
 295          if (pack_y_pitch > 2) {
 296             pack_y_pitch >>= 1;
 297             pack_y_pitch = ALIGN(pack_y_pitch, mt->align_h);
 298          }
 299       }
 300    }
 301
 302    /* The 965's sampler lays cachelines out according to how accesses
 303     * in the texture surfaces run, so they may be "vertical" through
 304     * memory.  As a result, the docs say in Surface Padding Requirements:
 305     * Sampling Engine Surfaces that two extra rows of padding are required.
 306     */
 307    if (mt->target == GL_TEXTURE_CUBE_MAP)
 308       mt->total_height += 2;
 309 }
 310
 311 void
 312 brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
 313 {
 314    mt->align_w = intel_horizontal_texture_alignment_unit(intel, mt->format);
 315    mt->align_h = intel_vertical_texture_alignment_unit(intel, mt->format);
 316
 317    switch (mt->target) {
 318    case GL_TEXTURE_CUBE_MAP:
 319       if (intel->gen == 4) {
 320          /* Gen4 stores cube maps as 3D textures. */
 321          assert(mt->physical_depth0 == 6);
 322          brw_miptree_layout_texture_3d(intel, mt);
 323       } else {
 324          /* All other hardware stores cube maps as 2D arrays. */
 325          brw_miptree_layout_texture_array(intel, mt);
 326       }
 327       break;
 328
 329    case GL_TEXTURE_3D:
 330       brw_miptree_layout_texture_3d(intel, mt);
 331       break;
 332
 333    case GL_TEXTURE_1D_ARRAY:
 334    case GL_TEXTURE_2D_ARRAY:
 335    case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
 336    case GL_TEXTURE_CUBE_MAP_ARRAY:
 337       brw_miptree_layout_texture_array(intel, mt);
 338       break;
 339
 340    default:
 341       switch (mt->msaa_layout) {
 342       case INTEL_MSAA_LAYOUT_UMS:
 343       case INTEL_MSAA_LAYOUT_CMS:
 344          brw_miptree_layout_texture_array(intel, mt);
 345          break;
 346       case INTEL_MSAA_LAYOUT_NONE:
 347       case INTEL_MSAA_LAYOUT_IMS:
 348          brw_miptree_layout_2d(mt);
 349          break;
 350       }
 351       break;
 352    }
 353    DBG("%s: %dx%dx%d\n", __FUNCTION__,
 354        mt->total_width, mt->total_height, mt->cpp);
 355 }
 356