2 * Copyright 2006 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * \file brw_tex_layout.cpp
29 * Code to lay out images in a mipmap tree.
31 * \author Keith Whitwell <keithw@vmware.com>
32 * \author Michel Dänzer <daenzer@vmware.com>
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
38 #include "main/glformats.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 intel_horizontal_texture_alignment_unit(struct brw_context
*brw
,
44 struct intel_mipmap_tree
*mt
,
45 uint32_t layout_flags
)
47 if (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
)
51 * +----------------------------------------------------------------------+
52 * | | alignment unit width ("i") |
53 * | Surface Property |-----------------------------|
54 * | | 915 | 965 | ILK | SNB | IVB |
55 * +----------------------------------------------------------------------+
56 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
57 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
58 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
59 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
60 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
61 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
62 * | All Others | 4 | 4 | 4 | 4 | 4 |
63 * +----------------------------------------------------------------------+
65 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
66 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
69 if (brw
->gen
>= 7 && mt
->format
== MESA_FORMAT_Z_UNORM16
)
76 intel_vertical_texture_alignment_unit(struct brw_context
*brw
,
77 const struct intel_mipmap_tree
*mt
)
80 * +----------------------------------------------------------------------+
81 * | | alignment unit height ("j") |
82 * | Surface Property |-----------------------------|
83 * | | 915 | 965 | ILK | SNB | IVB |
84 * +----------------------------------------------------------------------+
85 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
86 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
87 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
88 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
89 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
90 * | All Others | 2 | 2 | 2 | * | * |
91 * +----------------------------------------------------------------------+
93 * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
94 * the SURFACE_STATE "Surface Vertical Alignment" field.
97 /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
98 * should always be used, except for stencil buffers, which should be 8.
103 if (mt
->num_samples
> 1)
106 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
109 (base_format
== GL_DEPTH_COMPONENT
||
110 base_format
== GL_DEPTH_STENCIL
)) {
115 /* On Gen7, we prefer a vertical alignment of 4 when possible, because
116 * that allows Y tiled render targets.
118 * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
119 * messages), on p64, under the heading "Surface Vertical Alignment":
121 * Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
122 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
125 * VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
127 if (base_format
== GL_YCBCR_MESA
|| mt
->format
== MESA_FORMAT_RGB_FLOAT32
)
137 gen9_miptree_layout_1d(struct intel_mipmap_tree
*mt
)
140 unsigned width
= mt
->physical_width0
;
141 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
143 /* When this layout is used the horizontal alignment is fixed at 64 and the
144 * hardware ignores the value given in the surface state
146 const unsigned int halign
= 64;
148 mt
->total_height
= mt
->physical_height0
;
151 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
154 intel_miptree_set_level_info(mt
, level
, x
, 0, depth
);
156 img_width
= ALIGN(width
, halign
);
158 mt
->total_width
= MAX2(mt
->total_width
, x
+ img_width
);
162 width
= minify(width
, 1);
167 brw_miptree_layout_2d(struct intel_mipmap_tree
*mt
)
171 unsigned width
= mt
->physical_width0
;
172 unsigned height
= mt
->physical_height0
;
173 /* Number of layers of array texture or slices of 3d texture (gen9+). */
174 unsigned depth
= mt
->physical_depth0
;
177 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
179 mt
->total_width
= mt
->physical_width0
;
180 mt
->total_width
= ALIGN_NPOT(mt
->total_width
, bw
);
182 /* May need to adjust width to accommodate the placement of
183 * the 2nd mipmap. This occurs when the alignment
184 * constraints of mipmap placement push the right edge of the
185 * 2nd mipmap out past the width of its parent.
187 if (mt
->first_level
!= mt
->last_level
) {
190 mip1_width
= ALIGN_NPOT(minify(mt
->physical_width0
, 1), mt
->halign
) +
191 ALIGN_NPOT(minify(mt
->physical_width0
, 2), bw
);
193 if (mip1_width
> mt
->total_width
)
194 mt
->total_width
= mip1_width
;
197 mt
->total_width
/= bw
;
198 mt
->total_height
= 0;
200 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
203 intel_miptree_set_level_info(mt
, level
, x
, y
, depth
);
205 img_height
= ALIGN_NPOT(height
, mt
->valign
);
208 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
209 /* Compact arrays with separated miplevels */
213 /* Because the images are packed better, the final offset
214 * might not be the maximal one:
216 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
218 /* Layout_below: step right after second mipmap.
220 * For Sandy Bridge HiZ and stencil, we always step down.
222 if (level
== mt
->first_level
+ 1) {
223 x
+= ALIGN_NPOT(width
, mt
->halign
) / bw
;
228 width
= minify(width
, 1);
229 height
= minify(height
, 1);
231 if (mt
->target
== GL_TEXTURE_3D
)
232 depth
= minify(depth
, 1);
237 brw_miptree_layout_gen6_hiz_stencil(struct intel_mipmap_tree
*mt
)
241 unsigned width
= mt
->physical_width0
;
242 unsigned height
= mt
->physical_height0
;
243 /* Number of layers of array texture. */
244 unsigned depth
= mt
->physical_depth0
;
245 unsigned tile_width
, tile_height
, bw
, bh
;
247 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
253 assert(_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
||
254 _mesa_get_format_base_format(mt
->format
) == GL_DEPTH_STENCIL
);
255 /* Each 128-bit HiZ block corresponds to a region of of 8x4 depth
256 * samples. Each cache line in the Y-Tiled HiZ image contains 2x2 HiZ
257 * blocks. Therefore, each Y-tiled cache line corresponds to an 16x8
258 * region in the depth surface. Since we're representing it as
259 * RGBA_FLOAT32, the miptree calculations will think that each cache
260 * line is 1x4 pixels. Therefore, we need a scale-down factor of 16x2
261 * and a vertical alignment of 2.
267 tile_width
= 128 / mt
->cpp
;
272 mt
->total_height
= 0;
274 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
275 intel_miptree_set_level_info(
277 mt
->target
== GL_TEXTURE_3D
? minify(depth
, level
) : depth
);
279 const unsigned img_width
= ALIGN(DIV_ROUND_UP(width
, bw
), mt
->halign
);
280 const unsigned img_height
=
281 ALIGN(DIV_ROUND_UP(height
, bh
), mt
->valign
) * depth
;
283 mt
->total_width
= MAX2(mt
->total_width
, x
+ img_width
);
284 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
286 if (level
== mt
->first_level
) {
287 y
+= ALIGN(img_height
, tile_height
);
289 x
+= ALIGN(img_width
, tile_width
);
292 /* We only minify the width. We want qpitch to match for all miplevels
293 * because the hardware doesn't know we aren't on LOD0.
295 width
= minify(width
, 1);
300 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
301 const struct intel_mipmap_tree
*mt
,
304 if ((brw
->gen
< 9 && mt
->target
== GL_TEXTURE_3D
) ||
305 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
)) {
306 return ALIGN_NPOT(minify(mt
->physical_width0
, level
), mt
->halign
);
313 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
314 const struct intel_mipmap_tree
*mt
,
317 assert(mt
->array_layout
!= GEN6_HIZ_STENCIL
|| brw
->gen
== 6);
320 /* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
321 * effectively end up with a packed qpitch anyway whenever
322 * mt->first_level == mt->last_level.
324 assert(mt
->array_layout
!= ALL_SLICES_AT_EACH_LOD
);
326 /* On Gen9 we can pick whatever qpitch we like as long as it's aligned
327 * to the vertical alignment so we don't need to add any extra rows.
329 unsigned qpitch
= mt
->total_height
;
331 /* If the surface might be used as a stencil buffer or HiZ buffer then
332 * it needs to be a multiple of 8.
334 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
335 if (_mesa_is_depth_or_stencil_format(base_format
))
336 qpitch
= ALIGN(qpitch
, 8);
338 /* 3D textures need to be aligned to the tile height. At this point we
339 * don't know which tiling will be used so let's just align it to 32
341 if (mt
->target
== GL_TEXTURE_3D
)
342 qpitch
= ALIGN(qpitch
, 32);
346 } else if (mt
->target
== GL_TEXTURE_3D
||
347 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
) ||
348 mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
349 return ALIGN_NPOT(minify(mt
->physical_height0
, level
), mt
->valign
);
351 } else if (mt
->array_layout
== GEN6_HIZ_STENCIL
) {
352 /* For HiZ and stencil on Sandy Bridge, we don't minify the height. */
353 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
354 return ALIGN(mt
->physical_height0
, mt
->valign
);
356 /* HiZ has a vertical scale factor of 2. */
357 return ALIGN(DIV_ROUND_UP(mt
->physical_height0
, 2), mt
->valign
);
361 const unsigned h0
= ALIGN_NPOT(mt
->physical_height0
, mt
->valign
);
362 const unsigned h1
= ALIGN_NPOT(minify(mt
->physical_height0
, 1), mt
->valign
);
364 return h0
+ h1
+ (brw
->gen
>= 7 ? 12 : 11) * mt
->valign
;
369 align_cube(struct intel_mipmap_tree
*mt
)
371 /* The 965's sampler lays cachelines out according to how accesses
372 * in the texture surfaces run, so they may be "vertical" through
373 * memory. As a result, the docs say in Surface Padding Requirements:
374 * Sampling Engine Surfaces that two extra rows of padding are required.
376 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
377 mt
->total_height
+= 2;
381 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
382 const struct intel_mipmap_tree
*mt
)
384 /* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
385 * horizontal line. This isn't done for depth/stencil buffers however
386 * because those will be using a tiled layout
389 (mt
->target
== GL_TEXTURE_1D
||
390 mt
->target
== GL_TEXTURE_1D_ARRAY
)) {
391 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
393 if (base_format
!= GL_DEPTH_COMPONENT
&&
394 base_format
!= GL_DEPTH_STENCIL
&&
395 base_format
!= GL_STENCIL_INDEX
)
403 brw_miptree_layout_texture_array(struct brw_context
*brw
,
404 struct intel_mipmap_tree
*mt
)
406 unsigned height
= mt
->physical_height0
;
407 bool layout_1d
= gen9_use_linear_1d_layout(brw
, mt
);
411 gen9_miptree_layout_1d(mt
);
412 else if (mt
->array_layout
== GEN6_HIZ_STENCIL
)
413 brw_miptree_layout_gen6_hiz_stencil(mt
);
415 brw_miptree_layout_2d(mt
);
419 /* When using the horizontal layout the qpitch specifies the distance in
420 * pixels between array slices. The total_width is forced to be a
421 * multiple of the horizontal alignment in brw_miptree_layout_1d (in
422 * this case it's always 64). The vertical alignment is ignored.
424 mt
->qpitch
= mt
->total_width
;
426 mt
->qpitch
= brw_miptree_get_vertical_slice_pitch(brw
, mt
, 0);
427 /* Unlike previous generations the qpitch is a multiple of the
428 * compressed block size on Gen9 so physical_qpitch matches mt->qpitch.
430 physical_qpitch
= (mt
->compressed
&& brw
->gen
< 9 ? mt
->qpitch
/ 4 :
434 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
436 img_height
= ALIGN_NPOT(height
, mt
->valign
);
438 img_height
/= mt
->valign
;
440 for (unsigned q
= 0; q
< mt
->level
[level
].depth
; q
++) {
441 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
442 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* img_height
);
444 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* physical_qpitch
);
447 height
= minify(height
, 1);
449 if (mt
->array_layout
== ALL_LOD_IN_EACH_SLICE
)
450 mt
->total_height
= physical_qpitch
* mt
->physical_depth0
;
456 brw_miptree_layout_texture_3d(struct brw_context
*brw
,
457 struct intel_mipmap_tree
*mt
)
460 mt
->total_height
= 0;
465 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
467 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
468 unsigned WL
= MAX2(mt
->physical_width0
>> level
, 1);
469 unsigned HL
= MAX2(mt
->physical_height0
>> level
, 1);
470 unsigned DL
= MAX2(mt
->physical_depth0
>> level
, 1);
471 unsigned wL
= ALIGN_NPOT(WL
, mt
->halign
);
472 unsigned hL
= ALIGN_NPOT(HL
, mt
->valign
);
474 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
477 intel_miptree_set_level_info(mt
, level
, 0, 0, DL
);
479 for (unsigned q
= 0; q
< DL
; q
++) {
480 unsigned x
= (q
% (1 << level
)) * wL
;
481 unsigned y
= ysum
+ (q
>> level
) * hL
;
483 intel_miptree_set_image_offset(mt
, level
, q
, x
/ bw
, y
/ bh
);
484 mt
->total_width
= MAX2(mt
->total_width
, (x
+ wL
) / bw
);
485 mt
->total_height
= MAX2(mt
->total_height
, (y
+ hL
) / bh
);
488 ysum
+= ALIGN(DL
, 1 << level
) / (1 << level
) * hL
;
495 * \brief Helper function for intel_miptree_create().
498 brw_miptree_choose_tiling(struct brw_context
*brw
,
499 const struct intel_mipmap_tree
*mt
,
500 uint32_t layout_flags
)
502 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
503 /* The stencil buffer is W tiled. However, we request from the kernel a
504 * non-tiled buffer because the GTT is incapable of W fencing.
506 return I915_TILING_NONE
;
509 /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
510 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
512 /* Some usages may want only one type of tiling, like depth miptrees (Y
513 * tiled), or temporary BOs for uploading data once (linear).
515 switch (layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) {
516 case MIPTREE_LAYOUT_TILING_ANY
:
518 case MIPTREE_LAYOUT_TILING_Y
:
519 return I915_TILING_Y
;
520 case MIPTREE_LAYOUT_TILING_NONE
:
521 return I915_TILING_NONE
;
524 if (mt
->num_samples
> 1) {
525 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
528 * [DevSNB+]: For multi-sample render targets, this field must be
529 * 1. MSRTs can only be tiled.
531 * Our usual reason for preferring X tiling (fast blits using the
532 * blitting engine) doesn't apply to MSAA, since we'll generally be
533 * downsampling or upsampling when blitting between the MSAA buffer
534 * and another buffer, and the blitting engine doesn't support that.
535 * So use Y tiling, since it makes better use of the cache.
537 return I915_TILING_Y
;
540 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
541 if (base_format
== GL_DEPTH_COMPONENT
||
542 base_format
== GL_DEPTH_STENCIL_EXT
)
543 return I915_TILING_Y
;
545 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
546 * in fact it leads to a less efficient use of memory space and bandwidth
547 * due to tile alignment.
549 if (mt
->logical_height0
== 1)
550 return I915_TILING_NONE
;
552 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
554 /* If the width is much smaller than a tile, don't bother tiling. */
555 if (minimum_pitch
< 64)
556 return I915_TILING_NONE
;
558 if (ALIGN(minimum_pitch
, 512) >= 32768) {
559 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
560 mt
->total_width
, mt
->total_height
);
561 return I915_TILING_NONE
;
564 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
566 return I915_TILING_X
;
568 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
569 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
571 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
572 * all the way back to 965, but is permitted on Gen7+.
574 if (brw
->gen
< 7 && mt
->cpp
>= 16)
575 return I915_TILING_X
;
577 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
578 * messages), on p64, under the heading "Surface Vertical Alignment":
580 * This field must be set to VALIGN_4 for all tiled Y Render Target
583 * So if the surface is renderable and uses a vertical alignment of 2,
584 * force it to be X tiled. This is somewhat conservative (it's possible
585 * that the client won't ever render to this surface), but it's difficult
586 * to know that ahead of time. And besides, since we use a vertical
587 * alignment of 4 as often as we can, this shouldn't happen very often.
589 if (brw
->gen
== 7 && mt
->valign
== 2 &&
590 brw
->mesa_format_supports_render
[mt
->format
]) {
591 return I915_TILING_X
;
594 return I915_TILING_Y
| I915_TILING_X
;
598 intel_miptree_set_total_width_height(struct brw_context
*brw
,
599 struct intel_mipmap_tree
*mt
)
601 switch (mt
->target
) {
602 case GL_TEXTURE_CUBE_MAP
:
604 /* Gen4 stores cube maps as 3D textures. */
605 assert(mt
->physical_depth0
== 6);
606 brw_miptree_layout_texture_3d(brw
, mt
);
608 /* All other hardware stores cube maps as 2D arrays. */
609 brw_miptree_layout_texture_array(brw
, mt
);
615 brw_miptree_layout_texture_array(brw
, mt
);
617 brw_miptree_layout_texture_3d(brw
, mt
);
620 case GL_TEXTURE_1D_ARRAY
:
621 case GL_TEXTURE_2D_ARRAY
:
622 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
623 case GL_TEXTURE_CUBE_MAP_ARRAY
:
624 brw_miptree_layout_texture_array(brw
, mt
);
628 switch (mt
->msaa_layout
) {
629 case INTEL_MSAA_LAYOUT_UMS
:
630 case INTEL_MSAA_LAYOUT_CMS
:
631 brw_miptree_layout_texture_array(brw
, mt
);
633 case INTEL_MSAA_LAYOUT_NONE
:
634 case INTEL_MSAA_LAYOUT_IMS
:
635 if (gen9_use_linear_1d_layout(brw
, mt
))
636 gen9_miptree_layout_1d(mt
);
637 else if (mt
->array_layout
== GEN6_HIZ_STENCIL
)
638 brw_miptree_layout_gen6_hiz_stencil(mt
);
640 brw_miptree_layout_2d(mt
);
646 DBG("%s: %dx%dx%d\n", __func__
,
647 mt
->total_width
, mt
->total_height
, mt
->cpp
);
651 intel_miptree_set_alignment(struct brw_context
*brw
,
652 struct intel_mipmap_tree
*mt
,
653 uint32_t layout_flags
)
656 * From the "Alignment Unit Size" section of various specs, namely:
657 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
658 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
659 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
660 * - BSpec (for Ivybridge and slight variations in separate stencil)
663 if (mt
->array_layout
== GEN6_HIZ_STENCIL
) {
664 /* On gen6, we use GEN6_HIZ_STENCIL for stencil/hiz because the
665 * hardware doesn't support multiple mip levels on stencil/hiz.
667 * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
668 * "The hierarchical depth buffer does not support the LOD field"
670 * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
671 * "The stencil depth buffer does not support the LOD field"
673 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
674 /* Stencil uses W tiling, so we force W tiling alignment for the
675 * ALL_SLICES_AT_EACH_LOD miptree layout.
679 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
681 /* See brw_miptree_layout_gen6_hiz_stencil() */
685 } else if (mt
->compressed
) {
686 /* The hardware alignment requirements for compressed textures
687 * happen to match the block boundaries.
689 _mesa_get_format_block_size(mt
->format
, &mt
->halign
, &mt
->valign
);
691 /* On Gen9+ we can pick our own alignment for compressed textures but it
692 * has to be a multiple of the block size. The minimum alignment we can
693 * pick is 4 so we effectively have to align to 4 times the block
700 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
702 mt
->valign
= brw
->gen
>= 7 ? 8 : 4;
705 intel_horizontal_texture_alignment_unit(brw
, mt
, layout_flags
);
706 mt
->valign
= intel_vertical_texture_alignment_unit(brw
, mt
);
711 brw_miptree_layout(struct brw_context
*brw
,
712 struct intel_mipmap_tree
*mt
,
713 uint32_t layout_flags
)
715 intel_miptree_set_alignment(brw
, mt
, layout_flags
);
716 intel_miptree_set_total_width_height(brw
, mt
);
718 if (!mt
->total_width
|| !mt
->total_height
)
721 /* On Gen9+ the alignment values are expressed in multiples of the block
726 _mesa_get_format_block_size(mt
->format
, &i
, &j
);
731 if ((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0)
732 mt
->tiling
= brw_miptree_choose_tiling(brw
, mt
, layout_flags
);