2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 /* Code to layout images in a mipmap tree for i965.
35 #include "intel_mipmap_tree.h"
36 #include "intel_tex_layout.h"
37 #include "intel_context.h"
38 #include "main/macros.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 brw_miptree_layout_texture_array(struct intel_context
*intel
,
44 struct intel_mipmap_tree
*mt
,
53 intel_get_texture_alignment_unit(mt
->format
, &align_w
, &align_h
);
55 h0
= ALIGN(mt
->height0
, align_h
);
56 h1
= ALIGN(minify(mt
->height0
), align_h
);
57 qpitch
= (h0
+ h1
+ (intel
->gen
>= 7 ? 12 : 11) * align_h
);
61 i945_miptree_layout_2d(mt
, slices
);
63 for (level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
64 for (q
= 0; q
< slices
; q
++) {
65 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* qpitch
);
68 mt
->total_height
= qpitch
* slices
;
72 brw_miptree_layout(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
)
74 /* XXX: these vary depending on image format: */
75 /* GLint align_w = 4; */
78 case GL_TEXTURE_CUBE_MAP
:
79 if (intel
->gen
>= 5) {
80 /* On Ironlake, cube maps are finally represented as just a series of
81 * MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated by a
82 * pitch of qpitch rows, where qpitch is defined by the equation given
83 * in Volume 1 of the BSpec.
85 brw_miptree_layout_texture_array(intel
, mt
, 6);
91 GLuint width
= mt
->width0
;
92 GLuint height
= mt
->height0
;
93 GLuint depth
= mt
->depth0
;
94 GLuint pack_x_pitch
, pack_x_nr
;
100 mt
->total_height
= 0;
101 intel_get_texture_alignment_unit(mt
->format
, &align_w
, &align_h
);
103 if (mt
->compressed
) {
104 mt
->total_width
= ALIGN(width
, align_w
);
105 pack_y_pitch
= (height
+ 3) / 4;
107 mt
->total_width
= mt
->width0
;
108 pack_y_pitch
= ALIGN(mt
->height0
, align_h
);
111 pack_x_pitch
= width
;
114 for (level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
115 GLuint nr_images
= mt
->target
== GL_TEXTURE_3D
? depth
: 6;
120 intel_miptree_set_level_info(mt
, level
, nr_images
,
122 width
, height
, depth
);
124 for (q
= 0; q
< nr_images
;) {
125 for (j
= 0; j
< pack_x_nr
&& q
< nr_images
; j
++, q
++) {
126 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
);
135 mt
->total_height
+= y
;
136 width
= minify(width
);
137 height
= minify(height
);
138 depth
= minify(depth
);
140 if (mt
->compressed
) {
141 pack_y_pitch
= (height
+ 3) / 4;
143 if (pack_x_pitch
> ALIGN(width
, align_w
)) {
144 pack_x_pitch
= ALIGN(width
, align_w
);
148 if (pack_x_pitch
> 4) {
151 assert(pack_x_pitch
* pack_x_nr
<= mt
->total_width
);
154 if (pack_y_pitch
> 2) {
156 pack_y_pitch
= ALIGN(pack_y_pitch
, align_h
);
161 /* The 965's sampler lays cachelines out according to how accesses
162 * in the texture surfaces run, so they may be "vertical" through
163 * memory. As a result, the docs say in Surface Padding Requirements:
164 * Sampling Engine Surfaces that two extra rows of padding are required.
166 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
167 mt
->total_height
+= 2;
171 case GL_TEXTURE_2D_ARRAY
:
172 case GL_TEXTURE_1D_ARRAY
:
173 brw_miptree_layout_texture_array(intel
, mt
, mt
->depth0
);
177 i945_miptree_layout_2d(mt
, 1);
180 DBG("%s: %dx%dx%d\n", __FUNCTION__
,
181 mt
->total_width
, mt
->total_height
, mt
->cpp
);