2 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * Copyright © 2006 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * \file brw_tex_layout.cpp
29 * Code to lay out images in a mipmap tree.
31 * \author Keith Whitwell <keith@tungstengraphics.com>
32 * \author Michel Dänzer <michel@tungstengraphics.com>
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
39 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
42 intel_horizontal_texture_alignment_unit(struct brw_context
*brw
,
46 * From the "Alignment Unit Size" section of various specs, namely:
47 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
48 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
49 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
50 * - BSpec (for Ivybridge and slight variations in separate stencil)
52 * +----------------------------------------------------------------------+
53 * | | alignment unit width ("i") |
54 * | Surface Property |-----------------------------|
55 * | | 915 | 965 | ILK | SNB | IVB |
56 * +----------------------------------------------------------------------+
57 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
58 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
59 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
60 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
61 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
62 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
63 * | All Others | 4 | 4 | 4 | 4 | 4 |
64 * +----------------------------------------------------------------------+
66 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
67 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
69 if (_mesa_is_format_compressed(format
)) {
70 /* The hardware alignment requirements for compressed textures
71 * happen to match the block boundaries.
74 _mesa_get_format_block_size(format
, &i
, &j
);
78 if (format
== MESA_FORMAT_S8
)
81 if (brw
->gen
>= 7 && format
== MESA_FORMAT_Z16
)
88 intel_vertical_texture_alignment_unit(struct brw_context
*brw
,
92 * From the "Alignment Unit Size" section of various specs, namely:
93 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
94 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
95 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
96 * - BSpec (for Ivybridge and slight variations in separate stencil)
98 * +----------------------------------------------------------------------+
99 * | | alignment unit height ("j") |
100 * | Surface Property |-----------------------------|
101 * | | 915 | 965 | ILK | SNB | IVB |
102 * +----------------------------------------------------------------------+
103 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
104 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
105 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
106 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
107 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
108 * | All Others | 2 | 2 | 2 | 2 | 2 |
109 * +----------------------------------------------------------------------+
111 * On SNB+, non-special cases can be overridden by setting the SURFACE_STATE
112 * "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4.
114 * We currently don't support multisampling.
116 if (_mesa_is_format_compressed(format
))
119 if (format
== MESA_FORMAT_S8
)
120 return brw
->gen
>= 7 ? 8 : 4;
122 GLenum base_format
= _mesa_get_format_base_format(format
);
125 (base_format
== GL_DEPTH_COMPONENT
||
126 base_format
== GL_DEPTH_STENCIL
)) {
134 brw_miptree_layout_2d(struct intel_mipmap_tree
*mt
)
138 unsigned width
= mt
->physical_width0
;
139 unsigned height
= mt
->physical_height0
;
140 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
142 mt
->total_width
= mt
->physical_width0
;
144 if (mt
->compressed
) {
145 mt
->total_width
= ALIGN(mt
->physical_width0
, mt
->align_w
);
148 /* May need to adjust width to accomodate the placement of
149 * the 2nd mipmap. This occurs when the alignment
150 * constraints of mipmap placement push the right edge of the
151 * 2nd mipmap out past the width of its parent.
153 if (mt
->first_level
!= mt
->last_level
) {
156 if (mt
->compressed
) {
157 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
158 ALIGN(minify(mt
->physical_width0
, 2), mt
->align_w
);
160 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
161 minify(mt
->physical_width0
, 2);
164 if (mip1_width
> mt
->total_width
) {
165 mt
->total_width
= mip1_width
;
169 mt
->total_height
= 0;
171 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
174 intel_miptree_set_level_info(mt
, level
, x
, y
, width
,
177 img_height
= ALIGN(height
, mt
->align_h
);
179 img_height
/= mt
->align_h
;
181 /* Because the images are packed better, the final offset
182 * might not be the maximal one:
184 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
186 /* Layout_below: step right after second mipmap.
188 if (level
== mt
->first_level
+ 1) {
189 x
+= ALIGN(width
, mt
->align_w
);
194 width
= minify(width
, 1);
195 height
= minify(height
, 1);
200 brw_miptree_layout_texture_array(struct brw_context
*brw
,
201 struct intel_mipmap_tree
*mt
)
206 h0
= ALIGN(mt
->physical_height0
, mt
->align_h
);
207 h1
= ALIGN(minify(mt
->physical_height0
, 1), mt
->align_h
);
208 if (mt
->array_spacing_lod0
)
211 qpitch
= (h0
+ h1
+ (brw
->gen
>= 7 ? 12 : 11) * mt
->align_h
);
215 brw_miptree_layout_2d(mt
);
217 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
218 for (int q
= 0; q
< mt
->physical_depth0
; q
++) {
219 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* qpitch
);
222 mt
->total_height
= qpitch
* mt
->physical_depth0
;
226 brw_miptree_layout_texture_3d(struct brw_context
*brw
,
227 struct intel_mipmap_tree
*mt
)
229 unsigned width
= mt
->physical_width0
;
230 unsigned height
= mt
->physical_height0
;
231 unsigned depth
= mt
->physical_depth0
;
232 unsigned pack_x_pitch
, pack_x_nr
;
233 unsigned pack_y_pitch
;
235 mt
->total_height
= 0;
237 if (mt
->compressed
) {
238 mt
->total_width
= ALIGN(width
, mt
->align_w
);
239 pack_y_pitch
= (height
+ 3) / 4;
241 mt
->total_width
= mt
->physical_width0
;
242 pack_y_pitch
= ALIGN(mt
->physical_height0
, mt
->align_h
);
245 pack_x_pitch
= width
;
248 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
252 intel_miptree_set_level_info(mt
, level
,
254 width
, height
, depth
);
256 for (int q
= 0; q
< depth
; /* empty */) {
257 for (int j
= 0; j
< pack_x_nr
&& q
< depth
; j
++, q
++) {
258 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
);
261 if (x
> mt
->total_width
)
268 mt
->total_height
+= y
;
269 width
= minify(width
, 1);
270 height
= minify(height
, 1);
271 if (mt
->target
== GL_TEXTURE_3D
)
272 depth
= minify(depth
, 1);
274 if (mt
->compressed
) {
275 pack_y_pitch
= (height
+ 3) / 4;
277 if (pack_x_pitch
> ALIGN(width
, mt
->align_w
)) {
278 pack_x_pitch
= ALIGN(width
, mt
->align_w
);
283 if (pack_x_pitch
> 4) {
287 if (pack_y_pitch
> 2) {
289 pack_y_pitch
= ALIGN(pack_y_pitch
, mt
->align_h
);
294 /* The 965's sampler lays cachelines out according to how accesses
295 * in the texture surfaces run, so they may be "vertical" through
296 * memory. As a result, the docs say in Surface Padding Requirements:
297 * Sampling Engine Surfaces that two extra rows of padding are required.
299 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
300 mt
->total_height
+= 2;
304 brw_miptree_layout(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
306 mt
->align_w
= intel_horizontal_texture_alignment_unit(brw
, mt
->format
);
307 mt
->align_h
= intel_vertical_texture_alignment_unit(brw
, mt
->format
);
309 switch (mt
->target
) {
310 case GL_TEXTURE_CUBE_MAP
:
312 /* Gen4 stores cube maps as 3D textures. */
313 assert(mt
->physical_depth0
== 6);
314 brw_miptree_layout_texture_3d(brw
, mt
);
316 /* All other hardware stores cube maps as 2D arrays. */
317 brw_miptree_layout_texture_array(brw
, mt
);
322 brw_miptree_layout_texture_3d(brw
, mt
);
325 case GL_TEXTURE_1D_ARRAY
:
326 case GL_TEXTURE_2D_ARRAY
:
327 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
328 case GL_TEXTURE_CUBE_MAP_ARRAY
:
329 brw_miptree_layout_texture_array(brw
, mt
);
333 switch (mt
->msaa_layout
) {
334 case INTEL_MSAA_LAYOUT_UMS
:
335 case INTEL_MSAA_LAYOUT_CMS
:
336 brw_miptree_layout_texture_array(brw
, mt
);
338 case INTEL_MSAA_LAYOUT_NONE
:
339 case INTEL_MSAA_LAYOUT_IMS
:
340 brw_miptree_layout_2d(mt
);
345 DBG("%s: %dx%dx%d\n", __FUNCTION__
,
346 mt
->total_width
, mt
->total_height
, mt
->cpp
);