2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 /* Code to layout images in a mipmap tree for i965.
35 #include "intel_mipmap_tree.h"
36 #include "intel_tex_layout.h"
37 #include "intel_context.h"
38 #include "main/macros.h"
39 #include "intel_chipset.h"
41 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 GLboolean
brw_miptree_layout(struct intel_context
*intel
,
44 struct intel_mipmap_tree
*mt
,
47 /* XXX: these vary depending on image format: */
48 /* GLint align_w = 4; */
51 case GL_TEXTURE_CUBE_MAP
:
52 if (IS_IGDNG(intel
->intelScreen
->deviceID
)) {
53 GLuint align_h
= 2, align_w
= 4;
57 GLuint width
= mt
->width0
;
58 GLuint height
= mt
->height0
;
62 mt
->pitch
= mt
->width0
;
63 intel_get_texture_alignment_unit(mt
->internal_format
, &align_w
, &align_h
);
64 y_pitch
= ALIGN(height
, align_h
);
67 mt
->pitch
= ALIGN(mt
->width0
, align_w
);
70 if (mt
->first_level
!= mt
->last_level
) {
74 mip1_width
= ALIGN(minify(mt
->width0
), align_w
)
75 + ALIGN(minify(minify(mt
->width0
)), align_w
);
77 mip1_width
= ALIGN(minify(mt
->width0
), align_w
)
78 + minify(minify(mt
->width0
));
81 if (mip1_width
> mt
->pitch
) {
82 mt
->pitch
= mip1_width
;
86 mt
->pitch
= intel_miptree_pitch_align(intel
, mt
, tiling
, mt
->pitch
);
89 qpitch
= (y_pitch
+ ALIGN(minify(y_pitch
), align_h
) + 11 * align_h
) / 4;
90 mt
->total_height
= (y_pitch
+ ALIGN(minify(y_pitch
), align_h
) + 11 * align_h
) / 4 * 6;
92 qpitch
= (y_pitch
+ ALIGN(minify(y_pitch
), align_h
) + 11 * align_h
);
93 mt
->total_height
= (y_pitch
+ ALIGN(minify(y_pitch
), align_h
) + 11 * align_h
) * 6;
96 for (level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
101 intel_miptree_set_level_info(mt
, level
, nr_images
, x
, y
, width
,
104 for (q
= 0; q
< nr_images
; q
++)
105 intel_miptree_set_image_offset(mt
, level
, q
,
109 img_height
= MAX2(1, height
/4);
111 img_height
= ALIGN(height
, align_h
);
113 if (level
== mt
->first_level
+ 1) {
114 x
+= ALIGN(width
, align_w
);
120 width
= minify(width
);
121 height
= minify(height
);
127 case GL_TEXTURE_3D
: {
128 GLuint width
= mt
->width0
;
129 GLuint height
= mt
->height0
;
130 GLuint depth
= mt
->depth0
;
131 GLuint pack_x_pitch
, pack_x_nr
;
137 mt
->total_height
= 0;
138 intel_get_texture_alignment_unit(mt
->internal_format
, &align_w
, &align_h
);
140 if (mt
->compressed
) {
141 mt
->pitch
= ALIGN(width
, align_w
);
142 pack_y_pitch
= (height
+ 3) / 4;
144 mt
->pitch
= intel_miptree_pitch_align (intel
, mt
, tiling
, mt
->width0
);
145 pack_y_pitch
= ALIGN(mt
->height0
, align_h
);
148 pack_x_pitch
= width
;
151 for (level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
152 GLuint nr_images
= mt
->target
== GL_TEXTURE_3D
? depth
: 6;
157 intel_miptree_set_level_info(mt
, level
, nr_images
,
159 width
, height
, depth
);
161 for (q
= 0; q
< nr_images
;) {
162 for (j
= 0; j
< pack_x_nr
&& q
< nr_images
; j
++, q
++) {
163 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
);
172 mt
->total_height
+= y
;
173 width
= minify(width
);
174 height
= minify(height
);
175 depth
= minify(depth
);
177 if (mt
->compressed
) {
178 pack_y_pitch
= (height
+ 3) / 4;
180 if (pack_x_pitch
> ALIGN(width
, align_w
)) {
181 pack_x_pitch
= ALIGN(width
, align_w
);
185 if (pack_x_pitch
> 4) {
188 assert(pack_x_pitch
* pack_x_nr
<= mt
->pitch
);
191 if (pack_y_pitch
> 2) {
193 pack_y_pitch
= ALIGN(pack_y_pitch
, align_h
);
198 /* The 965's sampler lays cachelines out according to how accesses
199 * in the texture surfaces run, so they may be "vertical" through
200 * memory. As a result, the docs say in Surface Padding Requirements:
201 * Sampling Engine Surfaces that two extra rows of padding are required.
202 * We don't know of similar requirements for pre-965, but given that
203 * those docs are silent on padding requirements in general, let's play
206 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
207 mt
->total_height
+= 2;
212 i945_miptree_layout_2d(intel
, mt
, tiling
);
215 DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__
,
219 mt
->pitch
* mt
->total_height
* mt
->cpp
);