2 * Copyright 2006 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * \file brw_tex_layout.cpp
29 * Code to lay out images in a mipmap tree.
31 * \author Keith Whitwell <keithw@vmware.com>
32 * \author Michel Dänzer <daenzer@vmware.com>
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
38 #include "main/glformats.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 tr_mode_horizontal_texture_alignment(const struct brw_context
*brw
,
44 const struct intel_mipmap_tree
*mt
)
46 const unsigned *align_yf
, *align_ys
;
47 const unsigned bpp
= _mesa_get_format_bytes(mt
->format
) * 8;
48 unsigned ret_align
, divisor
;
50 /* Horizontal alignment tables for TRMODE_{YF,YS}. Value in below
51 * tables specifies the horizontal alignment requirement in elements
52 * for the surface. An element is defined as a pixel in uncompressed
53 * surface formats, and as a compression block in compressed surface
54 * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
55 * element is a sample.
57 const unsigned align_1d_yf
[] = {4096, 2048, 1024, 512, 256};
58 const unsigned align_1d_ys
[] = {65536, 32768, 16384, 8192, 4096};
59 const unsigned align_2d_yf
[] = {64, 64, 32, 32, 16};
60 const unsigned align_2d_ys
[] = {256, 256, 128, 128, 64};
61 const unsigned align_3d_yf
[] = {16, 8, 8, 8, 4};
62 const unsigned align_3d_ys
[] = {64, 32, 32, 32, 16};
65 /* Alignment computations below assume bpp >= 8 and a power of 2. */
66 assert (bpp
>= 8 && bpp
<= 128 && _mesa_is_pow_two(bpp
));
70 case GL_TEXTURE_1D_ARRAY
:
71 align_yf
= align_1d_yf
;
72 align_ys
= align_1d_ys
;
75 case GL_TEXTURE_RECTANGLE
:
76 case GL_TEXTURE_2D_ARRAY
:
77 case GL_TEXTURE_CUBE_MAP
:
78 case GL_TEXTURE_CUBE_MAP_ARRAY
:
79 case GL_TEXTURE_2D_MULTISAMPLE
:
80 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
81 align_yf
= align_2d_yf
;
82 align_ys
= align_2d_ys
;
85 align_yf
= align_3d_yf
;
86 align_ys
= align_3d_ys
;
89 unreachable("not reached");
92 /* Compute array index. */
95 ret_align
= mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
96 align_yf
[i
] : align_ys
[i
];
98 assert(_mesa_is_pow_two(mt
->num_samples
));
100 switch (mt
->num_samples
) {
113 return ret_align
/ divisor
;
118 intel_horizontal_texture_alignment_unit(struct brw_context
*brw
,
119 struct intel_mipmap_tree
*mt
,
120 uint32_t layout_flags
)
122 if (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
)
126 * From the "Alignment Unit Size" section of various specs, namely:
127 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
128 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
129 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
130 * - BSpec (for Ivybridge and slight variations in separate stencil)
132 * +----------------------------------------------------------------------+
133 * | | alignment unit width ("i") |
134 * | Surface Property |-----------------------------|
135 * | | 915 | 965 | ILK | SNB | IVB |
136 * +----------------------------------------------------------------------+
137 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
138 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
139 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
140 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
141 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
142 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
143 * | All Others | 4 | 4 | 4 | 4 | 4 |
144 * +----------------------------------------------------------------------+
146 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
147 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
149 if (_mesa_is_format_compressed(mt
->format
)) {
150 /* The hardware alignment requirements for compressed textures
151 * happen to match the block boundaries.
154 _mesa_get_format_block_size(mt
->format
, &i
, &j
);
156 /* On Gen9+ we can pick our own alignment for compressed textures but it
157 * has to be a multiple of the block size. The minimum alignment we can
158 * pick is 4 so we effectively have to align to 4 times the block
167 if (mt
->format
== MESA_FORMAT_S_UINT8
)
170 if (brw
->gen
>= 9 && mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
171 uint32_t align
= tr_mode_horizontal_texture_alignment(brw
, mt
);
172 /* XY_FAST_COPY_BLT doesn't support horizontal alignment < 32. */
173 return align
< 32 ? 32 : align
;
176 if (brw
->gen
>= 7 && mt
->format
== MESA_FORMAT_Z_UNORM16
)
183 tr_mode_vertical_texture_alignment(const struct brw_context
*brw
,
184 const struct intel_mipmap_tree
*mt
)
186 const unsigned *align_yf
, *align_ys
;
187 const unsigned bpp
= _mesa_get_format_bytes(mt
->format
) * 8;
188 unsigned ret_align
, divisor
;
190 /* Vertical alignment tables for TRMODE_YF and TRMODE_YS. */
191 const unsigned align_2d_yf
[] = {64, 32, 32, 16, 16};
192 const unsigned align_2d_ys
[] = {256, 128, 128, 64, 64};
193 const unsigned align_3d_yf
[] = {16, 16, 16, 8, 8};
194 const unsigned align_3d_ys
[] = {32, 32, 32, 16, 16};
197 assert(brw
->gen
>= 9 &&
198 mt
->target
!= GL_TEXTURE_1D
&&
199 mt
->target
!= GL_TEXTURE_1D_ARRAY
);
201 /* Alignment computations below assume bpp >= 8 and a power of 2. */
202 assert (bpp
>= 8 && bpp
<= 128 && _mesa_is_pow_two(bpp
)) ;
206 case GL_TEXTURE_RECTANGLE
:
207 case GL_TEXTURE_2D_ARRAY
:
208 case GL_TEXTURE_CUBE_MAP
:
209 case GL_TEXTURE_CUBE_MAP_ARRAY
:
210 case GL_TEXTURE_2D_MULTISAMPLE
:
211 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
212 align_yf
= align_2d_yf
;
213 align_ys
= align_2d_ys
;
216 align_yf
= align_3d_yf
;
217 align_ys
= align_3d_ys
;
220 unreachable("not reached");
223 /* Compute array index. */
224 i
= ffs(bpp
/ 8) - 1;
226 ret_align
= mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
227 align_yf
[i
] : align_ys
[i
];
229 assert(_mesa_is_pow_two(mt
->num_samples
));
231 switch (mt
->num_samples
) {
243 return ret_align
/ divisor
;
247 intel_vertical_texture_alignment_unit(struct brw_context
*brw
,
248 const struct intel_mipmap_tree
*mt
)
251 * From the "Alignment Unit Size" section of various specs, namely:
252 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
253 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
254 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
255 * - BSpec (for Ivybridge and slight variations in separate stencil)
257 * +----------------------------------------------------------------------+
258 * | | alignment unit height ("j") |
259 * | Surface Property |-----------------------------|
260 * | | 915 | 965 | ILK | SNB | IVB |
261 * +----------------------------------------------------------------------+
262 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
263 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
264 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
265 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
266 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
267 * | All Others | 2 | 2 | 2 | * | * |
268 * +----------------------------------------------------------------------+
270 * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
271 * the SURFACE_STATE "Surface Vertical Alignment" field.
273 if (_mesa_is_format_compressed(mt
->format
))
274 /* See comment above for the horizontal alignment */
275 return brw
->gen
>= 9 ? 16 : 4;
277 if (mt
->format
== MESA_FORMAT_S_UINT8
)
278 return brw
->gen
>= 7 ? 8 : 4;
280 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
281 uint32_t align
= tr_mode_vertical_texture_alignment(brw
, mt
);
282 /* XY_FAST_COPY_BLT doesn't support vertical alignment < 64 */
283 return align
< 64 ? 64 : align
;
286 /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
287 * should always be used, except for stencil buffers, which should be 8.
292 if (mt
->num_samples
> 1)
295 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
298 (base_format
== GL_DEPTH_COMPONENT
||
299 base_format
== GL_DEPTH_STENCIL
)) {
304 /* On Gen7, we prefer a vertical alignment of 4 when possible, because
305 * that allows Y tiled render targets.
307 * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
308 * messages), on p64, under the heading "Surface Vertical Alignment":
310 * Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
311 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
314 * VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
316 if (base_format
== GL_YCBCR_MESA
|| mt
->format
== MESA_FORMAT_RGB_FLOAT32
)
326 gen9_miptree_layout_1d(struct intel_mipmap_tree
*mt
)
329 unsigned width
= mt
->physical_width0
;
330 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
332 /* When this layout is used the horizontal alignment is fixed at 64 and the
333 * hardware ignores the value given in the surface state
335 const unsigned int align_w
= 64;
337 mt
->total_height
= mt
->physical_height0
;
340 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
343 intel_miptree_set_level_info(mt
, level
, x
, 0, depth
);
345 img_width
= ALIGN(width
, align_w
);
347 mt
->total_width
= MAX2(mt
->total_width
, x
+ img_width
);
351 width
= minify(width
, 1);
356 brw_miptree_layout_2d(struct intel_mipmap_tree
*mt
)
360 unsigned width
= mt
->physical_width0
;
361 unsigned height
= mt
->physical_height0
;
362 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
365 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
367 mt
->total_width
= mt
->physical_width0
;
370 mt
->total_width
= ALIGN(mt
->total_width
, bw
);
372 /* May need to adjust width to accommodate the placement of
373 * the 2nd mipmap. This occurs when the alignment
374 * constraints of mipmap placement push the right edge of the
375 * 2nd mipmap out past the width of its parent.
377 if (mt
->first_level
!= mt
->last_level
) {
380 if (mt
->compressed
) {
381 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
382 ALIGN(minify(mt
->physical_width0
, 2), bw
);
384 mip1_width
= ALIGN(minify(mt
->physical_width0
, 1), mt
->align_w
) +
385 minify(mt
->physical_width0
, 2);
388 if (mip1_width
> mt
->total_width
) {
389 mt
->total_width
= mip1_width
;
393 mt
->total_height
= 0;
395 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
398 intel_miptree_set_level_info(mt
, level
, x
, y
, depth
);
400 img_height
= ALIGN(height
, mt
->align_h
);
404 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
405 /* Compact arrays with separated miplevels */
409 /* Because the images are packed better, the final offset
410 * might not be the maximal one:
412 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
414 /* Layout_below: step right after second mipmap.
416 if (level
== mt
->first_level
+ 1) {
417 x
+= ALIGN(width
, mt
->align_w
);
422 width
= minify(width
, 1);
423 height
= minify(height
, 1);
425 if (mt
->target
== GL_TEXTURE_3D
)
426 depth
= minify(depth
, 1);
431 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
432 const struct intel_mipmap_tree
*mt
,
435 if ((brw
->gen
< 9 && mt
->target
== GL_TEXTURE_3D
) ||
436 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
)) {
437 return ALIGN(minify(mt
->physical_width0
, level
), mt
->align_w
);
444 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
445 const struct intel_mipmap_tree
*mt
,
449 /* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
450 * effectively end up with a packed qpitch anyway whenever
451 * mt->first_level == mt->last_level.
453 assert(mt
->array_layout
!= ALL_SLICES_AT_EACH_LOD
);
455 /* On Gen9 we can pick whatever qpitch we like as long as it's aligned
456 * to the vertical alignment so we don't need to add any extra rows.
458 unsigned qpitch
= mt
->total_height
;
460 /* If the surface might be used as a stencil buffer or HiZ buffer then
461 * it needs to be a multiple of 8.
463 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
464 if (_mesa_is_depth_or_stencil_format(base_format
))
465 qpitch
= ALIGN(qpitch
, 8);
467 /* 3D textures need to be aligned to the tile height. At this point we
468 * don't know which tiling will be used so let's just align it to 32
470 if (mt
->target
== GL_TEXTURE_3D
)
471 qpitch
= ALIGN(qpitch
, 32);
475 } else if (mt
->target
== GL_TEXTURE_3D
||
476 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
) ||
477 mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
478 return ALIGN(minify(mt
->physical_height0
, level
), mt
->align_h
);
481 const unsigned h0
= ALIGN(mt
->physical_height0
, mt
->align_h
);
482 const unsigned h1
= ALIGN(minify(mt
->physical_height0
, 1), mt
->align_h
);
484 return h0
+ h1
+ (brw
->gen
>= 7 ? 12 : 11) * mt
->align_h
;
489 align_cube(struct intel_mipmap_tree
*mt
)
491 /* The 965's sampler lays cachelines out according to how accesses
492 * in the texture surfaces run, so they may be "vertical" through
493 * memory. As a result, the docs say in Surface Padding Requirements:
494 * Sampling Engine Surfaces that two extra rows of padding are required.
496 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
497 mt
->total_height
+= 2;
501 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
502 const struct intel_mipmap_tree
*mt
)
504 /* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
505 * horizontal line. This isn't done for depth/stencil buffers however
506 * because those will be using a tiled layout
509 (mt
->target
== GL_TEXTURE_1D
||
510 mt
->target
== GL_TEXTURE_1D_ARRAY
)) {
511 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
513 if (base_format
!= GL_DEPTH_COMPONENT
&&
514 base_format
!= GL_DEPTH_STENCIL
&&
515 base_format
!= GL_STENCIL_INDEX
)
523 brw_miptree_layout_texture_array(struct brw_context
*brw
,
524 struct intel_mipmap_tree
*mt
)
526 unsigned height
= mt
->physical_height0
;
527 bool layout_1d
= gen9_use_linear_1d_layout(brw
, mt
);
531 gen9_miptree_layout_1d(mt
);
533 brw_miptree_layout_2d(mt
);
537 /* When using the horizontal layout the qpitch specifies the distance in
538 * pixels between array slices. The total_width is forced to be a
539 * multiple of the horizontal alignment in brw_miptree_layout_1d (in
540 * this case it's always 64). The vertical alignment is ignored.
542 mt
->qpitch
= mt
->total_width
;
544 mt
->qpitch
= brw_miptree_get_vertical_slice_pitch(brw
, mt
, 0);
545 /* Unlike previous generations the qpitch is a multiple of the
546 * compressed block size on Gen9 so physical_qpitch matches mt->qpitch.
548 physical_qpitch
= (mt
->compressed
&& brw
->gen
< 9 ? mt
->qpitch
/ 4 :
552 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
554 img_height
= ALIGN(height
, mt
->align_h
);
556 img_height
/= mt
->align_h
;
558 for (unsigned q
= 0; q
< mt
->level
[level
].depth
; q
++) {
559 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
560 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* img_height
);
562 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* physical_qpitch
);
565 height
= minify(height
, 1);
567 if (mt
->array_layout
== ALL_LOD_IN_EACH_SLICE
)
568 mt
->total_height
= physical_qpitch
* mt
->physical_depth0
;
574 brw_miptree_layout_texture_3d(struct brw_context
*brw
,
575 struct intel_mipmap_tree
*mt
)
577 unsigned yscale
= mt
->compressed
? 4 : 1;
580 mt
->total_height
= 0;
583 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
584 unsigned WL
= MAX2(mt
->physical_width0
>> level
, 1);
585 unsigned HL
= MAX2(mt
->physical_height0
>> level
, 1);
586 unsigned DL
= MAX2(mt
->physical_depth0
>> level
, 1);
587 unsigned wL
= ALIGN(WL
, mt
->align_w
);
588 unsigned hL
= ALIGN(HL
, mt
->align_h
);
590 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
593 intel_miptree_set_level_info(mt
, level
, 0, 0, DL
);
595 for (unsigned q
= 0; q
< DL
; q
++) {
596 unsigned x
= (q
% (1 << level
)) * wL
;
597 unsigned y
= ysum
+ (q
>> level
) * hL
;
599 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
/ yscale
);
600 mt
->total_width
= MAX2(mt
->total_width
, x
+ wL
);
601 mt
->total_height
= MAX2(mt
->total_height
, (y
+ hL
) / yscale
);
604 ysum
+= ALIGN(DL
, 1 << level
) / (1 << level
) * hL
;
611 * \brief Helper function for intel_miptree_create().
614 brw_miptree_choose_tiling(struct brw_context
*brw
,
615 const struct intel_mipmap_tree
*mt
,
616 uint32_t layout_flags
)
618 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
619 /* The stencil buffer is W tiled. However, we request from the kernel a
620 * non-tiled buffer because the GTT is incapable of W fencing.
622 return I915_TILING_NONE
;
625 /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
626 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
628 /* Some usages may want only one type of tiling, like depth miptrees (Y
629 * tiled), or temporary BOs for uploading data once (linear).
631 switch (layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) {
632 case MIPTREE_LAYOUT_TILING_ANY
:
634 case MIPTREE_LAYOUT_TILING_Y
:
635 return I915_TILING_Y
;
636 case MIPTREE_LAYOUT_TILING_NONE
:
637 return I915_TILING_NONE
;
640 if (mt
->num_samples
> 1) {
641 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
644 * [DevSNB+]: For multi-sample render targets, this field must be
645 * 1. MSRTs can only be tiled.
647 * Our usual reason for preferring X tiling (fast blits using the
648 * blitting engine) doesn't apply to MSAA, since we'll generally be
649 * downsampling or upsampling when blitting between the MSAA buffer
650 * and another buffer, and the blitting engine doesn't support that.
651 * So use Y tiling, since it makes better use of the cache.
653 return I915_TILING_Y
;
656 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
657 if (base_format
== GL_DEPTH_COMPONENT
||
658 base_format
== GL_DEPTH_STENCIL_EXT
)
659 return I915_TILING_Y
;
661 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
662 * in fact it leads to a less efficient use of memory space and bandwidth
663 * due to tile alignment.
665 if (mt
->logical_height0
== 1)
666 return I915_TILING_NONE
;
668 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
670 /* If the width is much smaller than a tile, don't bother tiling. */
671 if (minimum_pitch
< 64)
672 return I915_TILING_NONE
;
674 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
675 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
676 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
677 mt
->total_width
, mt
->total_height
);
678 return I915_TILING_NONE
;
681 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
683 return I915_TILING_X
;
685 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
686 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
688 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
689 * all the way back to 965, but is permitted on Gen7+.
691 if (brw
->gen
< 7 && mt
->cpp
>= 16)
692 return I915_TILING_X
;
694 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
695 * messages), on p64, under the heading "Surface Vertical Alignment":
697 * This field must be set to VALIGN_4 for all tiled Y Render Target
700 * So if the surface is renderable and uses a vertical alignment of 2,
701 * force it to be X tiled. This is somewhat conservative (it's possible
702 * that the client won't ever render to this surface), but it's difficult
703 * to know that ahead of time. And besides, since we use a vertical
704 * alignment of 4 as often as we can, this shouldn't happen very often.
706 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
707 brw
->format_supported_as_render_target
[mt
->format
]) {
708 return I915_TILING_X
;
711 return I915_TILING_Y
| I915_TILING_X
;
715 intel_miptree_set_total_width_height(struct brw_context
*brw
,
716 struct intel_mipmap_tree
*mt
)
718 switch (mt
->target
) {
719 case GL_TEXTURE_CUBE_MAP
:
721 /* Gen4 stores cube maps as 3D textures. */
722 assert(mt
->physical_depth0
== 6);
723 brw_miptree_layout_texture_3d(brw
, mt
);
725 /* All other hardware stores cube maps as 2D arrays. */
726 brw_miptree_layout_texture_array(brw
, mt
);
732 brw_miptree_layout_texture_array(brw
, mt
);
734 brw_miptree_layout_texture_3d(brw
, mt
);
737 case GL_TEXTURE_1D_ARRAY
:
738 case GL_TEXTURE_2D_ARRAY
:
739 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
740 case GL_TEXTURE_CUBE_MAP_ARRAY
:
741 brw_miptree_layout_texture_array(brw
, mt
);
745 switch (mt
->msaa_layout
) {
746 case INTEL_MSAA_LAYOUT_UMS
:
747 case INTEL_MSAA_LAYOUT_CMS
:
748 brw_miptree_layout_texture_array(brw
, mt
);
750 case INTEL_MSAA_LAYOUT_NONE
:
751 case INTEL_MSAA_LAYOUT_IMS
:
752 if (gen9_use_linear_1d_layout(brw
, mt
))
753 gen9_miptree_layout_1d(mt
);
755 brw_miptree_layout_2d(mt
);
761 DBG("%s: %dx%dx%d\n", __func__
,
762 mt
->total_width
, mt
->total_height
, mt
->cpp
);
766 intel_miptree_set_alignment(struct brw_context
*brw
,
767 struct intel_mipmap_tree
*mt
,
768 uint32_t layout_flags
)
770 bool gen6_hiz_or_stencil
= false;
772 if (brw
->gen
== 6 && mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
773 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
774 gen6_hiz_or_stencil
= _mesa_is_depth_or_stencil_format(base_format
);
777 if (gen6_hiz_or_stencil
) {
778 /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
779 * hardware doesn't support multiple mip levels on stencil/hiz.
781 * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
782 * "The hierarchical depth buffer does not support the LOD field"
784 * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
785 * "The stencil depth buffer does not support the LOD field"
787 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
788 /* Stencil uses W tiling, so we force W tiling alignment for the
789 * ALL_SLICES_AT_EACH_LOD miptree layout.
793 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
795 /* Depth uses Y tiling, so we force need Y tiling alignment for the
796 * ALL_SLICES_AT_EACH_LOD miptree layout.
798 mt
->align_w
= 128 / mt
->cpp
;
803 intel_horizontal_texture_alignment_unit(brw
, mt
, layout_flags
);
804 mt
->align_h
= intel_vertical_texture_alignment_unit(brw
, mt
);
809 brw_miptree_layout(struct brw_context
*brw
,
810 struct intel_mipmap_tree
*mt
,
811 uint32_t layout_flags
)
813 mt
->tr_mode
= INTEL_MIPTREE_TRMODE_NONE
;
815 intel_miptree_set_alignment(brw
, mt
, layout_flags
);
816 intel_miptree_set_total_width_height(brw
, mt
);
818 if (!mt
->total_width
|| !mt
->total_height
) {
819 intel_miptree_release(&mt
);
823 /* On Gen9+ the alignment values are expressed in multiples of the block
828 _mesa_get_format_block_size(mt
->format
, &i
, &j
);
833 if ((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0)
834 mt
->tiling
= brw_miptree_choose_tiling(brw
, mt
, layout_flags
);