src/mesa/drivers/dri/i965/brw_tex_layout.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 /* Code to layout images in a mipmap tree for i965.
  33  */
  34
  35 #include "intel_mipmap_tree.h"
  36 #include "intel_tex_layout.h"
  37 #include "intel_context.h"
  38 #include "main/macros.h"
  39
  40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
  41
  42 static void
  43 brw_miptree_layout_texture_array(struct intel_context *intel,
  44                                  struct intel_mipmap_tree *mt)
  45 {
  46    GLuint level;
  47    GLuint qpitch = 0;
  48    int h0, h1, q;
  49
  50    h0 = ALIGN(mt->height0, mt->align_h);
  51    h1 = ALIGN(minify(mt->height0), mt->align_h);
  52    qpitch = (h0 + h1 + (intel->gen >= 7 ? 12 : 11) * mt->align_h);
  53    if (mt->compressed)
  54       qpitch /= 4;
  55
  56    i945_miptree_layout_2d(mt);
  57
  58    for (level = mt->first_level; level <= mt->last_level; level++) {
  59       for (q = 0; q < mt->depth0; q++) {
  60          intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
  61       }
  62    }
  63    mt->total_height = qpitch * mt->depth0;
  64 }
  65
  66 void
  67 brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
  68 {
  69    switch (mt->target) {
  70    case GL_TEXTURE_CUBE_MAP:
  71       if (intel->gen >= 5) {
  72          /* On Ironlake, cube maps are finally represented as just a series of
  73           * MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated by a
  74           * pitch of qpitch rows, where qpitch is defined by the equation given
  75           * in Volume 1 of the BSpec.
  76           */
  77          brw_miptree_layout_texture_array(intel, mt);
  78          break;
  79       }
  80       /* FALLTHROUGH */
  81
  82    case GL_TEXTURE_3D: {
  83       GLuint width  = mt->width0;
  84       GLuint height = mt->height0;
  85       GLuint depth = mt->depth0;
  86       GLuint pack_x_pitch, pack_x_nr;
  87       GLuint pack_y_pitch;
  88       GLuint level;
  89
  90       mt->total_height = 0;
  91
  92       if (mt->compressed) {
  93           mt->total_width = ALIGN(width, mt->align_w);
  94           pack_y_pitch = (height + 3) / 4;
  95       } else {
  96          mt->total_width = mt->width0;
  97          pack_y_pitch = ALIGN(mt->height0, mt->align_h);
  98       }
  99
 100       pack_x_pitch = width;
 101       pack_x_nr = 1;
 102
 103       for (level = mt->first_level ; level <= mt->last_level ; level++) {
 104          GLuint nr_images = mt->target == GL_TEXTURE_3D ? depth : 6;
 105          GLint x = 0;
 106          GLint y = 0;
 107          GLint q, j;
 108
 109          intel_miptree_set_level_info(mt, level,
 110                                       0, mt->total_height,
 111                                       width, height, depth);
 112
 113          for (q = 0; q < nr_images;) {
 114             for (j = 0; j < pack_x_nr && q < nr_images; j++, q++) {
 115                intel_miptree_set_image_offset(mt, level, q, x, y);
 116                x += pack_x_pitch;
 117             }
 118
 119             x = 0;
 120             y += pack_y_pitch;
 121          }
 122
 123
 124          mt->total_height += y;
 125          width  = minify(width);
 126          height = minify(height);
 127          depth  = minify(depth);
 128
 129          if (mt->compressed) {
 130             pack_y_pitch = (height + 3) / 4;
 131
 132             if (pack_x_pitch > ALIGN(width, mt->align_w)) {
 133                pack_x_pitch = ALIGN(width, mt->align_w);
 134                pack_x_nr <<= 1;
 135             }
 136          } else {
 137             if (pack_x_pitch > 4) {
 138                pack_x_pitch >>= 1;
 139                pack_x_nr <<= 1;
 140                assert(pack_x_pitch * pack_x_nr <= mt->total_width);
 141             }
 142
 143             if (pack_y_pitch > 2) {
 144                pack_y_pitch >>= 1;
 145                pack_y_pitch = ALIGN(pack_y_pitch, mt->align_h);
 146             }
 147          }
 148
 149       }
 150       /* The 965's sampler lays cachelines out according to how accesses
 151        * in the texture surfaces run, so they may be "vertical" through
 152        * memory.  As a result, the docs say in Surface Padding Requirements:
 153        * Sampling Engine Surfaces that two extra rows of padding are required.
 154        */
 155       if (mt->target == GL_TEXTURE_CUBE_MAP)
 156          mt->total_height += 2;
 157       break;
 158    }
 159
 160    case GL_TEXTURE_2D_ARRAY:
 161    case GL_TEXTURE_1D_ARRAY:
 162       brw_miptree_layout_texture_array(intel, mt);
 163       break;
 164
 165    default:
 166       i945_miptree_layout_2d(mt);
 167       break;
 168    }
 169    DBG("%s: %dx%dx%d\n", __FUNCTION__,
 170        mt->total_width, mt->total_height, mt->cpp);
 171 }
 172