2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 /* Code to layout images in a mipmap tree for i965.
35 #include "intel_mipmap_tree.h"
36 #include "intel_tex_layout.h"
37 #include "intel_context.h"
38 #include "main/macros.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 brw_miptree_layout_texture_array(struct intel_context
*intel
,
44 struct intel_mipmap_tree
*mt
)
50 h0
= ALIGN(mt
->physical_height0
, mt
->align_h
);
51 h1
= ALIGN(minify(mt
->physical_height0
, 1), mt
->align_h
);
52 if (mt
->array_spacing_lod0
)
55 qpitch
= (h0
+ h1
+ (intel
->gen
>= 7 ? 12 : 11) * mt
->align_h
);
59 i945_miptree_layout_2d(mt
);
61 for (level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
62 for (q
= 0; q
< mt
->physical_depth0
; q
++) {
63 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* qpitch
);
66 mt
->total_height
= qpitch
* mt
->physical_depth0
;
70 brw_miptree_layout(struct intel_context
*intel
, struct intel_mipmap_tree
*mt
)
73 case GL_TEXTURE_CUBE_MAP_ARRAY
:
74 brw_miptree_layout_texture_array(intel
, mt
);
77 case GL_TEXTURE_CUBE_MAP
:
78 if (intel
->gen
>= 5) {
79 /* On Ironlake, cube maps are finally represented as just a series of
80 * MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated by a
81 * pitch of qpitch rows, where qpitch is defined by the equation given
82 * in Volume 1 of the BSpec.
84 brw_miptree_layout_texture_array(intel
, mt
);
87 assert(mt
->physical_depth0
== 6);
91 GLuint width
= mt
->physical_width0
;
92 GLuint height
= mt
->physical_height0
;
93 GLuint depth
= mt
->physical_depth0
;
94 GLuint pack_x_pitch
, pack_x_nr
;
100 if (mt
->compressed
) {
101 mt
->total_width
= ALIGN(width
, mt
->align_w
);
102 pack_y_pitch
= (height
+ 3) / 4;
104 mt
->total_width
= mt
->physical_width0
;
105 pack_y_pitch
= ALIGN(mt
->physical_height0
, mt
->align_h
);
108 pack_x_pitch
= width
;
111 for (level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
116 intel_miptree_set_level_info(mt
, level
,
118 width
, height
, depth
);
120 for (q
= 0; q
< depth
; /* empty */) {
121 for (j
= 0; j
< pack_x_nr
&& q
< depth
; j
++, q
++) {
122 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
);
125 if (x
> mt
->total_width
)
133 mt
->total_height
+= y
;
134 width
= minify(width
, 1);
135 height
= minify(height
, 1);
136 if (mt
->target
== GL_TEXTURE_3D
)
137 depth
= minify(depth
, 1);
139 if (mt
->compressed
) {
140 pack_y_pitch
= (height
+ 3) / 4;
142 if (pack_x_pitch
> ALIGN(width
, mt
->align_w
)) {
143 pack_x_pitch
= ALIGN(width
, mt
->align_w
);
148 if (pack_x_pitch
> 4) {
152 if (pack_y_pitch
> 2) {
154 pack_y_pitch
= ALIGN(pack_y_pitch
, mt
->align_h
);
159 /* The 965's sampler lays cachelines out according to how accesses
160 * in the texture surfaces run, so they may be "vertical" through
161 * memory. As a result, the docs say in Surface Padding Requirements:
162 * Sampling Engine Surfaces that two extra rows of padding are required.
164 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
165 mt
->total_height
+= 2;
169 case GL_TEXTURE_2D_ARRAY
:
170 case GL_TEXTURE_1D_ARRAY
:
171 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
172 brw_miptree_layout_texture_array(intel
, mt
);
176 switch (mt
->msaa_layout
) {
177 case INTEL_MSAA_LAYOUT_UMS
:
178 case INTEL_MSAA_LAYOUT_CMS
:
179 brw_miptree_layout_texture_array(intel
, mt
);
181 case INTEL_MSAA_LAYOUT_NONE
:
182 case INTEL_MSAA_LAYOUT_IMS
:
183 i945_miptree_layout_2d(mt
);
188 DBG("%s: %dx%dx%d\n", __FUNCTION__
,
189 mt
->total_width
, mt
->total_height
, mt
->cpp
);