fb78b08b64916982f84fff7f67efd5e030a80b00
[mesa.git] / src / mesa / drivers / dri / i965 / brw_tex_layout.c
1 /*
2 * Copyright 2006 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 /**
27 * \file brw_tex_layout.cpp
28 *
29 * Code to lay out images in a mipmap tree.
30 *
31 * \author Keith Whitwell <keithw@vmware.com>
32 * \author Michel Dänzer <daenzer@vmware.com>
33 */
34
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
38 #include "main/glformats.h"
39
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
41
42 static unsigned int
43 tr_mode_horizontal_texture_alignment(const struct brw_context *brw,
44 const struct intel_mipmap_tree *mt)
45 {
46 const unsigned *align_yf, *align_ys;
47 const unsigned bpp = _mesa_get_format_bytes(mt->format) * 8;
48 unsigned ret_align, divisor;
49
50 /* Horizontal alignment tables for TRMODE_{YF,YS}. Value in below
51 * tables specifies the horizontal alignment requirement in elements
52 * for the surface. An element is defined as a pixel in uncompressed
53 * surface formats, and as a compression block in compressed surface
54 * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
55 * element is a sample.
56 */
57 const unsigned align_1d_yf[] = {4096, 2048, 1024, 512, 256};
58 const unsigned align_1d_ys[] = {65536, 32768, 16384, 8192, 4096};
59 const unsigned align_2d_yf[] = {64, 64, 32, 32, 16};
60 const unsigned align_2d_ys[] = {256, 256, 128, 128, 64};
61 const unsigned align_3d_yf[] = {16, 8, 8, 8, 4};
62 const unsigned align_3d_ys[] = {64, 32, 32, 32, 16};
63 int i = 0;
64
65 /* Alignment computations below assume bpp >= 8 and a power of 2. */
66 assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
67
68 switch(mt->target) {
69 case GL_TEXTURE_1D:
70 case GL_TEXTURE_1D_ARRAY:
71 align_yf = align_1d_yf;
72 align_ys = align_1d_ys;
73 break;
74 case GL_TEXTURE_2D:
75 case GL_TEXTURE_RECTANGLE:
76 case GL_TEXTURE_2D_ARRAY:
77 case GL_TEXTURE_CUBE_MAP:
78 case GL_TEXTURE_CUBE_MAP_ARRAY:
79 case GL_TEXTURE_2D_MULTISAMPLE:
80 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
81 align_yf = align_2d_yf;
82 align_ys = align_2d_ys;
83 break;
84 case GL_TEXTURE_3D:
85 align_yf = align_3d_yf;
86 align_ys = align_3d_ys;
87 break;
88 default:
89 unreachable("not reached");
90 }
91
92 /* Compute array index. */
93 i = ffs(bpp/8) - 1;
94
95 ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
96 align_yf[i] : align_ys[i];
97
98 assert(_mesa_is_pow_two(mt->num_samples));
99
100 switch (mt->num_samples) {
101 case 2:
102 case 4:
103 divisor = 2;
104 break;
105 case 8:
106 case 16:
107 divisor = 4;
108 break;
109 default:
110 divisor = 1;
111 break;
112 }
113 return ret_align / divisor;
114 }
115
116
117 static unsigned int
118 intel_horizontal_texture_alignment_unit(struct brw_context *brw,
119 struct intel_mipmap_tree *mt,
120 uint32_t layout_flags)
121 {
122 if (layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16)
123 return 16;
124
125 /**
126 * From the "Alignment Unit Size" section of various specs, namely:
127 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
128 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
129 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
130 * - BSpec (for Ivybridge and slight variations in separate stencil)
131 *
132 * +----------------------------------------------------------------------+
133 * | | alignment unit width ("i") |
134 * | Surface Property |-----------------------------|
135 * | | 915 | 965 | ILK | SNB | IVB |
136 * +----------------------------------------------------------------------+
137 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
138 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
139 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
140 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
141 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
142 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
143 * | All Others | 4 | 4 | 4 | 4 | 4 |
144 * +----------------------------------------------------------------------+
145 *
146 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
147 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
148 */
149 if (_mesa_is_format_compressed(mt->format)) {
150 /* The hardware alignment requirements for compressed textures
151 * happen to match the block boundaries.
152 */
153 unsigned int i, j;
154 _mesa_get_format_block_size(mt->format, &i, &j);
155
156 /* On Gen9+ we can pick our own alignment for compressed textures but it
157 * has to be a multiple of the block size. The minimum alignment we can
158 * pick is 4 so we effectively have to align to 4 times the block
159 * size
160 */
161 if (brw->gen >= 9)
162 return i * 4;
163 else
164 return i;
165 }
166
167 if (mt->format == MESA_FORMAT_S_UINT8)
168 return 8;
169
170 if (brw->gen >= 9 && mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
171 uint32_t align = tr_mode_horizontal_texture_alignment(brw, mt);
172 /* XY_FAST_COPY_BLT doesn't support horizontal alignment < 32. */
173 return align < 32 ? 32 : align;
174 }
175
176 if (brw->gen >= 7 && mt->format == MESA_FORMAT_Z_UNORM16)
177 return 8;
178
179 return 4;
180 }
181
182 static unsigned int
183 tr_mode_vertical_texture_alignment(const struct brw_context *brw,
184 const struct intel_mipmap_tree *mt)
185 {
186 const unsigned *align_yf, *align_ys;
187 const unsigned bpp = _mesa_get_format_bytes(mt->format) * 8;
188 unsigned ret_align, divisor;
189
190 /* Vertical alignment tables for TRMODE_YF and TRMODE_YS. */
191 const unsigned align_2d_yf[] = {64, 32, 32, 16, 16};
192 const unsigned align_2d_ys[] = {256, 128, 128, 64, 64};
193 const unsigned align_3d_yf[] = {16, 16, 16, 8, 8};
194 const unsigned align_3d_ys[] = {32, 32, 32, 16, 16};
195 int i = 0;
196
197 assert(brw->gen >= 9 &&
198 mt->target != GL_TEXTURE_1D &&
199 mt->target != GL_TEXTURE_1D_ARRAY);
200
201 /* Alignment computations below assume bpp >= 8 and a power of 2. */
202 assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)) ;
203
204 switch(mt->target) {
205 case GL_TEXTURE_2D:
206 case GL_TEXTURE_RECTANGLE:
207 case GL_TEXTURE_2D_ARRAY:
208 case GL_TEXTURE_CUBE_MAP:
209 case GL_TEXTURE_CUBE_MAP_ARRAY:
210 case GL_TEXTURE_2D_MULTISAMPLE:
211 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
212 align_yf = align_2d_yf;
213 align_ys = align_2d_ys;
214 break;
215 case GL_TEXTURE_3D:
216 align_yf = align_3d_yf;
217 align_ys = align_3d_ys;
218 break;
219 default:
220 unreachable("not reached");
221 }
222
223 /* Compute array index. */
224 i = ffs(bpp / 8) - 1;
225
226 ret_align = mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
227 align_yf[i] : align_ys[i];
228
229 assert(_mesa_is_pow_two(mt->num_samples));
230
231 switch (mt->num_samples) {
232 case 4:
233 case 8:
234 divisor = 2;
235 break;
236 case 16:
237 divisor = 4;
238 break;
239 default:
240 divisor = 1;
241 break;
242 }
243 return ret_align / divisor;
244 }
245
246 static unsigned int
247 intel_vertical_texture_alignment_unit(struct brw_context *brw,
248 const struct intel_mipmap_tree *mt)
249 {
250 /**
251 * From the "Alignment Unit Size" section of various specs, namely:
252 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
253 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
254 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
255 * - BSpec (for Ivybridge and slight variations in separate stencil)
256 *
257 * +----------------------------------------------------------------------+
258 * | | alignment unit height ("j") |
259 * | Surface Property |-----------------------------|
260 * | | 915 | 965 | ILK | SNB | IVB |
261 * +----------------------------------------------------------------------+
262 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
263 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
264 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
265 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
266 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
267 * | All Others | 2 | 2 | 2 | * | * |
268 * +----------------------------------------------------------------------+
269 *
270 * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
271 * the SURFACE_STATE "Surface Vertical Alignment" field.
272 */
273 if (_mesa_is_format_compressed(mt->format))
274 /* See comment above for the horizontal alignment */
275 return brw->gen >= 9 ? 16 : 4;
276
277 if (mt->format == MESA_FORMAT_S_UINT8)
278 return brw->gen >= 7 ? 8 : 4;
279
280 if (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
281 uint32_t align = tr_mode_vertical_texture_alignment(brw, mt);
282 /* XY_FAST_COPY_BLT doesn't support vertical alignment < 64 */
283 return align < 64 ? 64 : align;
284 }
285
286 /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
287 * should always be used, except for stencil buffers, which should be 8.
288 */
289 if (brw->gen >= 8)
290 return 4;
291
292 if (mt->num_samples > 1)
293 return 4;
294
295 GLenum base_format = _mesa_get_format_base_format(mt->format);
296
297 if (brw->gen >= 6 &&
298 (base_format == GL_DEPTH_COMPONENT ||
299 base_format == GL_DEPTH_STENCIL)) {
300 return 4;
301 }
302
303 if (brw->gen == 7) {
304 /* On Gen7, we prefer a vertical alignment of 4 when possible, because
305 * that allows Y tiled render targets.
306 *
307 * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
308 * messages), on p64, under the heading "Surface Vertical Alignment":
309 *
310 * Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
311 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
312 * (0x190)
313 *
314 * VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
315 */
316 if (base_format == GL_YCBCR_MESA || mt->format == MESA_FORMAT_RGB_FLOAT32)
317 return 2;
318
319 return 4;
320 }
321
322 return 2;
323 }
324
325 static void
326 gen9_miptree_layout_1d(struct intel_mipmap_tree *mt)
327 {
328 unsigned x = 0;
329 unsigned width = mt->physical_width0;
330 unsigned depth = mt->physical_depth0; /* number of array layers. */
331
332 /* When this layout is used the horizontal alignment is fixed at 64 and the
333 * hardware ignores the value given in the surface state
334 */
335 const unsigned int align_w = 64;
336
337 mt->total_height = mt->physical_height0;
338 mt->total_width = 0;
339
340 for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
341 unsigned img_width;
342
343 intel_miptree_set_level_info(mt, level, x, 0, depth);
344
345 img_width = ALIGN(width, align_w);
346
347 mt->total_width = MAX2(mt->total_width, x + img_width);
348
349 x += img_width;
350
351 width = minify(width, 1);
352 }
353 }
354
355 static void
356 brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
357 {
358 unsigned x = 0;
359 unsigned y = 0;
360 unsigned width = mt->physical_width0;
361 unsigned height = mt->physical_height0;
362 unsigned depth = mt->physical_depth0; /* number of array layers. */
363 unsigned int bw, bh;
364
365 _mesa_get_format_block_size(mt->format, &bw, &bh);
366
367 mt->total_width = mt->physical_width0;
368
369 if (mt->compressed)
370 mt->total_width = ALIGN(mt->total_width, bw);
371
372 /* May need to adjust width to accommodate the placement of
373 * the 2nd mipmap. This occurs when the alignment
374 * constraints of mipmap placement push the right edge of the
375 * 2nd mipmap out past the width of its parent.
376 */
377 if (mt->first_level != mt->last_level) {
378 unsigned mip1_width;
379
380 if (mt->compressed) {
381 mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
382 ALIGN(minify(mt->physical_width0, 2), bw);
383 } else {
384 mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
385 minify(mt->physical_width0, 2);
386 }
387
388 if (mip1_width > mt->total_width) {
389 mt->total_width = mip1_width;
390 }
391 }
392
393 mt->total_height = 0;
394
395 for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
396 unsigned img_height;
397
398 intel_miptree_set_level_info(mt, level, x, y, depth);
399
400 img_height = ALIGN(height, mt->align_h);
401 if (mt->compressed)
402 img_height /= bh;
403
404 if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
405 /* Compact arrays with separated miplevels */
406 img_height *= depth;
407 }
408
409 /* Because the images are packed better, the final offset
410 * might not be the maximal one:
411 */
412 mt->total_height = MAX2(mt->total_height, y + img_height);
413
414 /* Layout_below: step right after second mipmap.
415 */
416 if (level == mt->first_level + 1) {
417 x += ALIGN(width, mt->align_w);
418 } else {
419 y += img_height;
420 }
421
422 width = minify(width, 1);
423 height = minify(height, 1);
424
425 if (mt->target == GL_TEXTURE_3D)
426 depth = minify(depth, 1);
427 }
428 }
429
430 unsigned
431 brw_miptree_get_horizontal_slice_pitch(const struct brw_context *brw,
432 const struct intel_mipmap_tree *mt,
433 unsigned level)
434 {
435 assert(brw->gen < 9);
436
437 if (mt->target == GL_TEXTURE_3D ||
438 (brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP)) {
439 return ALIGN(minify(mt->physical_width0, level), mt->align_w);
440 } else {
441 return 0;
442 }
443 }
444
445 unsigned
446 brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
447 const struct intel_mipmap_tree *mt,
448 unsigned level)
449 {
450 if (brw->gen >= 9) {
451 /* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
452 * effectively end up with a packed qpitch anyway whenever
453 * mt->first_level == mt->last_level.
454 */
455 assert(mt->array_layout != ALL_SLICES_AT_EACH_LOD);
456
457 /* On Gen9 we can pick whatever qpitch we like as long as it's aligned
458 * to the vertical alignment so we don't need to add any extra rows.
459 */
460 unsigned qpitch = mt->total_height;
461
462 /* If the surface might be used as a stencil buffer or HiZ buffer then
463 * it needs to be a multiple of 8.
464 */
465 const GLenum base_format = _mesa_get_format_base_format(mt->format);
466 if (_mesa_is_depth_or_stencil_format(base_format))
467 qpitch = ALIGN(qpitch, 8);
468
469 /* 3D textures need to be aligned to the tile height. At this point we
470 * don't know which tiling will be used so let's just align it to 32
471 */
472 if (mt->target == GL_TEXTURE_3D)
473 qpitch = ALIGN(qpitch, 32);
474
475 return qpitch;
476
477 } else if (mt->target == GL_TEXTURE_3D ||
478 (brw->gen == 4 && mt->target == GL_TEXTURE_CUBE_MAP) ||
479 mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
480 return ALIGN(minify(mt->physical_height0, level), mt->align_h);
481
482 } else {
483 const unsigned h0 = ALIGN(mt->physical_height0, mt->align_h);
484 const unsigned h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
485
486 return h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->align_h;
487 }
488 }
489
490 static void
491 align_cube(struct intel_mipmap_tree *mt)
492 {
493 /* The 965's sampler lays cachelines out according to how accesses
494 * in the texture surfaces run, so they may be "vertical" through
495 * memory. As a result, the docs say in Surface Padding Requirements:
496 * Sampling Engine Surfaces that two extra rows of padding are required.
497 */
498 if (mt->target == GL_TEXTURE_CUBE_MAP)
499 mt->total_height += 2;
500 }
501
502 bool
503 gen9_use_linear_1d_layout(const struct brw_context *brw,
504 const struct intel_mipmap_tree *mt)
505 {
506 /* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
507 * horizontal line. This isn't done for depth/stencil buffers however
508 * because those will be using a tiled layout
509 */
510 if (brw->gen >= 9 &&
511 (mt->target == GL_TEXTURE_1D ||
512 mt->target == GL_TEXTURE_1D_ARRAY)) {
513 GLenum base_format = _mesa_get_format_base_format(mt->format);
514
515 if (base_format != GL_DEPTH_COMPONENT &&
516 base_format != GL_DEPTH_STENCIL &&
517 base_format != GL_STENCIL_INDEX)
518 return true;
519 }
520
521 return false;
522 }
523
524 static void
525 brw_miptree_layout_texture_array(struct brw_context *brw,
526 struct intel_mipmap_tree *mt)
527 {
528 unsigned height = mt->physical_height0;
529 bool layout_1d = gen9_use_linear_1d_layout(brw, mt);
530 int physical_qpitch;
531
532 if (layout_1d)
533 gen9_miptree_layout_1d(mt);
534 else
535 brw_miptree_layout_2d(mt);
536
537 if (layout_1d) {
538 physical_qpitch = 1;
539 /* When using the horizontal layout the qpitch specifies the distance in
540 * pixels between array slices. The total_width is forced to be a
541 * multiple of the horizontal alignment in brw_miptree_layout_1d (in
542 * this case it's always 64). The vertical alignment is ignored.
543 */
544 mt->qpitch = mt->total_width;
545 } else {
546 mt->qpitch = brw_miptree_get_vertical_slice_pitch(brw, mt, 0);
547 /* Unlike previous generations the qpitch is a multiple of the
548 * compressed block size on Gen9 so physical_qpitch matches mt->qpitch.
549 */
550 physical_qpitch = (mt->compressed && brw->gen < 9 ? mt->qpitch / 4 :
551 mt->qpitch);
552 }
553
554 for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
555 unsigned img_height;
556 img_height = ALIGN(height, mt->align_h);
557 if (mt->compressed)
558 img_height /= mt->align_h;
559
560 for (int q = 0; q < mt->level[level].depth; q++) {
561 if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
562 intel_miptree_set_image_offset(mt, level, q, 0, q * img_height);
563 } else {
564 intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch);
565 }
566 }
567 height = minify(height, 1);
568 }
569 if (mt->array_layout == ALL_LOD_IN_EACH_SLICE)
570 mt->total_height = physical_qpitch * mt->physical_depth0;
571
572 align_cube(mt);
573 }
574
575 static void
576 brw_miptree_layout_texture_3d(struct brw_context *brw,
577 struct intel_mipmap_tree *mt)
578 {
579 unsigned yscale = mt->compressed ? 4 : 1;
580
581 mt->total_width = 0;
582 mt->total_height = 0;
583
584 unsigned ysum = 0;
585 for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
586 unsigned WL = MAX2(mt->physical_width0 >> level, 1);
587 unsigned HL = MAX2(mt->physical_height0 >> level, 1);
588 unsigned DL = MAX2(mt->physical_depth0 >> level, 1);
589 unsigned wL = ALIGN(WL, mt->align_w);
590 unsigned hL = ALIGN(HL, mt->align_h);
591
592 if (mt->target == GL_TEXTURE_CUBE_MAP)
593 DL = 6;
594
595 intel_miptree_set_level_info(mt, level, 0, 0, DL);
596
597 for (unsigned q = 0; q < DL; q++) {
598 unsigned x = (q % (1 << level)) * wL;
599 unsigned y = ysum + (q >> level) * hL;
600
601 intel_miptree_set_image_offset(mt, level, q, x, y / yscale);
602 mt->total_width = MAX2(mt->total_width, x + wL);
603 mt->total_height = MAX2(mt->total_height, (y + hL) / yscale);
604 }
605
606 ysum += ALIGN(DL, 1 << level) / (1 << level) * hL;
607 }
608
609 align_cube(mt);
610 }
611
612 /**
613 * \brief Helper function for intel_miptree_create().
614 */
615 static uint32_t
616 brw_miptree_choose_tiling(struct brw_context *brw,
617 const struct intel_mipmap_tree *mt,
618 uint32_t layout_flags)
619 {
620 if (mt->format == MESA_FORMAT_S_UINT8) {
621 /* The stencil buffer is W tiled. However, we request from the kernel a
622 * non-tiled buffer because the GTT is incapable of W fencing.
623 */
624 return I915_TILING_NONE;
625 }
626
627 /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
628 assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
629
630 /* Some usages may want only one type of tiling, like depth miptrees (Y
631 * tiled), or temporary BOs for uploading data once (linear).
632 */
633 switch (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) {
634 case MIPTREE_LAYOUT_ALLOC_ANY_TILED:
635 break;
636 case MIPTREE_LAYOUT_ALLOC_YTILED:
637 return I915_TILING_Y;
638 case MIPTREE_LAYOUT_ALLOC_LINEAR:
639 return I915_TILING_NONE;
640 }
641
642 if (mt->num_samples > 1) {
643 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
644 * Surface"):
645 *
646 * [DevSNB+]: For multi-sample render targets, this field must be
647 * 1. MSRTs can only be tiled.
648 *
649 * Our usual reason for preferring X tiling (fast blits using the
650 * blitting engine) doesn't apply to MSAA, since we'll generally be
651 * downsampling or upsampling when blitting between the MSAA buffer
652 * and another buffer, and the blitting engine doesn't support that.
653 * So use Y tiling, since it makes better use of the cache.
654 */
655 return I915_TILING_Y;
656 }
657
658 GLenum base_format = _mesa_get_format_base_format(mt->format);
659 if (base_format == GL_DEPTH_COMPONENT ||
660 base_format == GL_DEPTH_STENCIL_EXT)
661 return I915_TILING_Y;
662
663 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
664 * in fact it leads to a less efficient use of memory space and bandwidth
665 * due to tile alignment.
666 */
667 if (mt->logical_height0 == 1)
668 return I915_TILING_NONE;
669
670 int minimum_pitch = mt->total_width * mt->cpp;
671
672 /* If the width is much smaller than a tile, don't bother tiling. */
673 if (minimum_pitch < 64)
674 return I915_TILING_NONE;
675
676 if (ALIGN(minimum_pitch, 512) >= 32768 ||
677 mt->total_width >= 32768 || mt->total_height >= 32768) {
678 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
679 mt->total_width, mt->total_height);
680 return I915_TILING_NONE;
681 }
682
683 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
684 if (brw->gen < 6)
685 return I915_TILING_X;
686
687 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
688 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
689 * or Linear."
690 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
691 * all the way back to 965, but is permitted on Gen7+.
692 */
693 if (brw->gen < 7 && mt->cpp >= 16)
694 return I915_TILING_X;
695
696 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
697 * messages), on p64, under the heading "Surface Vertical Alignment":
698 *
699 * This field must be set to VALIGN_4 for all tiled Y Render Target
700 * surfaces.
701 *
702 * So if the surface is renderable and uses a vertical alignment of 2,
703 * force it to be X tiled. This is somewhat conservative (it's possible
704 * that the client won't ever render to this surface), but it's difficult
705 * to know that ahead of time. And besides, since we use a vertical
706 * alignment of 4 as often as we can, this shouldn't happen very often.
707 */
708 if (brw->gen == 7 && mt->align_h == 2 &&
709 brw->format_supported_as_render_target[mt->format]) {
710 return I915_TILING_X;
711 }
712
713 return I915_TILING_Y | I915_TILING_X;
714 }
715
716 static void
717 intel_miptree_set_total_width_height(struct brw_context *brw,
718 struct intel_mipmap_tree *mt)
719 {
720 switch (mt->target) {
721 case GL_TEXTURE_CUBE_MAP:
722 if (brw->gen == 4) {
723 /* Gen4 stores cube maps as 3D textures. */
724 assert(mt->physical_depth0 == 6);
725 brw_miptree_layout_texture_3d(brw, mt);
726 } else {
727 /* All other hardware stores cube maps as 2D arrays. */
728 brw_miptree_layout_texture_array(brw, mt);
729 }
730 break;
731
732 case GL_TEXTURE_3D:
733 if (brw->gen >= 9)
734 brw_miptree_layout_texture_array(brw, mt);
735 else
736 brw_miptree_layout_texture_3d(brw, mt);
737 break;
738
739 case GL_TEXTURE_1D_ARRAY:
740 case GL_TEXTURE_2D_ARRAY:
741 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
742 case GL_TEXTURE_CUBE_MAP_ARRAY:
743 brw_miptree_layout_texture_array(brw, mt);
744 break;
745
746 default:
747 switch (mt->msaa_layout) {
748 case INTEL_MSAA_LAYOUT_UMS:
749 case INTEL_MSAA_LAYOUT_CMS:
750 brw_miptree_layout_texture_array(brw, mt);
751 break;
752 case INTEL_MSAA_LAYOUT_NONE:
753 case INTEL_MSAA_LAYOUT_IMS:
754 if (gen9_use_linear_1d_layout(brw, mt))
755 gen9_miptree_layout_1d(mt);
756 else
757 brw_miptree_layout_2d(mt);
758 break;
759 }
760 break;
761 }
762
763 DBG("%s: %dx%dx%d\n", __func__,
764 mt->total_width, mt->total_height, mt->cpp);
765 }
766
767 static void
768 intel_miptree_set_alignment(struct brw_context *brw,
769 struct intel_mipmap_tree *mt,
770 uint32_t layout_flags)
771 {
772 bool gen6_hiz_or_stencil = false;
773
774 if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
775 const GLenum base_format = _mesa_get_format_base_format(mt->format);
776 gen6_hiz_or_stencil = _mesa_is_depth_or_stencil_format(base_format);
777 }
778
779 if (gen6_hiz_or_stencil) {
780 /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
781 * hardware doesn't support multiple mip levels on stencil/hiz.
782 *
783 * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
784 * "The hierarchical depth buffer does not support the LOD field"
785 *
786 * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
787 * "The stencil depth buffer does not support the LOD field"
788 */
789 if (mt->format == MESA_FORMAT_S_UINT8) {
790 /* Stencil uses W tiling, so we force W tiling alignment for the
791 * ALL_SLICES_AT_EACH_LOD miptree layout.
792 */
793 mt->align_w = 64;
794 mt->align_h = 64;
795 assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
796 } else {
797 /* Depth uses Y tiling, so we force need Y tiling alignment for the
798 * ALL_SLICES_AT_EACH_LOD miptree layout.
799 */
800 mt->align_w = 128 / mt->cpp;
801 mt->align_h = 32;
802 }
803 } else {
804 mt->align_w =
805 intel_horizontal_texture_alignment_unit(brw, mt, layout_flags);
806 mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
807 }
808 }
809
810 void
811 brw_miptree_layout(struct brw_context *brw,
812 struct intel_mipmap_tree *mt,
813 uint32_t layout_flags)
814 {
815 mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
816
817 intel_miptree_set_alignment(brw, mt, layout_flags);
818 intel_miptree_set_total_width_height(brw, mt);
819
820 if (!mt->total_width || !mt->total_height) {
821 intel_miptree_release(&mt);
822 return;
823 }
824
825 /* On Gen9+ the alignment values are expressed in multiples of the block
826 * size
827 */
828 if (brw->gen >= 9) {
829 unsigned int i, j;
830 _mesa_get_format_block_size(mt->format, &i, &j);
831 mt->align_w /= i;
832 mt->align_h /= j;
833 }
834
835 if ((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0)
836 mt->tiling = brw_miptree_choose_tiling(brw, mt, layout_flags);
837 }
838