2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 /* Code to layout images in a mipmap tree for i965.
35 #include "intel_mipmap_tree.h"
36 #include "intel_tex_layout.h"
37 #include "intel_context.h"
38 #include "main/macros.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
42 GLboolean
brw_miptree_layout(struct intel_context
*intel
,
43 struct intel_mipmap_tree
*mt
,
46 /* XXX: these vary depending on image format: */
47 /* GLint align_w = 4; */
50 case GL_TEXTURE_CUBE_MAP
:
51 if (intel
->is_ironlake
) {
52 GLuint align_h
= 2, align_w
= 4;
56 GLuint width
= mt
->width0
;
57 GLuint height
= mt
->height0
;
61 mt
->total_width
= mt
->width0
;
62 intel_get_texture_alignment_unit(mt
->internal_format
, &align_w
, &align_h
);
63 y_pitch
= ALIGN(height
, align_h
);
66 mt
->total_width
= ALIGN(mt
->width0
, align_w
);
69 if (mt
->first_level
!= mt
->last_level
) {
73 mip1_width
= ALIGN(minify(mt
->width0
), align_w
)
74 + ALIGN(minify(minify(mt
->width0
)), align_w
);
76 mip1_width
= ALIGN(minify(mt
->width0
), align_w
)
77 + minify(minify(mt
->width0
));
80 if (mip1_width
> mt
->total_width
) {
81 mt
->total_width
= mip1_width
;
86 qpitch
= (y_pitch
+ ALIGN(minify(y_pitch
), align_h
) + 11 * align_h
) / 4;
87 mt
->total_height
= (y_pitch
+ ALIGN(minify(y_pitch
), align_h
) + 11 * align_h
) / 4 * 6;
89 qpitch
= (y_pitch
+ ALIGN(minify(y_pitch
), align_h
) + 11 * align_h
);
90 mt
->total_height
= (y_pitch
+ ALIGN(minify(y_pitch
), align_h
) + 11 * align_h
) * 6;
93 for (level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
98 intel_miptree_set_level_info(mt
, level
, nr_images
, x
, y
, width
,
101 for (q
= 0; q
< nr_images
; q
++)
102 intel_miptree_set_image_offset(mt
, level
, q
,
106 img_height
= MAX2(1, height
/4);
108 img_height
= ALIGN(height
, align_h
);
110 if (level
== mt
->first_level
+ 1) {
111 x
+= ALIGN(width
, align_w
);
117 width
= minify(width
);
118 height
= minify(height
);
124 case GL_TEXTURE_3D
: {
125 GLuint width
= mt
->width0
;
126 GLuint height
= mt
->height0
;
127 GLuint depth
= mt
->depth0
;
128 GLuint pack_x_pitch
, pack_x_nr
;
134 mt
->total_height
= 0;
135 intel_get_texture_alignment_unit(mt
->internal_format
, &align_w
, &align_h
);
137 if (mt
->compressed
) {
138 mt
->total_width
= ALIGN(width
, align_w
);
139 pack_y_pitch
= (height
+ 3) / 4;
141 mt
->total_width
= mt
->width0
;
142 pack_y_pitch
= ALIGN(mt
->height0
, align_h
);
145 pack_x_pitch
= width
;
148 for (level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
149 GLuint nr_images
= mt
->target
== GL_TEXTURE_3D
? depth
: 6;
154 intel_miptree_set_level_info(mt
, level
, nr_images
,
156 width
, height
, depth
);
158 for (q
= 0; q
< nr_images
;) {
159 for (j
= 0; j
< pack_x_nr
&& q
< nr_images
; j
++, q
++) {
160 intel_miptree_set_image_offset(mt
, level
, q
, x
, y
);
169 mt
->total_height
+= y
;
170 width
= minify(width
);
171 height
= minify(height
);
172 depth
= minify(depth
);
174 if (mt
->compressed
) {
175 pack_y_pitch
= (height
+ 3) / 4;
177 if (pack_x_pitch
> ALIGN(width
, align_w
)) {
178 pack_x_pitch
= ALIGN(width
, align_w
);
182 if (pack_x_pitch
> 4) {
185 assert(pack_x_pitch
* pack_x_nr
<= mt
->total_width
);
188 if (pack_y_pitch
> 2) {
190 pack_y_pitch
= ALIGN(pack_y_pitch
, align_h
);
195 /* The 965's sampler lays cachelines out according to how accesses
196 * in the texture surfaces run, so they may be "vertical" through
197 * memory. As a result, the docs say in Surface Padding Requirements:
198 * Sampling Engine Surfaces that two extra rows of padding are required.
199 * We don't know of similar requirements for pre-965, but given that
200 * those docs are silent on padding requirements in general, let's play
203 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
204 mt
->total_height
+= 2;
209 i945_miptree_layout_2d(intel
, mt
, tiling
);
212 DBG("%s: %dx%dx%d\n", __FUNCTION__
,
213 mt
->total_width
, mt
->total_height
, mt
->cpp
);