2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "brw_context.h"
36 #include "brw_state.h"
37 #include "brw_defines.h"
46 /* XXX: Are the min_entry_size numbers useful?
47 * XXX: Verify min_nr_entries, esp for VS.
48 * XXX: Verify SF min_entry_size.
51 GLuint min_nr_entries
;
52 GLuint preferred_nr_entries
;
53 GLuint min_entry_size
;
54 GLuint max_entry_size
;
56 { 8, 16, 1, 5 }, /* vs */
57 { 4, 8, 1, 5 }, /* gs */
58 { 6, 12, 1, 5 }, /* clp */
59 { 1, 8, 1, 12 }, /* sf */
60 { 1, 4, 1, 32 } /* cs */
64 static GLboolean
check_urb_layout( struct brw_context
*brw
)
66 brw
->urb
.vs_start
= 0;
67 brw
->urb
.gs_start
= brw
->urb
.nr_vs_entries
* brw
->urb
.vsize
;
68 brw
->urb
.clip_start
= brw
->urb
.gs_start
+ brw
->urb
.nr_gs_entries
* brw
->urb
.vsize
;
69 brw
->urb
.sf_start
= brw
->urb
.clip_start
+ brw
->urb
.nr_clip_entries
* brw
->urb
.vsize
;
70 brw
->urb
.cs_start
= brw
->urb
.sf_start
+ brw
->urb
.nr_sf_entries
* brw
->urb
.sfsize
;
72 return brw
->urb
.cs_start
+ brw
->urb
.nr_cs_entries
* brw
->urb
.csize
<= 256;
75 /* Most minimal update, forces re-emit of URB fence packet after GS
78 static void recalculate_urb_fence( struct brw_context
*brw
)
80 GLuint csize
= brw
->curbe
.total_size
;
81 GLuint vsize
= brw
->vs
.prog_data
->urb_entry_size
;
82 GLuint sfsize
= brw
->sf
.prog_data
->urb_entry_size
;
84 static GLboolean (*hal_recalculate_urb_fence
) (struct brw_context
*brw
);
85 static GLboolean hal_tried
;
89 hal_recalculate_urb_fence
= brw_hal_find_symbol ("intel_hal_recalculate_urb_fence");
92 if (hal_recalculate_urb_fence
)
94 if ((*hal_recalculate_urb_fence
) (brw
))
98 if (csize
< limits
[CS
].min_entry_size
)
99 csize
= limits
[CS
].min_entry_size
;
101 if (vsize
< limits
[VS
].min_entry_size
)
102 vsize
= limits
[VS
].min_entry_size
;
104 if (sfsize
< limits
[SF
].min_entry_size
)
105 sfsize
= limits
[SF
].min_entry_size
;
107 if (brw
->urb
.vsize
< vsize
||
108 brw
->urb
.sfsize
< sfsize
||
109 brw
->urb
.csize
< csize
||
110 (brw
->urb
.constrained
&& (brw
->urb
.vsize
> brw
->urb
.vsize
||
111 brw
->urb
.sfsize
> brw
->urb
.sfsize
||
112 brw
->urb
.csize
> brw
->urb
.csize
))) {
115 brw
->urb
.csize
= csize
;
116 brw
->urb
.sfsize
= sfsize
;
117 brw
->urb
.vsize
= vsize
;
119 brw
->urb
.nr_vs_entries
= limits
[VS
].preferred_nr_entries
;
120 brw
->urb
.nr_gs_entries
= limits
[GS
].preferred_nr_entries
;
121 brw
->urb
.nr_clip_entries
= limits
[CLP
].preferred_nr_entries
;
122 brw
->urb
.nr_sf_entries
= limits
[SF
].preferred_nr_entries
;
123 brw
->urb
.nr_cs_entries
= limits
[CS
].preferred_nr_entries
;
125 if (!check_urb_layout(brw
)) {
126 brw
->urb
.nr_vs_entries
= limits
[VS
].min_nr_entries
;
127 brw
->urb
.nr_gs_entries
= limits
[GS
].min_nr_entries
;
128 brw
->urb
.nr_clip_entries
= limits
[CLP
].min_nr_entries
;
129 brw
->urb
.nr_sf_entries
= limits
[SF
].min_nr_entries
;
130 brw
->urb
.nr_cs_entries
= limits
[CS
].min_nr_entries
;
132 brw
->urb
.constrained
= 1;
134 if (check_urb_layout(brw
)) {
135 /* This is impossible, given the maximal sizes of urb
136 * entries and the values for minimum nr of entries
139 _mesa_printf("couldn't calculate URB layout!\n");
143 if (INTEL_DEBUG
& (DEBUG_URB
|DEBUG_FALLBACKS
))
144 _mesa_printf("URB CONSTRAINED\n");
147 brw
->urb
.constrained
= 0;
149 if (INTEL_DEBUG
& DEBUG_URB
)
150 _mesa_printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
158 brw
->state
.dirty
.brw
|= BRW_NEW_URB_FENCE
;
163 const struct brw_tracked_state brw_recalculate_urb_fence
= {
166 .brw
= BRW_NEW_CURBE_OFFSETS
,
167 .cache
= (CACHE_NEW_VS_PROG
|
170 .update
= recalculate_urb_fence
177 void brw_upload_urb_fence(struct brw_context
*brw
)
179 struct brw_urb_fence uf
;
180 memset(&uf
, 0, sizeof(uf
));
182 uf
.header
.opcode
= CMD_URB_FENCE
;
183 uf
.header
.length
= sizeof(uf
)/4-2;
184 uf
.header
.vs_realloc
= 1;
185 uf
.header
.gs_realloc
= 1;
186 uf
.header
.clp_realloc
= 1;
187 uf
.header
.sf_realloc
= 1;
188 uf
.header
.vfe_realloc
= 1;
189 uf
.header
.cs_realloc
= 1;
191 /* The ordering below is correct, not the layout in the
194 * There are 256 urb reg pairs in total.
196 uf
.bits0
.vs_fence
= brw
->urb
.gs_start
;
197 uf
.bits0
.gs_fence
= brw
->urb
.clip_start
;
198 uf
.bits0
.clp_fence
= brw
->urb
.sf_start
;
199 uf
.bits1
.sf_fence
= brw
->urb
.cs_start
;
200 uf
.bits1
.cs_fence
= 256;
202 BRW_BATCH_STRUCT(brw
, &uf
);
207 const struct brw_tracked_state brw_urb_fence
= {
210 .brw
= BRW_NEW_URB_FENCE
| BRW_NEW_PSP
,
213 .update
= brw_upload_urb_fence