src/mesa/drivers/dri/i965/brw_urb.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38
  39 #define VS 0
  40 #define GS 1
  41 #define CLP 2
  42 #define SF 3
  43 #define CS 4
  44
  45 /** @file brw_urb.c
  46  *
  47  * Manages the division of the URB space between the various fixed-function
  48  * units.
  49  *
  50  * See the Thread Initiation Management section of the GEN4 B-Spec, and
  51  * the individual *_STATE structures for restrictions on numbers of
  52  * entries and threads.
  53  */
  54
  55 /*
  56  * Generally, a unit requires a min_nr_entries based on how many entries
  57  * it produces before the downstream unit gets unblocked and can use and
  58  * dereference some of its handles.
  59  *
  60  * The SF unit preallocates a PUE at the start of thread dispatch, and only
  61  * uses that one.  So it requires one entry per thread.
  62  *
  63  * For CLIP, the SF unit will hold the previous primitive while the
  64  * next is getting assembled, meaning that linestrips require 3 CLIP VUEs
  65  * (vertices) to ensure continued processing, trifans require 4, and tristrips
  66  * require 5.  There can be 1 or 2 threads, and each has the same requirement.
  67  *
  68  * GS has the same requirement as CLIP, but it never handles tristrips,
  69  * so we can lower the minimum to 4 for the POLYGONs (trifans) it produces.
  70  * We only run it single-threaded.
  71  *
  72  * For VS, the number of entries may be 8, 12, 16, or 32 (or 64 on G4X).
  73  * Each thread processes 2 preallocated VUEs (vertices) at a time, and they
  74  * get streamed down as soon as threads processing earlier vertices get
  75  * theirs accepted.
  76  *
  77  * Each unit will take the number of URB entries we give it (based on the
  78  * entry size calculated in brw_vs_emit.c for VUEs, brw_sf_emit.c for PUEs,
  79  * and brw_curbe.c for the CURBEs) and decide its maximum number of
  80  * threads it can support based on that. in brw_*_state.c.
  81  *
  82  * XXX: Are the min_entry_size numbers useful?
  83  * XXX: Verify min_nr_entries, esp for VS.
  84  * XXX: Verify SF min_entry_size.
  85  */
  86 static const struct {
  87    GLuint min_nr_entries;
  88    GLuint preferred_nr_entries;
  89    GLuint min_entry_size;
  90    GLuint max_entry_size;
  91 } limits[CS+1] = {
  92    { 16, 32, 1, 5 },                    /* vs */
  93    { 4, 8,  1, 5 },                     /* gs */
  94    { 5, 10,  1, 5 },                    /* clp */
  95    { 1, 8,  1, 12 },                    /* sf */
  96    { 1, 4,  1, 32 }                     /* cs */
  97 };
  98
  99
 100 static GLboolean check_urb_layout( struct brw_context *brw )
 101 {
 102    brw->urb.vs_start = 0;
 103    brw->urb.gs_start = brw->urb.nr_vs_entries * brw->urb.vsize;
 104    brw->urb.clip_start = brw->urb.gs_start + brw->urb.nr_gs_entries * brw->urb.vsize;
 105    brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize;
 106    brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize;
 107
 108    return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= URB_SIZES(brw);
 109 }
 110
 111 /* Most minimal update, forces re-emit of URB fence packet after GS
 112  * unit turned on/off.
 113  */
 114 static void recalculate_urb_fence( struct brw_context *brw )
 115 {
 116    GLuint csize = brw->curbe.total_size;
 117    GLuint vsize = brw->vs.prog_data->urb_entry_size;
 118    GLuint sfsize = brw->sf.prog_data->urb_entry_size;
 119
 120    if (csize < limits[CS].min_entry_size)
 121       csize = limits[CS].min_entry_size;
 122
 123    if (vsize < limits[VS].min_entry_size)
 124       vsize = limits[VS].min_entry_size;
 125
 126    if (sfsize < limits[SF].min_entry_size)
 127       sfsize = limits[SF].min_entry_size;
 128
 129    if (brw->urb.vsize < vsize ||
 130        brw->urb.sfsize < sfsize ||
 131        brw->urb.csize < csize ||
 132        (brw->urb.constrained && (brw->urb.vsize > vsize ||
 133                                  brw->urb.sfsize > sfsize ||
 134                                  brw->urb.csize > csize))) {
 135
 136
 137       brw->urb.csize = csize;
 138       brw->urb.sfsize = sfsize;
 139       brw->urb.vsize = vsize;
 140
 141       brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
 142       brw->urb.nr_gs_entries = limits[GS].preferred_nr_entries;
 143       brw->urb.nr_clip_entries = limits[CLP].preferred_nr_entries;
 144       brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
 145       brw->urb.nr_cs_entries = limits[CS].preferred_nr_entries;
 146
 147       brw->urb.constrained = 0;
 148
 149       if (BRW_IS_IGDNG(brw)) {
 150          brw->urb.nr_vs_entries = 128;
 151          brw->urb.nr_sf_entries = 48;
 152          if (check_urb_layout(brw)) {
 153             goto done;
 154          } else {
 155             brw->urb.constrained = 1;
 156             brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
 157             brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
 158          }
 159       } else if (BRW_IS_G4X(brw)) {
 160          brw->urb.nr_vs_entries = 64;
 161          if (check_urb_layout(brw)) {
 162             goto done;
 163          } else {
 164             brw->urb.constrained = 1;
 165             brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
 166          }
 167       }
 168
 169       if (!check_urb_layout(brw)) {
 170          brw->urb.nr_vs_entries = limits[VS].min_nr_entries;
 171          brw->urb.nr_gs_entries = limits[GS].min_nr_entries;
 172          brw->urb.nr_clip_entries = limits[CLP].min_nr_entries;
 173          brw->urb.nr_sf_entries = limits[SF].min_nr_entries;
 174          brw->urb.nr_cs_entries = limits[CS].min_nr_entries;
 175
 176          /* Mark us as operating with constrained nr_entries, so that next
 177           * time we recalculate we'll resize the fences in the hope of
 178           * escaping constrained mode and getting back to normal performance.
 179           */
 180          brw->urb.constrained = 1;
 181
 182          if (!check_urb_layout(brw)) {
 183             /* This is impossible, given the maximal sizes of urb
 184              * entries and the values for minimum nr of entries
 185              * provided above.
 186              */
 187             _mesa_printf("couldn't calculate URB layout!\n");
 188             exit(1);
 189          }
 190
 191          if (INTEL_DEBUG & (DEBUG_URB|DEBUG_FALLBACKS))
 192             _mesa_printf("URB CONSTRAINED\n");
 193       }
 194
 195 done:
 196       if (INTEL_DEBUG & DEBUG_URB)
 197          _mesa_printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
 198                       brw->urb.vs_start,
 199                       brw->urb.gs_start,
 200                       brw->urb.clip_start,
 201                       brw->urb.sf_start,
 202                       brw->urb.cs_start,
 203                       URB_SIZES(brw));
 204
 205       brw->state.dirty.brw |= BRW_NEW_URB_FENCE;
 206    }
 207 }
 208
 209
 210 const struct brw_tracked_state brw_recalculate_urb_fence = {
 211    .dirty = {
 212       .mesa = 0,
 213       .brw = BRW_NEW_CURBE_OFFSETS,
 214       .cache = (CACHE_NEW_VS_PROG |
 215                 CACHE_NEW_SF_PROG)
 216    },
 217    .prepare = recalculate_urb_fence
 218 };
 219
 220
 221
 222
 223
 224 void brw_upload_urb_fence(struct brw_context *brw)
 225 {
 226    struct brw_urb_fence uf;
 227    memset(&uf, 0, sizeof(uf));
 228
 229    uf.header.opcode = CMD_URB_FENCE;
 230    uf.header.length = sizeof(uf)/4-2;
 231    uf.header.vs_realloc = 1;
 232    uf.header.gs_realloc = 1;
 233    uf.header.clp_realloc = 1;
 234    uf.header.sf_realloc = 1;
 235    uf.header.vfe_realloc = 1;
 236    uf.header.cs_realloc = 1;
 237
 238    /* The ordering below is correct, not the layout in the
 239     * instruction.
 240     *
 241     * There are 256/384 urb reg pairs in total.
 242     */
 243    uf.bits0.vs_fence  = brw->urb.gs_start;
 244    uf.bits0.gs_fence  = brw->urb.clip_start;
 245    uf.bits0.clp_fence = brw->urb.sf_start;
 246    uf.bits1.sf_fence  = brw->urb.cs_start;
 247    uf.bits1.cs_fence  = URB_SIZES(brw);
 248
 249    BRW_BATCH_STRUCT(brw, &uf);
 250 }