src/mesa/drivers/dri/i965/brw_urb.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38
  39 #define VS 0
  40 #define GS 1
  41 #define CLP 2
  42 #define SF 3
  43 #define CS 4
  44
  45 /* XXX: Are the min_entry_size numbers useful?
  46  * XXX: Verify min_nr_entries, esp for VS.
  47  * XXX: Verify SF min_entry_size.
  48  */
  49 static const struct {
  50    GLuint min_nr_entries;
  51    GLuint preferred_nr_entries;
  52    GLuint min_entry_size;
  53    GLuint max_entry_size;
  54 } limits[CS+1] = {
  55    { 8, 32, 1, 5 },                     /* vs */
  56    { 4, 8,  1, 5 },                     /* gs */
  57    { 6, 8,  1, 5 },                     /* clp */
  58    { 1, 8,  1, 12 },                    /* sf */
  59    { 1, 4,  1, 32 }                     /* cs */
  60 };
  61
  62
  63 static GLboolean check_urb_layout( struct brw_context *brw )
  64 {
  65    brw->urb.vs_start = 0;
  66    brw->urb.gs_start = brw->urb.nr_vs_entries * brw->urb.vsize;
  67    brw->urb.clip_start = brw->urb.gs_start + brw->urb.nr_gs_entries * brw->urb.vsize;
  68    brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize;
  69    brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize;
  70
  71    return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= URB_SIZES(brw);
  72 }
  73
  74 /* Most minimal update, forces re-emit of URB fence packet after GS
  75  * unit turned on/off.
  76  */
  77 static void recalculate_urb_fence( struct brw_context *brw )
  78 {
  79    GLuint csize = brw->curbe.total_size;
  80    GLuint vsize = brw->vs.prog_data->urb_entry_size;
  81    GLuint sfsize = brw->sf.prog_data->urb_entry_size;
  82
  83    if (csize < limits[CS].min_entry_size)
  84       csize = limits[CS].min_entry_size;
  85
  86    if (vsize < limits[VS].min_entry_size)
  87       vsize = limits[VS].min_entry_size;
  88
  89    if (sfsize < limits[SF].min_entry_size)
  90       sfsize = limits[SF].min_entry_size;
  91
  92    if (brw->urb.vsize < vsize ||
  93        brw->urb.sfsize < sfsize ||
  94        brw->urb.csize < csize ||
  95        (brw->urb.constrained && (brw->urb.vsize > brw->urb.vsize ||
  96                                  brw->urb.sfsize > brw->urb.sfsize ||
  97                                  brw->urb.csize > brw->urb.csize))) {
  98
  99
 100       brw->urb.csize = csize;
 101       brw->urb.sfsize = sfsize;
 102       brw->urb.vsize = vsize;
 103
 104       brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
 105       brw->urb.nr_gs_entries = limits[GS].preferred_nr_entries;
 106       brw->urb.nr_clip_entries = limits[CLP].preferred_nr_entries;
 107       brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
 108       brw->urb.nr_cs_entries = limits[CS].preferred_nr_entries;
 109
 110       if (!check_urb_layout(brw)) {
 111          brw->urb.nr_vs_entries = limits[VS].min_nr_entries;
 112          brw->urb.nr_gs_entries = limits[GS].min_nr_entries;
 113          brw->urb.nr_clip_entries = limits[CLP].min_nr_entries;
 114          brw->urb.nr_sf_entries = limits[SF].min_nr_entries;
 115          brw->urb.nr_cs_entries = limits[CS].min_nr_entries;
 116
 117          brw->urb.constrained = 1;
 118
 119          if (!check_urb_layout(brw)) {
 120             /* This is impossible, given the maximal sizes of urb
 121              * entries and the values for minimum nr of entries
 122              * provided above.
 123              */
 124             _mesa_printf("couldn't calculate URB layout!\n");
 125             exit(1);
 126          }
 127
 128          if (INTEL_DEBUG & (DEBUG_URB|DEBUG_FALLBACKS))
 129             _mesa_printf("URB CONSTRAINED\n");
 130       }
 131       else
 132          brw->urb.constrained = 0;
 133
 134       if (INTEL_DEBUG & DEBUG_URB)
 135          _mesa_printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
 136                       brw->urb.vs_start,
 137                       brw->urb.gs_start,
 138                       brw->urb.clip_start,
 139                       brw->urb.sf_start,
 140                       brw->urb.cs_start,
 141                       URB_SIZES(brw));
 142
 143       brw->state.dirty.brw |= BRW_NEW_URB_FENCE;
 144    }
 145 }
 146
 147
 148 const struct brw_tracked_state brw_recalculate_urb_fence = {
 149    .dirty = {
 150       .mesa = 0,
 151       .brw = BRW_NEW_CURBE_OFFSETS,
 152       .cache = (CACHE_NEW_VS_PROG |
 153                 CACHE_NEW_SF_PROG)
 154    },
 155    .update = recalculate_urb_fence
 156 };
 157
 158
 159
 160
 161
 162 void brw_upload_urb_fence(struct brw_context *brw)
 163 {
 164    struct brw_urb_fence uf;
 165    memset(&uf, 0, sizeof(uf));
 166
 167    uf.header.opcode = CMD_URB_FENCE;
 168    uf.header.length = sizeof(uf)/4-2;
 169    uf.header.vs_realloc = 1;
 170    uf.header.gs_realloc = 1;
 171    uf.header.clp_realloc = 1;
 172    uf.header.sf_realloc = 1;
 173    uf.header.vfe_realloc = 1;
 174    uf.header.cs_realloc = 1;
 175
 176    /* The ordering below is correct, not the layout in the
 177     * instruction.
 178     *
 179     * There are 256/384 urb reg pairs in total.
 180     */
 181    uf.bits0.vs_fence  = brw->urb.gs_start;
 182    uf.bits0.gs_fence  = brw->urb.clip_start;
 183    uf.bits0.clp_fence = brw->urb.sf_start;
 184    uf.bits1.sf_fence  = brw->urb.cs_start;
 185    uf.bits1.cs_fence  = URB_SIZES(brw);
 186
 187    BRW_BATCH_STRUCT(brw, &uf);
 188 }
 189
 190
 191 #if 0
 192 const struct brw_tracked_state brw_urb_fence = {
 193    .dirty = {
 194       .mesa = 0,
 195       .brw = BRW_NEW_URB_FENCE | BRW_NEW_PSP,
 196       .cache = 0
 197    },
 198    .update = brw_upload_urb_fence
 199 };
 200 #endif