2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "brw_context.h"
36 #include "brw_state.h"
37 #include "brw_defines.h"
45 /* XXX: Are the min_entry_size numbers useful?
46 * XXX: Verify min_nr_entries, esp for VS.
47 * XXX: Verify SF min_entry_size.
50 GLuint min_nr_entries
;
51 GLuint preferred_nr_entries
;
52 GLuint min_entry_size
;
53 GLuint max_entry_size
;
55 { 16, 32, 1, 5 }, /* vs */
56 { 4, 8, 1, 5 }, /* gs */
57 { 6, 8, 1, 5 }, /* clp */
58 { 1, 8, 1, 12 }, /* sf */
59 { 1, 4, 1, 32 } /* cs */
63 static GLboolean
check_urb_layout( struct brw_context
*brw
)
65 brw
->urb
.vs_start
= 0;
66 brw
->urb
.gs_start
= brw
->urb
.nr_vs_entries
* brw
->urb
.vsize
;
67 brw
->urb
.clip_start
= brw
->urb
.gs_start
+ brw
->urb
.nr_gs_entries
* brw
->urb
.vsize
;
68 brw
->urb
.sf_start
= brw
->urb
.clip_start
+ brw
->urb
.nr_clip_entries
* brw
->urb
.vsize
;
69 brw
->urb
.cs_start
= brw
->urb
.sf_start
+ brw
->urb
.nr_sf_entries
* brw
->urb
.sfsize
;
71 return brw
->urb
.cs_start
+ brw
->urb
.nr_cs_entries
* brw
->urb
.csize
<= URB_SIZES(brw
);
74 /* Most minimal update, forces re-emit of URB fence packet after GS
77 static void recalculate_urb_fence( struct brw_context
*brw
)
79 GLuint csize
= brw
->curbe
.total_size
;
80 GLuint vsize
= brw
->vs
.prog_data
->urb_entry_size
;
81 GLuint sfsize
= brw
->sf
.prog_data
->urb_entry_size
;
83 if (csize
< limits
[CS
].min_entry_size
)
84 csize
= limits
[CS
].min_entry_size
;
86 if (vsize
< limits
[VS
].min_entry_size
)
87 vsize
= limits
[VS
].min_entry_size
;
89 if (sfsize
< limits
[SF
].min_entry_size
)
90 sfsize
= limits
[SF
].min_entry_size
;
92 if (brw
->urb
.vsize
< vsize
||
93 brw
->urb
.sfsize
< sfsize
||
94 brw
->urb
.csize
< csize
||
95 (brw
->urb
.constrained
&& (brw
->urb
.vsize
> vsize
||
96 brw
->urb
.sfsize
> sfsize
||
97 brw
->urb
.csize
> csize
))) {
100 brw
->urb
.csize
= csize
;
101 brw
->urb
.sfsize
= sfsize
;
102 brw
->urb
.vsize
= vsize
;
104 brw
->urb
.nr_vs_entries
= limits
[VS
].preferred_nr_entries
;
105 brw
->urb
.nr_gs_entries
= limits
[GS
].preferred_nr_entries
;
106 brw
->urb
.nr_clip_entries
= limits
[CLP
].preferred_nr_entries
;
107 brw
->urb
.nr_sf_entries
= limits
[SF
].preferred_nr_entries
;
108 brw
->urb
.nr_cs_entries
= limits
[CS
].preferred_nr_entries
;
110 if (!check_urb_layout(brw
)) {
111 brw
->urb
.nr_vs_entries
= limits
[VS
].min_nr_entries
;
112 brw
->urb
.nr_gs_entries
= limits
[GS
].min_nr_entries
;
113 brw
->urb
.nr_clip_entries
= limits
[CLP
].min_nr_entries
;
114 brw
->urb
.nr_sf_entries
= limits
[SF
].min_nr_entries
;
115 brw
->urb
.nr_cs_entries
= limits
[CS
].min_nr_entries
;
117 /* Mark us as operating with constrained nr_entries, so that next
118 * time we recalculate we'll resize the fences in the hope of
119 * escaping constrained mode and getting back to normal performance.
121 brw
->urb
.constrained
= 1;
123 if (!check_urb_layout(brw
)) {
124 /* This is impossible, given the maximal sizes of urb
125 * entries and the values for minimum nr of entries
128 _mesa_printf("couldn't calculate URB layout!\n");
132 if (INTEL_DEBUG
& (DEBUG_URB
|DEBUG_FALLBACKS
))
133 _mesa_printf("URB CONSTRAINED\n");
136 brw
->urb
.constrained
= 0;
138 if (INTEL_DEBUG
& DEBUG_URB
)
139 _mesa_printf("URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
147 brw
->state
.dirty
.brw
|= BRW_NEW_URB_FENCE
;
152 const struct brw_tracked_state brw_recalculate_urb_fence
= {
155 .brw
= BRW_NEW_CURBE_OFFSETS
,
156 .cache
= (CACHE_NEW_VS_PROG
|
159 .prepare
= recalculate_urb_fence
166 void brw_upload_urb_fence(struct brw_context
*brw
)
168 struct brw_urb_fence uf
;
169 memset(&uf
, 0, sizeof(uf
));
171 uf
.header
.opcode
= CMD_URB_FENCE
;
172 uf
.header
.length
= sizeof(uf
)/4-2;
173 uf
.header
.vs_realloc
= 1;
174 uf
.header
.gs_realloc
= 1;
175 uf
.header
.clp_realloc
= 1;
176 uf
.header
.sf_realloc
= 1;
177 uf
.header
.vfe_realloc
= 1;
178 uf
.header
.cs_realloc
= 1;
180 /* The ordering below is correct, not the layout in the
183 * There are 256/384 urb reg pairs in total.
185 uf
.bits0
.vs_fence
= brw
->urb
.gs_start
;
186 uf
.bits0
.gs_fence
= brw
->urb
.clip_start
;
187 uf
.bits0
.clp_fence
= brw
->urb
.sf_start
;
188 uf
.bits1
.sf_fence
= brw
->urb
.cs_start
;
189 uf
.bits1
.cs_fence
= URB_SIZES(brw
);
191 BRW_BATCH_STRUCT(brw
, &uf
);