2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_builder.h"
30 #include "brw_vec4_live_variables.h"
31 #include "brw_dead_control_flow.h"
32 #include "program/prog_parameter.h"
34 #define MAX_INSTRUCTION (1 << 30)
43 memset(this, 0, sizeof(*this));
45 this->file
= BAD_FILE
;
48 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
54 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
55 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
57 this->swizzle
= BRW_SWIZZLE_XYZW
;
59 this->type
= brw_type_for_base_type(type
);
62 /** Generic unset register constructor. */
68 src_reg::src_reg(struct ::brw_reg reg
) :
75 src_reg::src_reg(const dst_reg
®
) :
78 this->reladdr
= reg
.reladdr
;
79 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
85 memset(this, 0, sizeof(*this));
86 this->file
= BAD_FILE
;
87 this->writemask
= WRITEMASK_XYZW
;
95 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
103 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
110 this->type
= brw_type_for_base_type(type
);
111 this->writemask
= writemask
;
114 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
122 this->writemask
= writemask
;
125 dst_reg::dst_reg(struct ::brw_reg reg
) :
128 this->reg_offset
= 0;
129 this->reladdr
= NULL
;
132 dst_reg::dst_reg(const src_reg
®
) :
135 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
136 this->reladdr
= reg
.reladdr
;
140 dst_reg::equals(const dst_reg
&r
) const
142 return (this->backend_reg::equals(r
) &&
143 (reladdr
== r
.reladdr
||
144 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
148 vec4_instruction::is_send_from_grf()
151 case SHADER_OPCODE_SHADER_TIME_ADD
:
152 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
153 case SHADER_OPCODE_UNTYPED_ATOMIC
:
154 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
155 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
156 case SHADER_OPCODE_TYPED_ATOMIC
:
157 case SHADER_OPCODE_TYPED_SURFACE_READ
:
158 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
159 case VEC4_OPCODE_URB_READ
:
160 case TCS_OPCODE_URB_WRITE
:
161 case TCS_OPCODE_RELEASE_INPUT
:
162 case SHADER_OPCODE_BARRIER
:
170 * Returns true if this instruction's sources and destinations cannot
171 * safely be the same register.
173 * In most cases, a register can be written over safely by the same
174 * instruction that is its last use. For a single instruction, the
175 * sources are dereferenced before writing of the destination starts
178 * However, there are a few cases where this can be problematic:
180 * - Virtual opcodes that translate to multiple instructions in the
181 * code generator: if src == dst and one instruction writes the
182 * destination before a later instruction reads the source, then
183 * src will have been clobbered.
185 * The register allocator uses this information to set up conflicts between
186 * GRF sources and the destination.
189 vec4_instruction::has_source_and_destination_hazard() const
192 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
193 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
194 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
202 vec4_instruction::regs_read(unsigned arg
) const
204 if (src
[arg
].file
== BAD_FILE
)
208 case SHADER_OPCODE_SHADER_TIME_ADD
:
209 case SHADER_OPCODE_UNTYPED_ATOMIC
:
210 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
211 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
212 case SHADER_OPCODE_TYPED_ATOMIC
:
213 case SHADER_OPCODE_TYPED_SURFACE_READ
:
214 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
215 case TCS_OPCODE_URB_WRITE
:
216 return arg
== 0 ? mlen
: 1;
218 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
219 return arg
== 1 ? mlen
: 1;
227 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
229 if (devinfo
->gen
== 6 && is_math())
232 if (is_send_from_grf())
235 if (!backend_instruction::can_do_source_mods())
242 vec4_instruction::can_change_types() const
244 return dst
.type
== src
[0].type
&&
245 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
246 (opcode
== BRW_OPCODE_MOV
||
247 (opcode
== BRW_OPCODE_SEL
&&
248 dst
.type
== src
[1].type
&&
249 predicate
!= BRW_PREDICATE_NONE
&&
250 !src
[1].abs
&& !src
[1].negate
));
254 * Returns how many MRFs an opcode will write over.
256 * Note that this is not the 0 or 1 implied writes in an actual gen
257 * instruction -- the generate_* functions generate additional MOVs
261 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
263 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
266 switch (inst
->opcode
) {
267 case SHADER_OPCODE_RCP
:
268 case SHADER_OPCODE_RSQ
:
269 case SHADER_OPCODE_SQRT
:
270 case SHADER_OPCODE_EXP2
:
271 case SHADER_OPCODE_LOG2
:
272 case SHADER_OPCODE_SIN
:
273 case SHADER_OPCODE_COS
:
275 case SHADER_OPCODE_INT_QUOTIENT
:
276 case SHADER_OPCODE_INT_REMAINDER
:
277 case SHADER_OPCODE_POW
:
278 case TCS_OPCODE_THREAD_END
:
280 case VS_OPCODE_URB_WRITE
:
282 case VS_OPCODE_PULL_CONSTANT_LOAD
:
284 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
286 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
288 case GS_OPCODE_URB_WRITE
:
289 case GS_OPCODE_URB_WRITE_ALLOCATE
:
290 case GS_OPCODE_THREAD_END
:
292 case GS_OPCODE_FF_SYNC
:
294 case TCS_OPCODE_URB_WRITE
:
296 case SHADER_OPCODE_SHADER_TIME_ADD
:
298 case SHADER_OPCODE_TEX
:
299 case SHADER_OPCODE_TXL
:
300 case SHADER_OPCODE_TXD
:
301 case SHADER_OPCODE_TXF
:
302 case SHADER_OPCODE_TXF_CMS
:
303 case SHADER_OPCODE_TXF_CMS_W
:
304 case SHADER_OPCODE_TXF_MCS
:
305 case SHADER_OPCODE_TXS
:
306 case SHADER_OPCODE_TG4
:
307 case SHADER_OPCODE_TG4_OFFSET
:
308 case SHADER_OPCODE_SAMPLEINFO
:
309 case VS_OPCODE_GET_BUFFER_SIZE
:
310 return inst
->header_size
;
312 unreachable("not reached");
317 src_reg::equals(const src_reg
&r
) const
319 return (this->backend_reg::equals(r
) &&
320 !reladdr
&& !r
.reladdr
);
324 vec4_visitor::vectorize_mov(bblock_t
*block
, vec4_instruction
*inst
,
325 uint8_t imm
[4], vec4_instruction
*imm_inst
[4],
326 int inst_count
, unsigned writemask
)
332 memcpy(&vf
, imm
, sizeof(vf
));
333 vec4_instruction
*mov
= MOV(imm_inst
[0]->dst
, brw_imm_vf(vf
));
334 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
335 mov
->dst
.writemask
= writemask
;
336 inst
->insert_before(block
, mov
);
338 for (int i
= 0; i
< inst_count
; i
++) {
339 imm_inst
[i
]->remove(block
);
346 vec4_visitor::opt_vector_float()
348 bool progress
= false;
350 int last_reg
= -1, last_reg_offset
= -1;
351 enum brw_reg_file last_reg_file
= BAD_FILE
;
353 uint8_t imm
[4] = { 0 };
355 vec4_instruction
*imm_inst
[4];
356 unsigned writemask
= 0;
358 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
359 if (last_reg
!= inst
->dst
.nr
||
360 last_reg_offset
!= inst
->dst
.reg_offset
||
361 last_reg_file
!= inst
->dst
.file
) {
362 progress
|= vectorize_mov(block
, inst
, imm
, imm_inst
, inst_count
,
366 last_reg
= inst
->dst
.nr
;
367 last_reg_offset
= inst
->dst
.reg_offset
;
368 last_reg_file
= inst
->dst
.file
;
370 for (int i
= 0; i
< 4; i
++) {
375 if (inst
->opcode
!= BRW_OPCODE_MOV
||
376 inst
->dst
.writemask
== WRITEMASK_XYZW
||
377 inst
->src
[0].file
!= IMM
||
378 inst
->predicate
!= BRW_PREDICATE_NONE
) {
379 progress
|= vectorize_mov(block
, inst
, imm
, imm_inst
, inst_count
,
386 int vf
= brw_float_to_vf(inst
->src
[0].f
);
390 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
392 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
394 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
396 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
399 writemask
|= inst
->dst
.writemask
;
400 imm_inst
[inst_count
++] = inst
;
404 invalidate_live_intervals();
409 /* Replaces unused channels of a swizzle with channels that are used.
411 * For instance, this pass transforms
413 * mov vgrf4.yz, vgrf5.wxzy
417 * mov vgrf4.yz, vgrf5.xxzx
419 * This eliminates false uses of some channels, letting dead code elimination
420 * remove the instructions that wrote them.
423 vec4_visitor::opt_reduce_swizzle()
425 bool progress
= false;
427 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
428 if (inst
->dst
.file
== BAD_FILE
||
429 inst
->dst
.file
== ARF
||
430 inst
->dst
.file
== FIXED_GRF
||
431 inst
->is_send_from_grf())
436 /* Determine which channels of the sources are read. */
437 switch (inst
->opcode
) {
438 case VEC4_OPCODE_PACK_BYTES
:
440 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
441 * but all four of src1.
443 swizzle
= brw_swizzle_for_size(4);
446 swizzle
= brw_swizzle_for_size(3);
449 swizzle
= brw_swizzle_for_size(2);
452 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
456 /* Update sources' swizzles. */
457 for (int i
= 0; i
< 3; i
++) {
458 if (inst
->src
[i
].file
!= VGRF
&&
459 inst
->src
[i
].file
!= ATTR
&&
460 inst
->src
[i
].file
!= UNIFORM
)
463 const unsigned new_swizzle
=
464 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
465 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
466 inst
->src
[i
].swizzle
= new_swizzle
;
473 invalidate_live_intervals();
479 vec4_visitor::split_uniform_registers()
481 /* Prior to this, uniforms have been in an array sized according to
482 * the number of vector uniforms present, sparsely filled (so an
483 * aggregate results in reg indices being skipped over). Now we're
484 * going to cut those aggregates up so each .nr index is one
485 * vector. The goal is to make elimination of unused uniform
486 * components easier later.
488 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
489 for (int i
= 0 ; i
< 3; i
++) {
490 if (inst
->src
[i
].file
!= UNIFORM
)
493 assert(!inst
->src
[i
].reladdr
);
495 inst
->src
[i
].nr
+= inst
->src
[i
].reg_offset
;
496 inst
->src
[i
].reg_offset
= 0;
502 vec4_visitor::pack_uniform_registers()
504 uint8_t chans_used
[this->uniforms
];
505 int new_loc
[this->uniforms
];
506 int new_chan
[this->uniforms
];
508 memset(chans_used
, 0, sizeof(chans_used
));
509 memset(new_loc
, 0, sizeof(new_loc
));
510 memset(new_chan
, 0, sizeof(new_chan
));
512 /* Find which uniform vectors are actually used by the program. We
513 * expect unused vector elements when we've moved array access out
514 * to pull constants, and from some GLSL code generators like wine.
516 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
518 switch (inst
->opcode
) {
519 case VEC4_OPCODE_PACK_BYTES
:
531 readmask
= inst
->dst
.writemask
;
535 for (int i
= 0 ; i
< 3; i
++) {
536 if (inst
->src
[i
].file
!= UNIFORM
)
539 int reg
= inst
->src
[i
].nr
;
540 for (int c
= 0; c
< 4; c
++) {
541 if (!(readmask
& (1 << c
)))
544 chans_used
[reg
] = MAX2(chans_used
[reg
],
545 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
550 int new_uniform_count
= 0;
552 /* Now, figure out a packing of the live uniform vectors into our
555 for (int src
= 0; src
< uniforms
; src
++) {
556 int size
= chans_used
[src
];
562 /* Find the lowest place we can slot this uniform in. */
563 for (dst
= 0; dst
< src
; dst
++) {
564 if (chans_used
[dst
] + size
<= 4)
573 new_chan
[src
] = chans_used
[dst
];
575 /* Move the references to the data */
576 for (int j
= 0; j
< size
; j
++) {
577 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
578 stage_prog_data
->param
[src
* 4 + j
];
581 chans_used
[dst
] += size
;
585 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
588 this->uniforms
= new_uniform_count
;
590 /* Now, update the instructions for our repacked uniforms. */
591 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
592 for (int i
= 0 ; i
< 3; i
++) {
593 int src
= inst
->src
[i
].nr
;
595 if (inst
->src
[i
].file
!= UNIFORM
)
598 inst
->src
[i
].nr
= new_loc
[src
];
599 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
600 new_chan
[src
], new_chan
[src
]);
606 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
608 * While GLSL IR also performs this optimization, we end up with it in
609 * our instruction stream for a couple of reasons. One is that we
610 * sometimes generate silly instructions, for example in array access
611 * where we'll generate "ADD offset, index, base" even if base is 0.
612 * The other is that GLSL IR's constant propagation doesn't track the
613 * components of aggregates, so some VS patterns (initialize matrix to
614 * 0, accumulate in vertex blending factors) end up breaking down to
615 * instructions involving 0.
618 vec4_visitor::opt_algebraic()
620 bool progress
= false;
622 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
623 switch (inst
->opcode
) {
625 if (inst
->src
[0].file
!= IMM
)
628 if (inst
->saturate
) {
629 if (inst
->dst
.type
!= inst
->src
[0].type
)
630 assert(!"unimplemented: saturate mixed types");
632 if (brw_saturate_immediate(inst
->dst
.type
,
633 &inst
->src
[0].as_brw_reg())) {
634 inst
->saturate
= false;
640 case VEC4_OPCODE_UNPACK_UNIFORM
:
641 if (inst
->src
[0].file
!= UNIFORM
) {
642 inst
->opcode
= BRW_OPCODE_MOV
;
648 if (inst
->src
[1].is_zero()) {
649 inst
->opcode
= BRW_OPCODE_MOV
;
650 inst
->src
[1] = src_reg();
656 if (inst
->src
[1].is_zero()) {
657 inst
->opcode
= BRW_OPCODE_MOV
;
658 switch (inst
->src
[0].type
) {
659 case BRW_REGISTER_TYPE_F
:
660 inst
->src
[0] = brw_imm_f(0.0f
);
662 case BRW_REGISTER_TYPE_D
:
663 inst
->src
[0] = brw_imm_d(0);
665 case BRW_REGISTER_TYPE_UD
:
666 inst
->src
[0] = brw_imm_ud(0u);
669 unreachable("not reached");
671 inst
->src
[1] = src_reg();
673 } else if (inst
->src
[1].is_one()) {
674 inst
->opcode
= BRW_OPCODE_MOV
;
675 inst
->src
[1] = src_reg();
677 } else if (inst
->src
[1].is_negative_one()) {
678 inst
->opcode
= BRW_OPCODE_MOV
;
679 inst
->src
[0].negate
= !inst
->src
[0].negate
;
680 inst
->src
[1] = src_reg();
685 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
687 inst
->src
[0].negate
&&
688 inst
->src
[1].is_zero()) {
689 inst
->src
[0].abs
= false;
690 inst
->src
[0].negate
= false;
691 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
696 case SHADER_OPCODE_BROADCAST
:
697 if (is_uniform(inst
->src
[0]) ||
698 inst
->src
[1].is_zero()) {
699 inst
->opcode
= BRW_OPCODE_MOV
;
700 inst
->src
[1] = src_reg();
701 inst
->force_writemask_all
= true;
712 invalidate_live_intervals();
718 * Only a limited number of hardware registers may be used for push
719 * constants, so this turns access to the overflowed constants into
723 vec4_visitor::move_push_constants_to_pull_constants()
725 int pull_constant_loc
[this->uniforms
];
727 /* Only allow 32 registers (256 uniform components) as push constants,
728 * which is the limit on gen6.
730 * If changing this value, note the limitation about total_regs in
733 int max_uniform_components
= 32 * 8;
734 if (this->uniforms
* 4 <= max_uniform_components
)
737 /* Make some sort of choice as to which uniforms get sent to pull
738 * constants. We could potentially do something clever here like
739 * look for the most infrequently used uniform vec4s, but leave
742 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
743 pull_constant_loc
[i
/ 4] = -1;
745 if (i
>= max_uniform_components
) {
746 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
748 /* Try to find an existing copy of this uniform in the pull
749 * constants if it was part of an array access already.
751 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
754 for (matches
= 0; matches
< 4; matches
++) {
755 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
760 pull_constant_loc
[i
/ 4] = j
/ 4;
765 if (pull_constant_loc
[i
/ 4] == -1) {
766 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
767 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
769 for (int j
= 0; j
< 4; j
++) {
770 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
777 /* Now actually rewrite usage of the things we've moved to pull
780 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
781 for (int i
= 0 ; i
< 3; i
++) {
782 if (inst
->src
[i
].file
!= UNIFORM
||
783 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
786 int uniform
= inst
->src
[i
].nr
;
788 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
790 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
791 pull_constant_loc
[uniform
], src_reg());
793 inst
->src
[i
].file
= temp
.file
;
794 inst
->src
[i
].nr
= temp
.nr
;
795 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
796 inst
->src
[i
].reladdr
= NULL
;
800 /* Repack push constants to remove the now-unused ones. */
801 pack_uniform_registers();
804 /* Conditions for which we want to avoid setting the dependency control bits */
806 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
808 #define IS_DWORD(reg) \
809 (reg.type == BRW_REGISTER_TYPE_UD || \
810 reg.type == BRW_REGISTER_TYPE_D)
812 /* "When source or destination datatype is 64b or operation is integer DWord
813 * multiply, DepCtrl must not be used."
814 * May apply to future SoCs as well.
816 if (devinfo
->is_cherryview
) {
817 if (inst
->opcode
== BRW_OPCODE_MUL
&&
818 IS_DWORD(inst
->src
[0]) &&
819 IS_DWORD(inst
->src
[1]))
824 if (devinfo
->gen
>= 8) {
825 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
831 * In the presence of send messages, totally interrupt dependency
832 * control. They're long enough that the chance of dependency
833 * control around them just doesn't matter.
836 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
837 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
838 * completes the scoreboard clear must have a non-zero execution mask. This
839 * means, if any kind of predication can change the execution mask or channel
840 * enable of the last instruction, the optimization must be avoided. This is
841 * to avoid instructions being shot down the pipeline when no writes are
845 * Dependency control does not work well over math instructions.
846 * NB: Discovered empirically
848 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
852 * Sets the dependency control fields on instructions after register
853 * allocation and before the generator is run.
855 * When you have a sequence of instructions like:
857 * DP4 temp.x vertex uniform[0]
858 * DP4 temp.y vertex uniform[0]
859 * DP4 temp.z vertex uniform[0]
860 * DP4 temp.w vertex uniform[0]
862 * The hardware doesn't know that it can actually run the later instructions
863 * while the previous ones are in flight, producing stalls. However, we have
864 * manual fields we can set in the instructions that let it do so.
867 vec4_visitor::opt_set_dependency_control()
869 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
870 uint8_t grf_channels_written
[BRW_MAX_GRF
];
871 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
872 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
874 assert(prog_data
->total_grf
||
875 !"Must be called after register allocation");
877 foreach_block (block
, cfg
) {
878 memset(last_grf_write
, 0, sizeof(last_grf_write
));
879 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
881 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
882 /* If we read from a register that we were doing dependency control
883 * on, don't do dependency control across the read.
885 for (int i
= 0; i
< 3; i
++) {
886 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
887 if (inst
->src
[i
].file
== VGRF
) {
888 last_grf_write
[reg
] = NULL
;
889 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
890 memset(last_grf_write
, 0, sizeof(last_grf_write
));
893 assert(inst
->src
[i
].file
!= MRF
);
896 if (is_dep_ctrl_unsafe(inst
)) {
897 memset(last_grf_write
, 0, sizeof(last_grf_write
));
898 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
902 /* Now, see if we can do dependency control for this instruction
903 * against a previous one writing to its destination.
905 int reg
= inst
->dst
.nr
+ inst
->dst
.reg_offset
;
906 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
907 if (last_grf_write
[reg
] &&
908 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
909 last_grf_write
[reg
]->no_dd_clear
= true;
910 inst
->no_dd_check
= true;
912 grf_channels_written
[reg
] = 0;
915 last_grf_write
[reg
] = inst
;
916 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
917 } else if (inst
->dst
.file
== MRF
) {
918 if (last_mrf_write
[reg
] &&
919 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
920 last_mrf_write
[reg
]->no_dd_clear
= true;
921 inst
->no_dd_check
= true;
923 mrf_channels_written
[reg
] = 0;
926 last_mrf_write
[reg
] = inst
;
927 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
934 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
939 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
940 * or writemasking are not allowed.
942 if (devinfo
->gen
== 6 && is_math() &&
943 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
946 /* If this instruction sets anything not referenced by swizzle, then we'd
947 * totally break it when we reswizzle.
949 if (dst
.writemask
& ~swizzle_mask
)
955 for (int i
= 0; i
< 3; i
++) {
956 if (src
[i
].is_accumulator())
964 * For any channels in the swizzle's source that were populated by this
965 * instruction, rewrite the instruction to put the appropriate result directly
968 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
971 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
973 /* Destination write mask doesn't correspond to source swizzle for the dot
974 * product and pack_bytes instructions.
976 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
977 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
978 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
979 for (int i
= 0; i
< 3; i
++) {
980 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
983 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
987 /* Apply the specified swizzle and writemask to the original mask of
988 * written components.
990 dst
.writemask
= dst_writemask
&
991 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
995 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
996 * just written and then MOVed into another reg and making the original write
997 * of the GRF write directly to the final destination instead.
1000 vec4_visitor::opt_register_coalesce()
1002 bool progress
= false;
1005 calculate_live_intervals();
1007 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1011 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1012 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1014 inst
->src
[0].file
!= VGRF
||
1015 inst
->dst
.type
!= inst
->src
[0].type
||
1016 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1019 /* Remove no-op MOVs */
1020 if (inst
->dst
.file
== inst
->src
[0].file
&&
1021 inst
->dst
.nr
== inst
->src
[0].nr
&&
1022 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1023 bool is_nop_mov
= true;
1025 for (unsigned c
= 0; c
< 4; c
++) {
1026 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1029 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1036 inst
->remove(block
);
1042 bool to_mrf
= (inst
->dst
.file
== MRF
);
1044 /* Can't coalesce this GRF if someone else was going to
1047 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1050 /* We need to check interference with the final destination between this
1051 * instruction and the earliest instruction involved in writing the GRF
1052 * we're eliminating. To do that, keep track of which of our source
1053 * channels we've seen initialized.
1055 const unsigned chans_needed
=
1056 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1057 inst
->dst
.writemask
);
1058 unsigned chans_remaining
= chans_needed
;
1060 /* Now walk up the instruction stream trying to see if we can rewrite
1061 * everything writing to the temporary to write into the destination
1064 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1065 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1067 _scan_inst
= scan_inst
;
1069 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1070 /* Found something writing to the reg we want to coalesce away. */
1072 /* SEND instructions can't have MRF as a destination. */
1073 if (scan_inst
->mlen
)
1076 if (devinfo
->gen
== 6) {
1077 /* gen6 math instructions must have the destination be
1078 * VGRF, so no compute-to-MRF for them.
1080 if (scan_inst
->is_math()) {
1086 /* This doesn't handle saturation on the instruction we
1087 * want to coalesce away if the register types do not match.
1088 * But if scan_inst is a non type-converting 'mov', we can fix
1091 if (inst
->saturate
&&
1092 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1093 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1094 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1097 /* If we can't handle the swizzle, bail. */
1098 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1099 inst
->src
[0].swizzle
,
1104 /* This doesn't handle coalescing of multiple registers. */
1105 if (scan_inst
->regs_written
> 1)
1108 /* Mark which channels we found unconditional writes for. */
1109 if (!scan_inst
->predicate
)
1110 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1112 if (chans_remaining
== 0)
1116 /* You can't read from an MRF, so if someone else reads our MRF's
1117 * source GRF that we wanted to rewrite, that stops us. If it's a
1118 * GRF we're trying to coalesce to, we don't actually handle
1119 * rewriting sources so bail in that case as well.
1121 bool interfered
= false;
1122 for (int i
= 0; i
< 3; i
++) {
1123 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1124 scan_inst
->regs_read(i
)))
1130 /* If somebody else writes the same channels of our destination here,
1131 * we can't coalesce before that.
1133 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1134 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1138 /* Check for reads of the register we're trying to coalesce into. We
1139 * can't go rewriting instructions above that to put some other value
1140 * in the register instead.
1142 if (to_mrf
&& scan_inst
->mlen
> 0) {
1143 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1144 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1148 for (int i
= 0; i
< 3; i
++) {
1149 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1150 scan_inst
->regs_read(i
)))
1158 if (chans_remaining
== 0) {
1159 /* If we've made it here, we have an MOV we want to coalesce out, and
1160 * a scan_inst pointing to the earliest instruction involved in
1161 * computing the value. Now go rewrite the instruction stream
1164 vec4_instruction
*scan_inst
= _scan_inst
;
1165 while (scan_inst
!= inst
) {
1166 if (scan_inst
->dst
.file
== VGRF
&&
1167 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1168 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1169 scan_inst
->reswizzle(inst
->dst
.writemask
,
1170 inst
->src
[0].swizzle
);
1171 scan_inst
->dst
.file
= inst
->dst
.file
;
1172 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1173 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1174 if (inst
->saturate
&&
1175 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1176 /* If we have reached this point, scan_inst is a non
1177 * type-converting 'mov' and we can modify its register types
1178 * to match the ones in inst. Otherwise, we could have an
1179 * incorrect saturation result.
1181 scan_inst
->dst
.type
= inst
->dst
.type
;
1182 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1184 scan_inst
->saturate
|= inst
->saturate
;
1186 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1188 inst
->remove(block
);
1194 invalidate_live_intervals();
1200 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1201 * flow. We could probably do better here with some form of divergence
1205 vec4_visitor::eliminate_find_live_channel()
1207 bool progress
= false;
1210 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1211 switch (inst
->opcode
) {
1217 case BRW_OPCODE_ENDIF
:
1218 case BRW_OPCODE_WHILE
:
1222 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1224 inst
->opcode
= BRW_OPCODE_MOV
;
1225 inst
->src
[0] = brw_imm_d(0);
1226 inst
->force_writemask_all
= true;
1240 * Splits virtual GRFs requesting more than one contiguous physical register.
1242 * We initially create large virtual GRFs for temporary structures, arrays,
1243 * and matrices, so that the dereference visitor functions can add reg_offsets
1244 * to work their way down to the actual member being accessed. But when it
1245 * comes to optimization, we'd like to treat each register as individual
1246 * storage if possible.
1248 * So far, the only thing that might prevent splitting is a send message from
1252 vec4_visitor::split_virtual_grfs()
1254 int num_vars
= this->alloc
.count
;
1255 int new_virtual_grf
[num_vars
];
1256 bool split_grf
[num_vars
];
1258 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1260 /* Try to split anything > 0 sized. */
1261 for (int i
= 0; i
< num_vars
; i
++) {
1262 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1265 /* Check that the instructions are compatible with the registers we're trying
1268 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1269 if (inst
->dst
.file
== VGRF
&& inst
->regs_written
> 1)
1270 split_grf
[inst
->dst
.nr
] = false;
1272 for (int i
= 0; i
< 3; i
++) {
1273 if (inst
->src
[i
].file
== VGRF
&& inst
->regs_read(i
) > 1)
1274 split_grf
[inst
->src
[i
].nr
] = false;
1278 /* Allocate new space for split regs. Note that the virtual
1279 * numbers will be contiguous.
1281 for (int i
= 0; i
< num_vars
; i
++) {
1285 new_virtual_grf
[i
] = alloc
.allocate(1);
1286 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1287 unsigned reg
= alloc
.allocate(1);
1288 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1291 this->alloc
.sizes
[i
] = 1;
1294 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1295 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1296 inst
->dst
.reg_offset
!= 0) {
1297 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1298 inst
->dst
.reg_offset
- 1);
1299 inst
->dst
.reg_offset
= 0;
1301 for (int i
= 0; i
< 3; i
++) {
1302 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1303 inst
->src
[i
].reg_offset
!= 0) {
1304 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1305 inst
->src
[i
].reg_offset
- 1);
1306 inst
->src
[i
].reg_offset
= 0;
1310 invalidate_live_intervals();
1314 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1316 dump_instruction(be_inst
, stderr
);
1320 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1322 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1324 if (inst
->predicate
) {
1325 fprintf(file
, "(%cf0.%d%s) ",
1326 inst
->predicate_inverse
? '-' : '+',
1328 pred_ctrl_align16
[inst
->predicate
]);
1331 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1333 fprintf(file
, ".sat");
1334 if (inst
->conditional_mod
) {
1335 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1336 if (!inst
->predicate
&&
1337 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1338 inst
->opcode
!= BRW_OPCODE_IF
&&
1339 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1340 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1345 switch (inst
->dst
.file
) {
1347 fprintf(file
, "vgrf%d.%d", inst
->dst
.nr
, inst
->dst
.reg_offset
);
1350 fprintf(file
, "g%d", inst
->dst
.nr
);
1353 fprintf(file
, "m%d", inst
->dst
.nr
);
1356 switch (inst
->dst
.nr
) {
1358 fprintf(file
, "null");
1360 case BRW_ARF_ADDRESS
:
1361 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1363 case BRW_ARF_ACCUMULATOR
:
1364 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1367 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1370 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1373 if (inst
->dst
.subnr
)
1374 fprintf(file
, "+%d", inst
->dst
.subnr
);
1377 fprintf(file
, "(null)");
1382 unreachable("not reached");
1384 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1386 if (inst
->dst
.writemask
& 1)
1388 if (inst
->dst
.writemask
& 2)
1390 if (inst
->dst
.writemask
& 4)
1392 if (inst
->dst
.writemask
& 8)
1395 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1397 if (inst
->src
[0].file
!= BAD_FILE
)
1398 fprintf(file
, ", ");
1400 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1401 if (inst
->src
[i
].negate
)
1403 if (inst
->src
[i
].abs
)
1405 switch (inst
->src
[i
].file
) {
1407 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1410 fprintf(file
, "g%d", inst
->src
[i
].nr
);
1413 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1416 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1419 switch (inst
->src
[i
].type
) {
1420 case BRW_REGISTER_TYPE_F
:
1421 fprintf(file
, "%fF", inst
->src
[i
].f
);
1423 case BRW_REGISTER_TYPE_D
:
1424 fprintf(file
, "%dD", inst
->src
[i
].d
);
1426 case BRW_REGISTER_TYPE_UD
:
1427 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1429 case BRW_REGISTER_TYPE_VF
:
1430 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1431 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1432 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1433 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1434 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1437 fprintf(file
, "???");
1442 switch (inst
->src
[i
].nr
) {
1444 fprintf(file
, "null");
1446 case BRW_ARF_ADDRESS
:
1447 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1449 case BRW_ARF_ACCUMULATOR
:
1450 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1453 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1456 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1459 if (inst
->src
[i
].subnr
)
1460 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
1463 fprintf(file
, "(null)");
1466 unreachable("not reached");
1469 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1470 if (inst
->src
[i
].reg_offset
!= 0 &&
1471 inst
->src
[i
].file
== VGRF
&&
1472 alloc
.sizes
[inst
->src
[i
].nr
] != 1)
1473 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1475 if (inst
->src
[i
].file
!= IMM
) {
1476 static const char *chans
[4] = {"x", "y", "z", "w"};
1478 for (int c
= 0; c
< 4; c
++) {
1479 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1483 if (inst
->src
[i
].abs
)
1486 if (inst
->src
[i
].file
!= IMM
) {
1487 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1490 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1491 fprintf(file
, ", ");
1494 if (inst
->force_writemask_all
)
1495 fprintf(file
, " NoMask");
1497 fprintf(file
, "\n");
1501 static inline struct brw_reg
1502 attribute_to_hw_reg(int attr
, bool interleaved
)
1505 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1507 return brw_vec8_grf(attr
, 0);
1512 * Replace each register of type ATTR in this->instructions with a reference
1513 * to a fixed HW register.
1515 * If interleaved is true, then each attribute takes up half a register, with
1516 * register N containing attribute 2*N in its first half and attribute 2*N+1
1517 * in its second half (this corresponds to the payload setup used by geometry
1518 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1519 * false, then each attribute takes up a whole register, with register N
1520 * containing attribute N (this corresponds to the payload setup used by
1521 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1524 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1527 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1528 for (int i
= 0; i
< 3; i
++) {
1529 if (inst
->src
[i
].file
!= ATTR
)
1532 int grf
= attribute_map
[inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
];
1534 /* All attributes used in the shader need to have been assigned a
1535 * hardware register by the caller
1539 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1540 reg
.swizzle
= inst
->src
[i
].swizzle
;
1541 reg
.type
= inst
->src
[i
].type
;
1542 if (inst
->src
[i
].abs
)
1544 if (inst
->src
[i
].negate
)
1553 vec4_vs_visitor::setup_attributes(int payload_reg
)
1556 int attribute_map
[VERT_ATTRIB_MAX
+ 2];
1557 memset(attribute_map
, 0, sizeof(attribute_map
));
1560 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1561 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1562 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1567 /* VertexID is stored by the VF as the last vertex element, but we
1568 * don't represent it with a flag in inputs_read, so we call it
1571 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
1572 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
) {
1573 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1577 if (vs_prog_data
->uses_drawid
) {
1578 attribute_map
[VERT_ATTRIB_MAX
+ 1] = payload_reg
+ nr_attributes
;
1582 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1584 return payload_reg
+ vs_prog_data
->nr_attributes
;
1588 vec4_visitor::setup_uniforms(int reg
)
1590 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1592 /* The pre-gen6 VS requires that some push constants get loaded no
1593 * matter what, or the GPU would hang.
1595 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1596 stage_prog_data
->param
=
1597 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1598 for (unsigned int i
= 0; i
< 4; i
++) {
1599 unsigned int slot
= this->uniforms
* 4 + i
;
1600 static gl_constant_value zero
= { 0.0 };
1601 stage_prog_data
->param
[slot
] = &zero
;
1607 reg
+= ALIGN(uniforms
, 2) / 2;
1610 stage_prog_data
->nr_params
= this->uniforms
* 4;
1612 prog_data
->base
.curb_read_length
=
1613 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1619 vec4_vs_visitor::setup_payload(void)
1623 /* The payload always contains important data in g0, which contains
1624 * the URB handles that are passed on to the URB write at the end
1625 * of the thread. So, we always start push constants at g1.
1629 reg
= setup_uniforms(reg
);
1631 reg
= setup_attributes(reg
);
1633 this->first_non_payload_grf
= reg
;
1637 vec4_visitor::lower_minmax()
1639 assert(devinfo
->gen
< 6);
1641 bool progress
= false;
1643 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1644 const vec4_builder
ibld(this, block
, inst
);
1646 if (inst
->opcode
== BRW_OPCODE_SEL
&&
1647 inst
->predicate
== BRW_PREDICATE_NONE
) {
1648 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
1649 * the original SEL.L/GE instruction
1651 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
1652 inst
->conditional_mod
);
1653 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1654 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
1661 invalidate_live_intervals();
1667 vec4_visitor::get_timestamp()
1669 assert(devinfo
->gen
>= 7);
1671 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1676 BRW_REGISTER_TYPE_UD
,
1677 BRW_VERTICAL_STRIDE_0
,
1679 BRW_HORIZONTAL_STRIDE_4
,
1683 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1685 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1686 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1687 * even if it's not enabled in the dispatch.
1689 mov
->force_writemask_all
= true;
1691 return src_reg(dst
);
1695 vec4_visitor::emit_shader_time_begin()
1697 current_annotation
= "shader time start";
1698 shader_start_time
= get_timestamp();
1702 vec4_visitor::emit_shader_time_end()
1704 current_annotation
= "shader time end";
1705 src_reg shader_end_time
= get_timestamp();
1708 /* Check that there weren't any timestamp reset events (assuming these
1709 * were the only two timestamp reads that happened).
1711 src_reg reset_end
= shader_end_time
;
1712 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1713 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1714 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1716 emit(IF(BRW_PREDICATE_NORMAL
));
1718 /* Take the current timestamp and get the delta. */
1719 shader_start_time
.negate
= true;
1720 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1721 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1723 /* If there were no instructions between the two timestamp gets, the diff
1724 * is 2 cycles. Remove that overhead, so I can forget about that when
1725 * trying to determine the time taken for single instructions.
1727 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1729 emit_shader_time_write(0, src_reg(diff
));
1730 emit_shader_time_write(1, brw_imm_ud(1u));
1731 emit(BRW_OPCODE_ELSE
);
1732 emit_shader_time_write(2, brw_imm_ud(1u));
1733 emit(BRW_OPCODE_ENDIF
);
1737 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1740 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1742 dst_reg offset
= dst
;
1746 offset
.type
= BRW_REGISTER_TYPE_UD
;
1747 int index
= shader_time_index
* 3 + shader_time_subindex
;
1748 emit(MOV(offset
, brw_imm_d(index
* SHADER_TIME_STRIDE
)));
1750 time
.type
= BRW_REGISTER_TYPE_UD
;
1751 emit(MOV(time
, value
));
1753 vec4_instruction
*inst
=
1754 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1759 vec4_visitor::convert_to_hw_regs()
1761 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1762 for (int i
= 0; i
< 3; i
++) {
1763 struct src_reg
&src
= inst
->src
[i
];
1767 reg
= brw_vec8_grf(src
.nr
+ src
.reg_offset
, 0);
1768 reg
.type
= src
.type
;
1769 reg
.swizzle
= src
.swizzle
;
1771 reg
.negate
= src
.negate
;
1775 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1776 (src
.nr
+ src
.reg_offset
) / 2,
1777 ((src
.nr
+ src
.reg_offset
) % 2) * 4),
1779 reg
.type
= src
.type
;
1780 reg
.swizzle
= src
.swizzle
;
1782 reg
.negate
= src
.negate
;
1784 /* This should have been moved to pull constants. */
1785 assert(!src
.reladdr
);
1794 /* Probably unused. */
1795 reg
= brw_null_reg();
1800 unreachable("not reached");
1806 if (inst
->is_3src()) {
1807 /* 3-src instructions with scalar sources support arbitrary subnr,
1808 * but don't actually use swizzles. Convert swizzle into subnr.
1810 for (int i
= 0; i
< 3; i
++) {
1811 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
) {
1812 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
1813 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
1818 dst_reg
&dst
= inst
->dst
;
1821 switch (inst
->dst
.file
) {
1823 reg
= brw_vec8_grf(dst
.nr
+ dst
.reg_offset
, 0);
1824 reg
.type
= dst
.type
;
1825 reg
.writemask
= dst
.writemask
;
1829 assert(((dst
.nr
+ dst
.reg_offset
) & ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
1830 reg
= brw_message_reg(dst
.nr
+ dst
.reg_offset
);
1831 reg
.type
= dst
.type
;
1832 reg
.writemask
= dst
.writemask
;
1837 reg
= dst
.as_brw_reg();
1841 reg
= brw_null_reg();
1847 unreachable("not reached");
1857 if (shader_time_index
>= 0)
1858 emit_shader_time_begin();
1871 /* Before any optimization, push array accesses out to scratch
1872 * space where we need them to be. This pass may allocate new
1873 * virtual GRFs, so we want to do it early. It also makes sure
1874 * that we have reladdr computations available for CSE, since we'll
1875 * often do repeated subexpressions for those.
1877 move_grf_array_access_to_scratch();
1878 move_uniform_array_access_to_pull_constants();
1880 pack_uniform_registers();
1881 move_push_constants_to_pull_constants();
1882 split_virtual_grfs();
1884 #define OPT(pass, args...) ({ \
1886 bool this_progress = pass(args); \
1888 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1889 char filename[64]; \
1890 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1891 stage_abbrev, nir->info.name, iteration, pass_num); \
1893 backend_shader::dump_instructions(filename); \
1896 progress = progress || this_progress; \
1901 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1903 snprintf(filename
, 64, "%s-%s-00-00-start",
1904 stage_abbrev
, nir
->info
.name
);
1906 backend_shader::dump_instructions(filename
);
1917 OPT(opt_predicated_break
, this);
1918 OPT(opt_reduce_swizzle
);
1919 OPT(dead_code_eliminate
);
1920 OPT(dead_control_flow_eliminate
, this);
1921 OPT(opt_copy_propagation
);
1922 OPT(opt_cmod_propagation
);
1925 OPT(opt_register_coalesce
);
1926 OPT(eliminate_find_live_channel
);
1931 if (OPT(opt_vector_float
)) {
1933 OPT(opt_copy_propagation
, false);
1934 OPT(opt_copy_propagation
, true);
1935 OPT(dead_code_eliminate
);
1938 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
1939 OPT(opt_cmod_propagation
);
1941 OPT(opt_copy_propagation
);
1942 OPT(dead_code_eliminate
);
1950 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1951 /* Debug of register spilling: Go spill everything. */
1952 const int grf_count
= alloc
.count
;
1953 float spill_costs
[alloc
.count
];
1954 bool no_spill
[alloc
.count
];
1955 evaluate_spill_costs(spill_costs
, no_spill
);
1956 for (int i
= 0; i
< grf_count
; i
++) {
1963 bool allocated_without_spills
= reg_allocate();
1965 if (!allocated_without_spills
) {
1966 compiler
->shader_perf_log(log_data
,
1967 "%s shader triggered register spilling. "
1968 "Try reducing the number of live vec4 values "
1969 "to improve performance.\n",
1972 while (!reg_allocate()) {
1978 opt_schedule_instructions();
1980 opt_set_dependency_control();
1982 convert_to_hw_regs();
1984 if (last_scratch
> 0) {
1985 prog_data
->base
.total_scratch
=
1986 brw_get_scratch_size(last_scratch
* REG_SIZE
);
1992 } /* namespace brw */
1997 * Compile a vertex shader.
1999 * Returns the final assembly and the program's size.
2002 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2004 const struct brw_vs_prog_key
*key
,
2005 struct brw_vs_prog_data
*prog_data
,
2006 const nir_shader
*src_shader
,
2007 gl_clip_plane
*clip_planes
,
2008 bool use_legacy_snorm_formula
,
2009 int shader_time_index
,
2010 unsigned *final_assembly_size
,
2013 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
2014 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
2015 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
2017 brw_nir_lower_vs_inputs(shader
, compiler
->devinfo
, is_scalar
,
2018 use_legacy_snorm_formula
, key
->gl_attrib_wa_flags
);
2019 brw_nir_lower_vue_outputs(shader
, is_scalar
);
2020 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, is_scalar
);
2022 const unsigned *assembly
= NULL
;
2024 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
2026 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2027 * incoming vertex attribute. So, add an extra slot.
2029 if (shader
->info
.system_values_read
&
2030 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
2031 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
2032 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2033 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2037 /* gl_DrawID has its very own vec4 */
2038 if (shader
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
)) {
2042 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2043 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2044 * vec4 mode, the hardware appears to wedge unless we read something.
2047 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
2049 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
2051 prog_data
->nr_attributes
= nr_attributes
;
2053 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2054 * (overwriting the original contents), we need to make sure the size is
2055 * the larger of the two.
2057 const unsigned vue_entries
=
2058 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2060 if (compiler
->devinfo
->gen
== 6)
2061 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2063 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2066 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2068 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2069 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2070 shader
, 8, shader_time_index
);
2071 if (!v
.run_vs(clip_planes
)) {
2073 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2078 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2079 &prog_data
->base
.base
, v
.promoted_constants
,
2080 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2081 if (INTEL_DEBUG
& DEBUG_VS
) {
2082 const char *debug_name
=
2083 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2084 shader
->info
.label
? shader
->info
.label
: "unnamed",
2087 g
.enable_debug(debug_name
);
2089 g
.generate_code(v
.cfg
, 8);
2090 assembly
= g
.get_assembly(final_assembly_size
);
2094 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2096 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2097 shader
, clip_planes
, mem_ctx
,
2098 shader_time_index
, use_legacy_snorm_formula
);
2101 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2106 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2107 shader
, &prog_data
->base
, v
.cfg
,
2108 final_assembly_size
);