2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "main/macros.h"
27 #include "program/prog_parameter.h"
30 #define MAX_INSTRUCTION (1 << 30)
35 * Common helper for constructing swizzles. When only a subset of
36 * channels of a vec4 are used, we don't want to reference the other
37 * channels, as that will tell optimization passes that those other
41 swizzle_for_size(int size
)
43 static const unsigned size_swizzles
[4] = {
44 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
45 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
46 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
47 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
50 assert((size
>= 1) && (size
<= 4));
51 return size_swizzles
[size
- 1];
57 memset(this, 0, sizeof(*this));
59 this->file
= BAD_FILE
;
62 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
68 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
69 this->swizzle
= swizzle_for_size(type
->vector_elements
);
71 this->swizzle
= SWIZZLE_XYZW
;
74 /** Generic unset register constructor. */
80 src_reg::src_reg(float f
)
85 this->type
= BRW_REGISTER_TYPE_F
;
89 src_reg::src_reg(uint32_t u
)
94 this->type
= BRW_REGISTER_TYPE_UD
;
98 src_reg::src_reg(int32_t i
)
103 this->type
= BRW_REGISTER_TYPE_D
;
107 src_reg::src_reg(dst_reg reg
)
111 this->file
= reg
.file
;
113 this->reg_offset
= reg
.reg_offset
;
114 this->type
= reg
.type
;
115 this->reladdr
= reg
.reladdr
;
116 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
122 for (int i
= 0; i
< 4; i
++) {
123 if (!(reg
.writemask
& (1 << i
)))
126 swizzles
[next_chan
++] = last
= i
;
129 for (; next_chan
< 4; next_chan
++) {
130 swizzles
[next_chan
] = last
;
133 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
134 swizzles
[2], swizzles
[3]);
138 vec4_instruction::is_tex()
140 return (opcode
== SHADER_OPCODE_TEX
||
141 opcode
== SHADER_OPCODE_TXD
||
142 opcode
== SHADER_OPCODE_TXF
||
143 opcode
== SHADER_OPCODE_TXL
||
144 opcode
== SHADER_OPCODE_TXS
);
150 memset(this, 0, sizeof(*this));
151 this->file
= BAD_FILE
;
152 this->writemask
= WRITEMASK_XYZW
;
160 dst_reg::dst_reg(register_file file
, int reg
)
168 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
175 this->type
= brw_type_for_base_type(type
);
176 this->writemask
= writemask
;
179 dst_reg::dst_reg(struct brw_reg reg
)
184 this->fixed_hw_reg
= reg
;
187 dst_reg::dst_reg(src_reg reg
)
191 this->file
= reg
.file
;
193 this->reg_offset
= reg
.reg_offset
;
194 this->type
= reg
.type
;
195 this->writemask
= WRITEMASK_XYZW
;
196 this->reladdr
= reg
.reladdr
;
197 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
201 vec4_instruction::is_math()
203 return (opcode
== SHADER_OPCODE_RCP
||
204 opcode
== SHADER_OPCODE_RSQ
||
205 opcode
== SHADER_OPCODE_SQRT
||
206 opcode
== SHADER_OPCODE_EXP2
||
207 opcode
== SHADER_OPCODE_LOG2
||
208 opcode
== SHADER_OPCODE_SIN
||
209 opcode
== SHADER_OPCODE_COS
||
210 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
211 opcode
== SHADER_OPCODE_INT_REMAINDER
||
212 opcode
== SHADER_OPCODE_POW
);
215 * Returns how many MRFs an opcode will write over.
217 * Note that this is not the 0 or 1 implied writes in an actual gen
218 * instruction -- the generate_* functions generate additional MOVs
222 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
227 switch (inst
->opcode
) {
228 case SHADER_OPCODE_RCP
:
229 case SHADER_OPCODE_RSQ
:
230 case SHADER_OPCODE_SQRT
:
231 case SHADER_OPCODE_EXP2
:
232 case SHADER_OPCODE_LOG2
:
233 case SHADER_OPCODE_SIN
:
234 case SHADER_OPCODE_COS
:
236 case SHADER_OPCODE_POW
:
238 case VS_OPCODE_URB_WRITE
:
240 case VS_OPCODE_PULL_CONSTANT_LOAD
:
242 case VS_OPCODE_SCRATCH_READ
:
244 case VS_OPCODE_SCRATCH_WRITE
:
247 assert(!"not reached");
253 src_reg::equals(src_reg
*r
)
255 return (file
== r
->file
&&
257 reg_offset
== r
->reg_offset
&&
259 negate
== r
->negate
&&
261 swizzle
== r
->swizzle
&&
262 !reladdr
&& !r
->reladdr
&&
263 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
264 sizeof(fixed_hw_reg
)) == 0 &&
269 * Must be called after calculate_live_intervales() to remove unused
270 * writes to registers -- register allocation will fail otherwise
271 * because something deffed but not used won't be considered to
272 * interfere with other regs.
275 vec4_visitor::dead_code_eliminate()
277 bool progress
= false;
280 calculate_live_intervals();
282 foreach_list_safe(node
, &this->instructions
) {
283 vec4_instruction
*inst
= (vec4_instruction
*)node
;
285 if (inst
->dst
.file
== GRF
&& this->virtual_grf_use
[inst
->dst
.reg
] <= pc
) {
294 live_intervals_valid
= false;
300 vec4_visitor::split_uniform_registers()
302 /* Prior to this, uniforms have been in an array sized according to
303 * the number of vector uniforms present, sparsely filled (so an
304 * aggregate results in reg indices being skipped over). Now we're
305 * going to cut those aggregates up so each .reg index is one
306 * vector. The goal is to make elimination of unused uniform
307 * components easier later.
309 foreach_list(node
, &this->instructions
) {
310 vec4_instruction
*inst
= (vec4_instruction
*)node
;
312 for (int i
= 0 ; i
< 3; i
++) {
313 if (inst
->src
[i
].file
!= UNIFORM
)
316 assert(!inst
->src
[i
].reladdr
);
318 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
319 inst
->src
[i
].reg_offset
= 0;
323 /* Update that everything is now vector-sized. */
324 for (int i
= 0; i
< this->uniforms
; i
++) {
325 this->uniform_size
[i
] = 1;
330 vec4_visitor::pack_uniform_registers()
332 bool uniform_used
[this->uniforms
];
333 int new_loc
[this->uniforms
];
334 int new_chan
[this->uniforms
];
336 memset(uniform_used
, 0, sizeof(uniform_used
));
337 memset(new_loc
, 0, sizeof(new_loc
));
338 memset(new_chan
, 0, sizeof(new_chan
));
340 /* Find which uniform vectors are actually used by the program. We
341 * expect unused vector elements when we've moved array access out
342 * to pull constants, and from some GLSL code generators like wine.
344 foreach_list(node
, &this->instructions
) {
345 vec4_instruction
*inst
= (vec4_instruction
*)node
;
347 for (int i
= 0 ; i
< 3; i
++) {
348 if (inst
->src
[i
].file
!= UNIFORM
)
351 uniform_used
[inst
->src
[i
].reg
] = true;
355 int new_uniform_count
= 0;
357 /* Now, figure out a packing of the live uniform vectors into our
360 for (int src
= 0; src
< uniforms
; src
++) {
361 int size
= this->uniform_vector_size
[src
];
363 if (!uniform_used
[src
]) {
364 this->uniform_vector_size
[src
] = 0;
369 /* Find the lowest place we can slot this uniform in. */
370 for (dst
= 0; dst
< src
; dst
++) {
371 if (this->uniform_vector_size
[dst
] + size
<= 4)
380 new_chan
[src
] = this->uniform_vector_size
[dst
];
382 /* Move the references to the data */
383 for (int j
= 0; j
< size
; j
++) {
384 c
->prog_data
.param
[dst
* 4 + new_chan
[src
] + j
] =
385 c
->prog_data
.param
[src
* 4 + j
];
388 this->uniform_vector_size
[dst
] += size
;
389 this->uniform_vector_size
[src
] = 0;
392 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
395 this->uniforms
= new_uniform_count
;
397 /* Now, update the instructions for our repacked uniforms. */
398 foreach_list(node
, &this->instructions
) {
399 vec4_instruction
*inst
= (vec4_instruction
*)node
;
401 for (int i
= 0 ; i
< 3; i
++) {
402 int src
= inst
->src
[i
].reg
;
404 if (inst
->src
[i
].file
!= UNIFORM
)
407 inst
->src
[i
].reg
= new_loc
[src
];
409 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
410 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
411 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
412 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
413 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
419 src_reg::is_zero() const
424 if (type
== BRW_REGISTER_TYPE_F
) {
432 src_reg::is_one() const
437 if (type
== BRW_REGISTER_TYPE_F
) {
445 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
447 * While GLSL IR also performs this optimization, we end up with it in
448 * our instruction stream for a couple of reasons. One is that we
449 * sometimes generate silly instructions, for example in array access
450 * where we'll generate "ADD offset, index, base" even if base is 0.
451 * The other is that GLSL IR's constant propagation doesn't track the
452 * components of aggregates, so some VS patterns (initialize matrix to
453 * 0, accumulate in vertex blending factors) end up breaking down to
454 * instructions involving 0.
457 vec4_visitor::opt_algebraic()
459 bool progress
= false;
461 foreach_list(node
, &this->instructions
) {
462 vec4_instruction
*inst
= (vec4_instruction
*)node
;
464 switch (inst
->opcode
) {
466 if (inst
->src
[1].is_zero()) {
467 inst
->opcode
= BRW_OPCODE_MOV
;
468 inst
->src
[1] = src_reg();
474 if (inst
->src
[1].is_zero()) {
475 inst
->opcode
= BRW_OPCODE_MOV
;
476 switch (inst
->src
[0].type
) {
477 case BRW_REGISTER_TYPE_F
:
478 inst
->src
[0] = src_reg(0.0f
);
480 case BRW_REGISTER_TYPE_D
:
481 inst
->src
[0] = src_reg(0);
483 case BRW_REGISTER_TYPE_UD
:
484 inst
->src
[0] = src_reg(0u);
487 assert(!"not reached");
488 inst
->src
[0] = src_reg(0.0f
);
491 inst
->src
[1] = src_reg();
493 } else if (inst
->src
[1].is_one()) {
494 inst
->opcode
= BRW_OPCODE_MOV
;
495 inst
->src
[1] = src_reg();
505 this->live_intervals_valid
= false;
511 * Only a limited number of hardware registers may be used for push
512 * constants, so this turns access to the overflowed constants into
516 vec4_visitor::move_push_constants_to_pull_constants()
518 int pull_constant_loc
[this->uniforms
];
520 /* Only allow 32 registers (256 uniform components) as push constants,
521 * which is the limit on gen6.
523 int max_uniform_components
= 32 * 8;
524 if (this->uniforms
* 4 <= max_uniform_components
)
527 /* Make some sort of choice as to which uniforms get sent to pull
528 * constants. We could potentially do something clever here like
529 * look for the most infrequently used uniform vec4s, but leave
532 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
533 pull_constant_loc
[i
/ 4] = -1;
535 if (i
>= max_uniform_components
) {
536 const float **values
= &prog_data
->param
[i
];
538 /* Try to find an existing copy of this uniform in the pull
539 * constants if it was part of an array access already.
541 for (unsigned int j
= 0; j
< prog_data
->nr_pull_params
; j
+= 4) {
544 for (matches
= 0; matches
< 4; matches
++) {
545 if (prog_data
->pull_param
[j
+ matches
] != values
[matches
])
550 pull_constant_loc
[i
/ 4] = j
/ 4;
555 if (pull_constant_loc
[i
/ 4] == -1) {
556 assert(prog_data
->nr_pull_params
% 4 == 0);
557 pull_constant_loc
[i
/ 4] = prog_data
->nr_pull_params
/ 4;
559 for (int j
= 0; j
< 4; j
++) {
560 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
566 /* Now actually rewrite usage of the things we've moved to pull
569 foreach_list_safe(node
, &this->instructions
) {
570 vec4_instruction
*inst
= (vec4_instruction
*)node
;
572 for (int i
= 0 ; i
< 3; i
++) {
573 if (inst
->src
[i
].file
!= UNIFORM
||
574 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
577 int uniform
= inst
->src
[i
].reg
;
579 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
581 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
582 pull_constant_loc
[uniform
]);
584 inst
->src
[i
].file
= temp
.file
;
585 inst
->src
[i
].reg
= temp
.reg
;
586 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
587 inst
->src
[i
].reladdr
= NULL
;
591 /* Repack push constants to remove the now-unused ones. */
592 pack_uniform_registers();
596 * Tries to reduce extra MOV instructions by taking GRFs that get just
597 * written and then MOVed into an MRF and making the original write of
598 * the GRF write directly to the MRF instead.
601 vec4_visitor::opt_compute_to_mrf()
603 bool progress
= false;
606 calculate_live_intervals();
608 foreach_list_safe(node
, &this->instructions
) {
609 vec4_instruction
*inst
= (vec4_instruction
*)node
;
614 if (inst
->opcode
!= BRW_OPCODE_MOV
||
616 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
617 inst
->dst
.type
!= inst
->src
[0].type
||
618 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
621 int mrf
= inst
->dst
.reg
;
623 /* Can't compute-to-MRF this GRF if someone else was going to
626 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
629 /* We need to check interference with the MRF between this
630 * instruction and the earliest instruction involved in writing
631 * the GRF we're eliminating. To do that, keep track of which
632 * of our source channels we've seen initialized.
634 bool chans_needed
[4] = {false, false, false, false};
635 int chans_remaining
= 0;
636 for (int i
= 0; i
< 4; i
++) {
637 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
639 if (!(inst
->dst
.writemask
& (1 << i
)))
642 /* We don't handle compute-to-MRF across a swizzle. We would
643 * need to be able to rewrite instructions above to output
644 * results to different channels.
649 if (!chans_needed
[chan
]) {
650 chans_needed
[chan
] = true;
654 if (chans_remaining
> 4)
657 /* Now walk up the instruction stream trying to see if we can
658 * rewrite everything writing to the GRF into the MRF instead.
660 vec4_instruction
*scan_inst
;
661 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
662 scan_inst
->prev
!= NULL
;
663 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
664 if (scan_inst
->dst
.file
== GRF
&&
665 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
666 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
667 /* Found something writing to the reg we want to turn into
671 /* SEND instructions can't have MRF as a destination. */
675 if (intel
->gen
>= 6) {
676 /* gen6 math instructions must have the destination be
677 * GRF, so no compute-to-MRF for them.
679 if (scan_inst
->is_math()) {
684 /* Mark which channels we found unconditional writes for. */
685 if (!scan_inst
->predicate
) {
686 for (int i
= 0; i
< 4; i
++) {
687 if (scan_inst
->dst
.writemask
& (1 << i
) &&
689 chans_needed
[i
] = false;
695 if (chans_remaining
== 0)
699 /* We don't handle flow control here. Most computation of
700 * values that end up in MRFs are shortly before the MRF
703 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
704 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
705 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
706 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
710 /* You can't read from an MRF, so if someone else reads our
711 * MRF's source GRF that we wanted to rewrite, that stops us.
713 bool interfered
= false;
714 for (int i
= 0; i
< 3; i
++) {
715 if (scan_inst
->src
[i
].file
== GRF
&&
716 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
717 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
724 /* If somebody else writes our MRF here, we can't
725 * compute-to-MRF before that.
727 if (scan_inst
->dst
.file
== MRF
&& mrf
== scan_inst
->dst
.reg
)
730 if (scan_inst
->mlen
> 0) {
731 /* Found a SEND instruction, which means that there are
732 * live values in MRFs from base_mrf to base_mrf +
733 * scan_inst->mlen - 1. Don't go pushing our MRF write up
736 if (mrf
>= scan_inst
->base_mrf
&&
737 mrf
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
743 if (chans_remaining
== 0) {
744 /* If we've made it here, we have an inst we want to
745 * compute-to-MRF, and a scan_inst pointing to the earliest
746 * instruction involved in computing the value. Now go
747 * rewrite the instruction stream between the two.
750 while (scan_inst
!= inst
) {
751 if (scan_inst
->dst
.file
== GRF
&&
752 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
753 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
754 scan_inst
->dst
.file
= MRF
;
755 scan_inst
->dst
.reg
= mrf
;
756 scan_inst
->dst
.reg_offset
= 0;
757 scan_inst
->dst
.writemask
&= inst
->dst
.writemask
;
758 scan_inst
->saturate
|= inst
->saturate
;
760 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
768 live_intervals_valid
= false;
774 * Splits virtual GRFs requesting more than one contiguous physical register.
776 * We initially create large virtual GRFs for temporary structures, arrays,
777 * and matrices, so that the dereference visitor functions can add reg_offsets
778 * to work their way down to the actual member being accessed.
780 * Unlike in the FS visitor, though, we have no SEND messages that return more
781 * than 1 register. We also don't do any array access in register space,
782 * which would have required contiguous physical registers. Thus, all those
783 * large virtual GRFs can be split up into independent single-register virtual
784 * GRFs, making allocation and optimization easier.
787 vec4_visitor::split_virtual_grfs()
789 int num_vars
= this->virtual_grf_count
;
790 int new_virtual_grf
[num_vars
];
792 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
794 /* Allocate new space for split regs. Note that the virtual
795 * numbers will be contiguous.
797 for (int i
= 0; i
< num_vars
; i
++) {
798 if (this->virtual_grf_sizes
[i
] == 1)
801 new_virtual_grf
[i
] = virtual_grf_alloc(1);
802 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
803 int reg
= virtual_grf_alloc(1);
804 assert(reg
== new_virtual_grf
[i
] + j
- 1);
807 this->virtual_grf_sizes
[i
] = 1;
810 foreach_list(node
, &this->instructions
) {
811 vec4_instruction
*inst
= (vec4_instruction
*)node
;
813 if (inst
->dst
.file
== GRF
&&
814 new_virtual_grf
[inst
->dst
.reg
] &&
815 inst
->dst
.reg_offset
!= 0) {
816 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
817 inst
->dst
.reg_offset
- 1);
818 inst
->dst
.reg_offset
= 0;
820 for (int i
= 0; i
< 3; i
++) {
821 if (inst
->src
[i
].file
== GRF
&&
822 new_virtual_grf
[inst
->src
[i
].reg
] &&
823 inst
->src
[i
].reg_offset
!= 0) {
824 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
825 inst
->src
[i
].reg_offset
- 1);
826 inst
->src
[i
].reg_offset
= 0;
830 this->live_intervals_valid
= false;
834 vec4_visitor::dump_instruction(vec4_instruction
*inst
)
836 if (inst
->opcode
< ARRAY_SIZE(opcode_descs
) &&
837 opcode_descs
[inst
->opcode
].name
) {
838 printf("%s ", opcode_descs
[inst
->opcode
].name
);
840 printf("op%d ", inst
->opcode
);
843 switch (inst
->dst
.file
) {
845 printf("vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
848 printf("m%d", inst
->dst
.reg
);
857 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
859 if (inst
->dst
.writemask
& 1)
861 if (inst
->dst
.writemask
& 2)
863 if (inst
->dst
.writemask
& 4)
865 if (inst
->dst
.writemask
& 8)
870 for (int i
= 0; i
< 3; i
++) {
871 switch (inst
->src
[i
].file
) {
873 printf("vgrf%d", inst
->src
[i
].reg
);
876 printf("attr%d", inst
->src
[i
].reg
);
879 printf("u%d", inst
->src
[i
].reg
);
889 if (inst
->src
[i
].reg_offset
)
890 printf(".%d", inst
->src
[i
].reg_offset
);
892 static const char *chans
[4] = {"x", "y", "z", "w"};
894 for (int c
= 0; c
< 4; c
++) {
895 printf("%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
906 vec4_visitor::dump_instructions()
909 foreach_list_safe(node
, &this->instructions
) {
910 vec4_instruction
*inst
= (vec4_instruction
*)node
;
911 printf("%d: ", ip
++);
912 dump_instruction(inst
);
916 } /* namespace brw */