2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "main/macros.h"
30 #include "main/shaderobj.h"
31 #include "program/prog_print.h"
32 #include "program/prog_parameter.h"
35 #define MAX_INSTRUCTION (1 << 30)
42 * Common helper for constructing swizzles. When only a subset of
43 * channels of a vec4 are used, we don't want to reference the other
44 * channels, as that will tell optimization passes that those other
48 swizzle_for_size(int size
)
50 static const unsigned size_swizzles
[4] = {
51 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
57 assert((size
>= 1) && (size
<= 4));
58 return size_swizzles
[size
- 1];
64 memset(this, 0, sizeof(*this));
66 this->file
= BAD_FILE
;
69 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
75 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
76 this->swizzle
= swizzle_for_size(type
->vector_elements
);
78 this->swizzle
= SWIZZLE_XYZW
;
81 /** Generic unset register constructor. */
87 src_reg::src_reg(float f
)
92 this->type
= BRW_REGISTER_TYPE_F
;
96 src_reg::src_reg(uint32_t u
)
101 this->type
= BRW_REGISTER_TYPE_UD
;
105 src_reg::src_reg(int32_t i
)
110 this->type
= BRW_REGISTER_TYPE_D
;
114 src_reg::src_reg(dst_reg reg
)
118 this->file
= reg
.file
;
120 this->reg_offset
= reg
.reg_offset
;
121 this->type
= reg
.type
;
122 this->reladdr
= reg
.reladdr
;
123 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
129 for (int i
= 0; i
< 4; i
++) {
130 if (!(reg
.writemask
& (1 << i
)))
133 swizzles
[next_chan
++] = last
= i
;
136 for (; next_chan
< 4; next_chan
++) {
137 swizzles
[next_chan
] = last
;
140 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
141 swizzles
[2], swizzles
[3]);
147 memset(this, 0, sizeof(*this));
148 this->file
= BAD_FILE
;
149 this->writemask
= WRITEMASK_XYZW
;
157 dst_reg::dst_reg(register_file file
, int reg
)
165 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
172 this->type
= brw_type_for_base_type(type
);
173 this->writemask
= writemask
;
176 dst_reg::dst_reg(struct brw_reg reg
)
181 this->fixed_hw_reg
= reg
;
184 dst_reg::dst_reg(src_reg reg
)
188 this->file
= reg
.file
;
190 this->reg_offset
= reg
.reg_offset
;
191 this->type
= reg
.type
;
192 /* How should we do writemasking when converting from a src_reg? It seems
193 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
194 * what about for src.wx? Just special-case src.xxxx for now.
196 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
197 this->writemask
= WRITEMASK_X
;
199 this->writemask
= WRITEMASK_XYZW
;
200 this->reladdr
= reg
.reladdr
;
201 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
205 vec4_instruction::is_send_from_grf()
208 case SHADER_OPCODE_SHADER_TIME_ADD
:
209 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
217 vec4_visitor::can_do_source_mods(vec4_instruction
*inst
)
219 if (brw
->gen
== 6 && inst
->is_math())
222 if (inst
->is_send_from_grf())
225 if (!inst
->can_do_source_mods())
232 * Returns how many MRFs an opcode will write over.
234 * Note that this is not the 0 or 1 implied writes in an actual gen
235 * instruction -- the generate_* functions generate additional MOVs
239 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
244 switch (inst
->opcode
) {
245 case SHADER_OPCODE_RCP
:
246 case SHADER_OPCODE_RSQ
:
247 case SHADER_OPCODE_SQRT
:
248 case SHADER_OPCODE_EXP2
:
249 case SHADER_OPCODE_LOG2
:
250 case SHADER_OPCODE_SIN
:
251 case SHADER_OPCODE_COS
:
253 case SHADER_OPCODE_INT_QUOTIENT
:
254 case SHADER_OPCODE_INT_REMAINDER
:
255 case SHADER_OPCODE_POW
:
257 case VS_OPCODE_URB_WRITE
:
259 case VS_OPCODE_PULL_CONSTANT_LOAD
:
261 case VS_OPCODE_SCRATCH_READ
:
263 case VS_OPCODE_SCRATCH_WRITE
:
265 case GS_OPCODE_URB_WRITE
:
266 case GS_OPCODE_THREAD_END
:
268 case SHADER_OPCODE_SHADER_TIME_ADD
:
270 case SHADER_OPCODE_TEX
:
271 case SHADER_OPCODE_TXL
:
272 case SHADER_OPCODE_TXD
:
273 case SHADER_OPCODE_TXF
:
274 case SHADER_OPCODE_TXF_MS
:
275 case SHADER_OPCODE_TXS
:
276 case SHADER_OPCODE_TG4
:
277 return inst
->header_present
? 1 : 0;
279 assert(!"not reached");
285 src_reg::equals(src_reg
*r
)
287 return (file
== r
->file
&&
289 reg_offset
== r
->reg_offset
&&
291 negate
== r
->negate
&&
293 swizzle
== r
->swizzle
&&
294 !reladdr
&& !r
->reladdr
&&
295 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
296 sizeof(fixed_hw_reg
)) == 0 &&
301 * Must be called after calculate_live_intervales() to remove unused
302 * writes to registers -- register allocation will fail otherwise
303 * because something deffed but not used won't be considered to
304 * interfere with other regs.
307 vec4_visitor::dead_code_eliminate()
309 bool progress
= false;
312 calculate_live_intervals();
314 foreach_list_safe(node
, &this->instructions
) {
315 vec4_instruction
*inst
= (vec4_instruction
*)node
;
317 if (inst
->dst
.file
== GRF
) {
318 assert(this->virtual_grf_end
[inst
->dst
.reg
] >= pc
);
319 if (this->virtual_grf_end
[inst
->dst
.reg
] == pc
) {
320 /* Don't dead code eliminate instructions that write to the
321 * accumulator as a side-effect. Instead just set the destination
322 * to the null register to free it.
324 switch (inst
->opcode
) {
325 case BRW_OPCODE_ADDC
:
326 case BRW_OPCODE_SUBB
:
327 case BRW_OPCODE_MACH
:
328 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
342 live_intervals_valid
= false;
348 vec4_visitor::split_uniform_registers()
350 /* Prior to this, uniforms have been in an array sized according to
351 * the number of vector uniforms present, sparsely filled (so an
352 * aggregate results in reg indices being skipped over). Now we're
353 * going to cut those aggregates up so each .reg index is one
354 * vector. The goal is to make elimination of unused uniform
355 * components easier later.
357 foreach_list(node
, &this->instructions
) {
358 vec4_instruction
*inst
= (vec4_instruction
*)node
;
360 for (int i
= 0 ; i
< 3; i
++) {
361 if (inst
->src
[i
].file
!= UNIFORM
)
364 assert(!inst
->src
[i
].reladdr
);
366 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
367 inst
->src
[i
].reg_offset
= 0;
371 /* Update that everything is now vector-sized. */
372 for (int i
= 0; i
< this->uniforms
; i
++) {
373 this->uniform_size
[i
] = 1;
378 vec4_visitor::pack_uniform_registers()
380 bool uniform_used
[this->uniforms
];
381 int new_loc
[this->uniforms
];
382 int new_chan
[this->uniforms
];
384 memset(uniform_used
, 0, sizeof(uniform_used
));
385 memset(new_loc
, 0, sizeof(new_loc
));
386 memset(new_chan
, 0, sizeof(new_chan
));
388 /* Find which uniform vectors are actually used by the program. We
389 * expect unused vector elements when we've moved array access out
390 * to pull constants, and from some GLSL code generators like wine.
392 foreach_list(node
, &this->instructions
) {
393 vec4_instruction
*inst
= (vec4_instruction
*)node
;
395 for (int i
= 0 ; i
< 3; i
++) {
396 if (inst
->src
[i
].file
!= UNIFORM
)
399 uniform_used
[inst
->src
[i
].reg
] = true;
403 int new_uniform_count
= 0;
405 /* Now, figure out a packing of the live uniform vectors into our
408 for (int src
= 0; src
< uniforms
; src
++) {
409 int size
= this->uniform_vector_size
[src
];
411 if (!uniform_used
[src
]) {
412 this->uniform_vector_size
[src
] = 0;
417 /* Find the lowest place we can slot this uniform in. */
418 for (dst
= 0; dst
< src
; dst
++) {
419 if (this->uniform_vector_size
[dst
] + size
<= 4)
428 new_chan
[src
] = this->uniform_vector_size
[dst
];
430 /* Move the references to the data */
431 for (int j
= 0; j
< size
; j
++) {
432 prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
433 prog_data
->param
[src
* 4 + j
];
436 this->uniform_vector_size
[dst
] += size
;
437 this->uniform_vector_size
[src
] = 0;
440 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
443 this->uniforms
= new_uniform_count
;
445 /* Now, update the instructions for our repacked uniforms. */
446 foreach_list(node
, &this->instructions
) {
447 vec4_instruction
*inst
= (vec4_instruction
*)node
;
449 for (int i
= 0 ; i
< 3; i
++) {
450 int src
= inst
->src
[i
].reg
;
452 if (inst
->src
[i
].file
!= UNIFORM
)
455 inst
->src
[i
].reg
= new_loc
[src
];
457 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
458 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
459 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
460 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
461 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
467 src_reg::is_zero() const
472 if (type
== BRW_REGISTER_TYPE_F
) {
480 src_reg::is_one() const
485 if (type
== BRW_REGISTER_TYPE_F
) {
493 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
495 * While GLSL IR also performs this optimization, we end up with it in
496 * our instruction stream for a couple of reasons. One is that we
497 * sometimes generate silly instructions, for example in array access
498 * where we'll generate "ADD offset, index, base" even if base is 0.
499 * The other is that GLSL IR's constant propagation doesn't track the
500 * components of aggregates, so some VS patterns (initialize matrix to
501 * 0, accumulate in vertex blending factors) end up breaking down to
502 * instructions involving 0.
505 vec4_visitor::opt_algebraic()
507 bool progress
= false;
509 foreach_list(node
, &this->instructions
) {
510 vec4_instruction
*inst
= (vec4_instruction
*)node
;
512 switch (inst
->opcode
) {
514 if (inst
->src
[1].is_zero()) {
515 inst
->opcode
= BRW_OPCODE_MOV
;
516 inst
->src
[1] = src_reg();
522 if (inst
->src
[1].is_zero()) {
523 inst
->opcode
= BRW_OPCODE_MOV
;
524 switch (inst
->src
[0].type
) {
525 case BRW_REGISTER_TYPE_F
:
526 inst
->src
[0] = src_reg(0.0f
);
528 case BRW_REGISTER_TYPE_D
:
529 inst
->src
[0] = src_reg(0);
531 case BRW_REGISTER_TYPE_UD
:
532 inst
->src
[0] = src_reg(0u);
535 assert(!"not reached");
536 inst
->src
[0] = src_reg(0.0f
);
539 inst
->src
[1] = src_reg();
541 } else if (inst
->src
[1].is_one()) {
542 inst
->opcode
= BRW_OPCODE_MOV
;
543 inst
->src
[1] = src_reg();
553 this->live_intervals_valid
= false;
559 * Only a limited number of hardware registers may be used for push
560 * constants, so this turns access to the overflowed constants into
564 vec4_visitor::move_push_constants_to_pull_constants()
566 int pull_constant_loc
[this->uniforms
];
568 /* Only allow 32 registers (256 uniform components) as push constants,
569 * which is the limit on gen6.
571 int max_uniform_components
= 32 * 8;
572 if (this->uniforms
* 4 <= max_uniform_components
)
575 /* Make some sort of choice as to which uniforms get sent to pull
576 * constants. We could potentially do something clever here like
577 * look for the most infrequently used uniform vec4s, but leave
580 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
581 pull_constant_loc
[i
/ 4] = -1;
583 if (i
>= max_uniform_components
) {
584 const float **values
= &prog_data
->param
[i
];
586 /* Try to find an existing copy of this uniform in the pull
587 * constants if it was part of an array access already.
589 for (unsigned int j
= 0; j
< prog_data
->nr_pull_params
; j
+= 4) {
592 for (matches
= 0; matches
< 4; matches
++) {
593 if (prog_data
->pull_param
[j
+ matches
] != values
[matches
])
598 pull_constant_loc
[i
/ 4] = j
/ 4;
603 if (pull_constant_loc
[i
/ 4] == -1) {
604 assert(prog_data
->nr_pull_params
% 4 == 0);
605 pull_constant_loc
[i
/ 4] = prog_data
->nr_pull_params
/ 4;
607 for (int j
= 0; j
< 4; j
++) {
608 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
614 /* Now actually rewrite usage of the things we've moved to pull
617 foreach_list_safe(node
, &this->instructions
) {
618 vec4_instruction
*inst
= (vec4_instruction
*)node
;
620 for (int i
= 0 ; i
< 3; i
++) {
621 if (inst
->src
[i
].file
!= UNIFORM
||
622 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
625 int uniform
= inst
->src
[i
].reg
;
627 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
629 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
630 pull_constant_loc
[uniform
]);
632 inst
->src
[i
].file
= temp
.file
;
633 inst
->src
[i
].reg
= temp
.reg
;
634 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
635 inst
->src
[i
].reladdr
= NULL
;
639 /* Repack push constants to remove the now-unused ones. */
640 pack_uniform_registers();
644 * Sets the dependency control fields on instructions after register
645 * allocation and before the generator is run.
647 * When you have a sequence of instructions like:
649 * DP4 temp.x vertex uniform[0]
650 * DP4 temp.y vertex uniform[0]
651 * DP4 temp.z vertex uniform[0]
652 * DP4 temp.w vertex uniform[0]
654 * The hardware doesn't know that it can actually run the later instructions
655 * while the previous ones are in flight, producing stalls. However, we have
656 * manual fields we can set in the instructions that let it do so.
659 vec4_visitor::opt_set_dependency_control()
661 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
662 uint8_t grf_channels_written
[BRW_MAX_GRF
];
663 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
664 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
668 assert(prog_data
->total_grf
||
669 !"Must be called after register allocation");
671 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
672 bblock_t
*bblock
= cfg
.blocks
[i
];
673 vec4_instruction
*inst
;
675 memset(last_grf_write
, 0, sizeof(last_grf_write
));
676 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
678 for (inst
= (vec4_instruction
*)bblock
->start
;
679 inst
!= (vec4_instruction
*)bblock
->end
->next
;
680 inst
= (vec4_instruction
*)inst
->next
) {
681 /* If we read from a register that we were doing dependency control
682 * on, don't do dependency control across the read.
684 for (int i
= 0; i
< 3; i
++) {
685 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
686 if (inst
->src
[i
].file
== GRF
) {
687 last_grf_write
[reg
] = NULL
;
688 } else if (inst
->src
[i
].file
== HW_REG
) {
689 memset(last_grf_write
, 0, sizeof(last_grf_write
));
692 assert(inst
->src
[i
].file
!= MRF
);
695 /* In the presence of send messages, totally interrupt dependency
696 * control. They're long enough that the chance of dependency
697 * control around them just doesn't matter.
700 memset(last_grf_write
, 0, sizeof(last_grf_write
));
701 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
705 /* It looks like setting dependency control on a predicated
706 * instruction hangs the GPU.
708 if (inst
->predicate
) {
709 memset(last_grf_write
, 0, sizeof(last_grf_write
));
710 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
714 /* Now, see if we can do dependency control for this instruction
715 * against a previous one writing to its destination.
717 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
718 if (inst
->dst
.file
== GRF
) {
719 if (last_grf_write
[reg
] &&
720 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
721 last_grf_write
[reg
]->no_dd_clear
= true;
722 inst
->no_dd_check
= true;
724 grf_channels_written
[reg
] = 0;
727 last_grf_write
[reg
] = inst
;
728 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
729 } else if (inst
->dst
.file
== MRF
) {
730 if (last_mrf_write
[reg
] &&
731 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
732 last_mrf_write
[reg
]->no_dd_clear
= true;
733 inst
->no_dd_check
= true;
735 mrf_channels_written
[reg
] = 0;
738 last_mrf_write
[reg
] = inst
;
739 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
740 } else if (inst
->dst
.reg
== HW_REG
) {
741 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
742 memset(last_grf_write
, 0, sizeof(last_grf_write
));
743 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
744 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
751 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
755 /* If this instruction sets anything not referenced by swizzle, then we'd
756 * totally break it when we reswizzle.
758 if (dst
.writemask
& ~swizzle_mask
)
767 /* Check if there happens to be no reswizzling required. */
768 for (int c
= 0; c
< 4; c
++) {
769 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
770 /* Skip components of the swizzle not used by the dst. */
771 if (!(dst_writemask
& (1 << c
)))
774 /* We don't do the reswizzling yet, so just sanity check that we
785 * For any channels in the swizzle's source that were populated by this
786 * instruction, rewrite the instruction to put the appropriate result directly
789 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
792 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
794 int new_writemask
= 0;
800 for (int c
= 0; c
< 4; c
++) {
801 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
802 /* Skip components of the swizzle not used by the dst. */
803 if (!(dst_writemask
& (1 << c
)))
805 /* If we were populating this component, then populate the
806 * corresponding channel of the new dst.
808 if (dst
.writemask
& bit
)
809 new_writemask
|= (1 << c
);
811 dst
.writemask
= new_writemask
;
814 for (int c
= 0; c
< 4; c
++) {
815 /* Skip components of the swizzle not used by the dst. */
816 if (!(dst_writemask
& (1 << c
)))
819 /* We don't do the reswizzling yet, so just sanity check that we
822 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
829 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
830 * just written and then MOVed into another reg and making the original write
831 * of the GRF write directly to the final destination instead.
834 vec4_visitor::opt_register_coalesce()
836 bool progress
= false;
839 calculate_live_intervals();
841 foreach_list_safe(node
, &this->instructions
) {
842 vec4_instruction
*inst
= (vec4_instruction
*)node
;
847 if (inst
->opcode
!= BRW_OPCODE_MOV
||
848 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
850 inst
->src
[0].file
!= GRF
||
851 inst
->dst
.type
!= inst
->src
[0].type
||
852 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
855 bool to_mrf
= (inst
->dst
.file
== MRF
);
857 /* Can't coalesce this GRF if someone else was going to
860 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
863 /* We need to check interference with the final destination between this
864 * instruction and the earliest instruction involved in writing the GRF
865 * we're eliminating. To do that, keep track of which of our source
866 * channels we've seen initialized.
868 bool chans_needed
[4] = {false, false, false, false};
869 int chans_remaining
= 0;
870 int swizzle_mask
= 0;
871 for (int i
= 0; i
< 4; i
++) {
872 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
874 if (!(inst
->dst
.writemask
& (1 << i
)))
877 swizzle_mask
|= (1 << chan
);
879 if (!chans_needed
[chan
]) {
880 chans_needed
[chan
] = true;
885 /* Now walk up the instruction stream trying to see if we can rewrite
886 * everything writing to the temporary to write into the destination
889 vec4_instruction
*scan_inst
;
890 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
891 scan_inst
->prev
!= NULL
;
892 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
893 if (scan_inst
->dst
.file
== GRF
&&
894 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
895 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
896 /* Found something writing to the reg we want to coalesce away. */
898 /* SEND instructions can't have MRF as a destination. */
903 /* gen6 math instructions must have the destination be
904 * GRF, so no compute-to-MRF for them.
906 if (scan_inst
->is_math()) {
912 /* If we can't handle the swizzle, bail. */
913 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
914 inst
->src
[0].swizzle
,
919 /* Mark which channels we found unconditional writes for. */
920 if (!scan_inst
->predicate
) {
921 for (int i
= 0; i
< 4; i
++) {
922 if (scan_inst
->dst
.writemask
& (1 << i
) &&
924 chans_needed
[i
] = false;
930 if (chans_remaining
== 0)
934 /* We don't handle flow control here. Most computation of values
935 * that could be coalesced happens just before their use.
937 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
938 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
939 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
940 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
944 /* You can't read from an MRF, so if someone else reads our MRF's
945 * source GRF that we wanted to rewrite, that stops us. If it's a
946 * GRF we're trying to coalesce to, we don't actually handle
947 * rewriting sources so bail in that case as well.
949 bool interfered
= false;
950 for (int i
= 0; i
< 3; i
++) {
951 if (scan_inst
->src
[i
].file
== GRF
&&
952 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
953 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
960 /* If somebody else writes our destination here, we can't coalesce
963 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
964 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
968 /* Check for reads of the register we're trying to coalesce into. We
969 * can't go rewriting instructions above that to put some other value
970 * in the register instead.
972 if (to_mrf
&& scan_inst
->mlen
> 0) {
973 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
974 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
978 for (int i
= 0; i
< 3; i
++) {
979 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
980 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
981 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
990 if (chans_remaining
== 0) {
991 /* If we've made it here, we have an MOV we want to coalesce out, and
992 * a scan_inst pointing to the earliest instruction involved in
993 * computing the value. Now go rewrite the instruction stream
997 while (scan_inst
!= inst
) {
998 if (scan_inst
->dst
.file
== GRF
&&
999 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1000 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1001 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
1002 inst
->src
[0].swizzle
);
1003 scan_inst
->dst
.file
= inst
->dst
.file
;
1004 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1005 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1006 scan_inst
->saturate
|= inst
->saturate
;
1008 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1016 live_intervals_valid
= false;
1022 * Splits virtual GRFs requesting more than one contiguous physical register.
1024 * We initially create large virtual GRFs for temporary structures, arrays,
1025 * and matrices, so that the dereference visitor functions can add reg_offsets
1026 * to work their way down to the actual member being accessed. But when it
1027 * comes to optimization, we'd like to treat each register as individual
1028 * storage if possible.
1030 * So far, the only thing that might prevent splitting is a send message from
1034 vec4_visitor::split_virtual_grfs()
1036 int num_vars
= this->virtual_grf_count
;
1037 int new_virtual_grf
[num_vars
];
1038 bool split_grf
[num_vars
];
1040 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1042 /* Try to split anything > 0 sized. */
1043 for (int i
= 0; i
< num_vars
; i
++) {
1044 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1047 /* Check that the instructions are compatible with the registers we're trying
1050 foreach_list(node
, &this->instructions
) {
1051 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1053 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1056 if (inst
->is_send_from_grf()) {
1057 for (int i
= 0; i
< 3; i
++) {
1058 if (inst
->src
[i
].file
== GRF
) {
1059 split_grf
[inst
->src
[i
].reg
] = false;
1065 /* Allocate new space for split regs. Note that the virtual
1066 * numbers will be contiguous.
1068 for (int i
= 0; i
< num_vars
; i
++) {
1072 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1073 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1074 int reg
= virtual_grf_alloc(1);
1075 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1078 this->virtual_grf_sizes
[i
] = 1;
1081 foreach_list(node
, &this->instructions
) {
1082 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1084 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1085 inst
->dst
.reg_offset
!= 0) {
1086 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1087 inst
->dst
.reg_offset
- 1);
1088 inst
->dst
.reg_offset
= 0;
1090 for (int i
= 0; i
< 3; i
++) {
1091 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1092 inst
->src
[i
].reg_offset
!= 0) {
1093 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1094 inst
->src
[i
].reg_offset
- 1);
1095 inst
->src
[i
].reg_offset
= 0;
1099 this->live_intervals_valid
= false;
1103 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1105 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1107 printf("%s ", brw_instruction_name(inst
->opcode
));
1109 switch (inst
->dst
.file
) {
1111 printf("vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1114 printf("m%d", inst
->dst
.reg
);
1123 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1125 if (inst
->dst
.writemask
& 1)
1127 if (inst
->dst
.writemask
& 2)
1129 if (inst
->dst
.writemask
& 4)
1131 if (inst
->dst
.writemask
& 8)
1136 for (int i
= 0; i
< 3; i
++) {
1137 switch (inst
->src
[i
].file
) {
1139 printf("vgrf%d", inst
->src
[i
].reg
);
1142 printf("attr%d", inst
->src
[i
].reg
);
1145 printf("u%d", inst
->src
[i
].reg
);
1148 switch (inst
->src
[i
].type
) {
1149 case BRW_REGISTER_TYPE_F
:
1150 printf("%fF", inst
->src
[i
].imm
.f
);
1152 case BRW_REGISTER_TYPE_D
:
1153 printf("%dD", inst
->src
[i
].imm
.i
);
1155 case BRW_REGISTER_TYPE_UD
:
1156 printf("%uU", inst
->src
[i
].imm
.u
);
1171 if (inst
->src
[i
].reg_offset
)
1172 printf(".%d", inst
->src
[i
].reg_offset
);
1174 static const char *chans
[4] = {"x", "y", "z", "w"};
1176 for (int c
= 0; c
< 4; c
++) {
1177 printf("%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1188 * Replace each register of type ATTR in this->instructions with a reference
1189 * to a fixed HW register.
1192 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
)
1194 foreach_list(node
, &this->instructions
) {
1195 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1197 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1198 if (inst
->dst
.file
== ATTR
) {
1199 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1201 /* All attributes used in the shader need to have been assigned a
1202 * hardware register by the caller
1206 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1207 reg
.type
= inst
->dst
.type
;
1208 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1210 inst
->dst
.file
= HW_REG
;
1211 inst
->dst
.fixed_hw_reg
= reg
;
1214 for (int i
= 0; i
< 3; i
++) {
1215 if (inst
->src
[i
].file
!= ATTR
)
1218 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1220 /* All attributes used in the shader need to have been assigned a
1221 * hardware register by the caller
1225 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1226 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1227 reg
.type
= inst
->src
[i
].type
;
1228 if (inst
->src
[i
].abs
)
1230 if (inst
->src
[i
].negate
)
1233 inst
->src
[i
].file
= HW_REG
;
1234 inst
->src
[i
].fixed_hw_reg
= reg
;
1240 vec4_vs_visitor::setup_attributes(int payload_reg
)
1243 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1244 memset(attribute_map
, 0, sizeof(attribute_map
));
1247 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1248 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1249 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1254 /* VertexID is stored by the VF as the last vertex element, but we
1255 * don't represent it with a flag in inputs_read, so we call it
1258 if (vs_prog_data
->uses_vertexid
) {
1259 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1263 lower_attributes_to_hw_regs(attribute_map
);
1265 /* The BSpec says we always have to read at least one thing from
1266 * the VF, and it appears that the hardware wedges otherwise.
1268 if (nr_attributes
== 0)
1271 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1273 unsigned vue_entries
=
1274 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1277 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1279 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1281 return payload_reg
+ nr_attributes
;
1285 vec4_visitor::setup_uniforms(int reg
)
1287 prog_data
->dispatch_grf_start_reg
= reg
;
1289 /* The pre-gen6 VS requires that some push constants get loaded no
1290 * matter what, or the GPU would hang.
1292 if (brw
->gen
< 6 && this->uniforms
== 0) {
1293 this->uniform_vector_size
[this->uniforms
] = 1;
1295 prog_data
->param
= reralloc(NULL
, prog_data
->param
, const float *, 4);
1296 for (unsigned int i
= 0; i
< 4; i
++) {
1297 unsigned int slot
= this->uniforms
* 4 + i
;
1298 static float zero
= 0.0;
1299 prog_data
->param
[slot
] = &zero
;
1305 reg
+= ALIGN(uniforms
, 2) / 2;
1308 prog_data
->nr_params
= this->uniforms
* 4;
1310 prog_data
->curb_read_length
= reg
- prog_data
->dispatch_grf_start_reg
;
1316 vec4_vs_visitor::setup_payload(void)
1320 /* The payload always contains important data in g0, which contains
1321 * the URB handles that are passed on to the URB write at the end
1322 * of the thread. So, we always start push constants at g1.
1326 reg
= setup_uniforms(reg
);
1328 reg
= setup_attributes(reg
);
1330 this->first_non_payload_grf
= reg
;
1334 vec4_visitor::get_timestamp()
1336 assert(brw
->gen
>= 7);
1338 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1341 BRW_REGISTER_TYPE_UD
,
1342 BRW_VERTICAL_STRIDE_0
,
1344 BRW_HORIZONTAL_STRIDE_4
,
1348 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1350 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1351 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1352 * even if it's not enabled in the dispatch.
1354 mov
->force_writemask_all
= true;
1356 return src_reg(dst
);
1360 vec4_visitor::emit_shader_time_begin()
1362 current_annotation
= "shader time start";
1363 shader_start_time
= get_timestamp();
1367 vec4_visitor::emit_shader_time_end()
1369 current_annotation
= "shader time end";
1370 src_reg shader_end_time
= get_timestamp();
1373 /* Check that there weren't any timestamp reset events (assuming these
1374 * were the only two timestamp reads that happened).
1376 src_reg reset_end
= shader_end_time
;
1377 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1378 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1379 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1381 emit(IF(BRW_PREDICATE_NORMAL
));
1383 /* Take the current timestamp and get the delta. */
1384 shader_start_time
.negate
= true;
1385 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1386 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1388 /* If there were no instructions between the two timestamp gets, the diff
1389 * is 2 cycles. Remove that overhead, so I can forget about that when
1390 * trying to determine the time taken for single instructions.
1392 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1394 emit_shader_time_write(ST_VS
, src_reg(diff
));
1395 emit_shader_time_write(ST_VS_WRITTEN
, src_reg(1u));
1396 emit(BRW_OPCODE_ELSE
);
1397 emit_shader_time_write(ST_VS_RESET
, src_reg(1u));
1398 emit(BRW_OPCODE_ENDIF
);
1402 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1405 int shader_time_index
=
1406 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1409 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1411 dst_reg offset
= dst
;
1415 offset
.type
= BRW_REGISTER_TYPE_UD
;
1416 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1418 time
.type
= BRW_REGISTER_TYPE_UD
;
1419 emit(MOV(time
, src_reg(value
)));
1421 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1425 vec4_visitor::assign_binding_table_offsets()
1427 prog_data
->base
.binding_table
.texture_start
= SURF_INDEX_VEC4_TEXTURE(0);
1428 prog_data
->base
.binding_table
.ubo_start
= SURF_INDEX_VEC4_UBO(0);
1429 prog_data
->base
.binding_table
.shader_time_start
= SURF_INDEX_VEC4_SHADER_TIME
;
1430 prog_data
->base
.binding_table
.gather_texture_start
= SURF_INDEX_VEC4_GATHER_TEXTURE(0);
1431 prog_data
->base
.binding_table
.pull_constants_start
= SURF_INDEX_VEC4_CONST_BUFFER
;
1433 /* prog_data->base.binding_table.size will be set by mark_surface_used. */
1439 sanity_param_count
= prog
->Parameters
->NumParameters
;
1441 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1442 emit_shader_time_begin();
1444 assign_binding_table_offsets();
1448 /* Generate VS IR for main(). (the visitor only descends into
1449 * functions called "main").
1452 visit_instructions(shader
->ir
);
1454 emit_program_code();
1458 if (key
->userclip_active
&& !key
->uses_clip_distance
)
1459 setup_uniform_clipplane_values();
1463 /* Before any optimization, push array accesses out to scratch
1464 * space where we need them to be. This pass may allocate new
1465 * virtual GRFs, so we want to do it early. It also makes sure
1466 * that we have reladdr computations available for CSE, since we'll
1467 * often do repeated subexpressions for those.
1470 move_grf_array_access_to_scratch();
1471 move_uniform_array_access_to_pull_constants();
1473 /* The ARB_vertex_program frontend emits pull constant loads directly
1474 * rather than using reladdr, so we don't need to walk through all the
1475 * instructions looking for things to move. There isn't anything.
1477 * We do still need to split things to vec4 size.
1479 split_uniform_registers();
1481 pack_uniform_registers();
1482 move_push_constants_to_pull_constants();
1483 split_virtual_grfs();
1488 progress
= dead_code_eliminate() || progress
;
1489 progress
= opt_copy_propagation() || progress
;
1490 progress
= opt_algebraic() || progress
;
1491 progress
= opt_register_coalesce() || progress
;
1501 /* Debug of register spilling: Go spill everything. */
1502 const int grf_count
= virtual_grf_count
;
1503 float spill_costs
[virtual_grf_count
];
1504 bool no_spill
[virtual_grf_count
];
1505 evaluate_spill_costs(spill_costs
, no_spill
);
1506 for (int i
= 0; i
< grf_count
; i
++) {
1513 while (!reg_allocate()) {
1518 opt_schedule_instructions();
1520 opt_set_dependency_control();
1522 /* If any state parameters were appended, then ParameterValues could have
1523 * been realloced, in which case the driver uniform storage set up by
1524 * _mesa_associate_uniform_storage() would point to freed memory. Make
1525 * sure that didn't happen.
1527 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1532 } /* namespace brw */
1537 * Compile a vertex shader.
1539 * Returns the final assembly and the program's size.
1542 brw_vs_emit(struct brw_context
*brw
,
1543 struct gl_shader_program
*prog
,
1544 struct brw_vs_compile
*c
,
1545 struct brw_vs_prog_data
*prog_data
,
1547 unsigned *final_assembly_size
)
1549 bool start_busy
= false;
1550 float start_time
= 0;
1552 if (unlikely(brw
->perf_debug
)) {
1553 start_busy
= (brw
->batch
.last_bo
&&
1554 drm_intel_bo_busy(brw
->batch
.last_bo
));
1555 start_time
= get_time();
1558 struct brw_shader
*shader
= NULL
;
1560 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1562 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1564 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
1565 _mesa_print_ir(shader
->ir
, NULL
);
1568 printf("ARB_vertex_program %d for native vertex shader\n",
1569 c
->vp
->program
.Base
.Id
);
1570 _mesa_print_program(&c
->vp
->program
.Base
);
1574 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, shader
, mem_ctx
);
1577 prog
->LinkStatus
= false;
1578 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1581 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1587 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
, mem_ctx
,
1588 INTEL_DEBUG
& DEBUG_VS
);
1589 const unsigned *generated
=g
.generate_assembly(&v
.instructions
,
1590 final_assembly_size
);
1592 if (unlikely(brw
->perf_debug
) && shader
) {
1593 if (shader
->compiled_once
) {
1594 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1596 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1597 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1598 (get_time() - start_time
) * 1000);
1600 shader
->compiled_once
= true;
1608 brw_vec4_prog_data_compare(const struct brw_vec4_prog_data
*a
,
1609 const struct brw_vec4_prog_data
*b
)
1611 /* Compare all the struct (including the base) up to the pointers. */
1612 if (memcmp(a
, b
, offsetof(struct brw_vec4_prog_data
, param
)))
1615 if (memcmp(a
->param
, b
->param
, a
->nr_params
* sizeof(void *)))
1618 if (memcmp(a
->pull_param
, b
->pull_param
, a
->nr_pull_params
* sizeof(void *)))
1626 brw_vec4_prog_data_free(const struct brw_vec4_prog_data
*prog_data
)
1628 ralloc_free((void *)prog_data
->param
);
1629 ralloc_free((void *)prog_data
->pull_param
);