2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "main/macros.h"
30 #include "main/shaderobj.h"
31 #include "program/prog_print.h"
32 #include "program/prog_parameter.h"
35 #define MAX_INSTRUCTION (1 << 30)
42 * Common helper for constructing swizzles. When only a subset of
43 * channels of a vec4 are used, we don't want to reference the other
44 * channels, as that will tell optimization passes that those other
48 swizzle_for_size(int size
)
50 static const unsigned size_swizzles
[4] = {
51 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
57 assert((size
>= 1) && (size
<= 4));
58 return size_swizzles
[size
- 1];
64 memset(this, 0, sizeof(*this));
66 this->file
= BAD_FILE
;
69 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
75 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
76 this->swizzle
= swizzle_for_size(type
->vector_elements
);
78 this->swizzle
= SWIZZLE_XYZW
;
81 /** Generic unset register constructor. */
87 src_reg::src_reg(float f
)
92 this->type
= BRW_REGISTER_TYPE_F
;
96 src_reg::src_reg(uint32_t u
)
101 this->type
= BRW_REGISTER_TYPE_UD
;
105 src_reg::src_reg(int32_t i
)
110 this->type
= BRW_REGISTER_TYPE_D
;
114 src_reg::src_reg(dst_reg reg
)
118 this->file
= reg
.file
;
120 this->reg_offset
= reg
.reg_offset
;
121 this->type
= reg
.type
;
122 this->reladdr
= reg
.reladdr
;
123 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
129 for (int i
= 0; i
< 4; i
++) {
130 if (!(reg
.writemask
& (1 << i
)))
133 swizzles
[next_chan
++] = last
= i
;
136 for (; next_chan
< 4; next_chan
++) {
137 swizzles
[next_chan
] = last
;
140 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
141 swizzles
[2], swizzles
[3]);
147 memset(this, 0, sizeof(*this));
148 this->file
= BAD_FILE
;
149 this->writemask
= WRITEMASK_XYZW
;
157 dst_reg::dst_reg(register_file file
, int reg
)
165 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
172 this->type
= brw_type_for_base_type(type
);
173 this->writemask
= writemask
;
176 dst_reg::dst_reg(struct brw_reg reg
)
181 this->fixed_hw_reg
= reg
;
184 dst_reg::dst_reg(src_reg reg
)
188 this->file
= reg
.file
;
190 this->reg_offset
= reg
.reg_offset
;
191 this->type
= reg
.type
;
192 /* How should we do writemasking when converting from a src_reg? It seems
193 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
194 * what about for src.wx? Just special-case src.xxxx for now.
196 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
197 this->writemask
= WRITEMASK_X
;
199 this->writemask
= WRITEMASK_XYZW
;
200 this->reladdr
= reg
.reladdr
;
201 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
205 vec4_instruction::is_send_from_grf()
208 case SHADER_OPCODE_SHADER_TIME_ADD
:
209 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
217 vec4_visitor::can_do_source_mods(vec4_instruction
*inst
)
219 if (brw
->gen
== 6 && inst
->is_math())
222 if (inst
->is_send_from_grf())
229 * Returns how many MRFs an opcode will write over.
231 * Note that this is not the 0 or 1 implied writes in an actual gen
232 * instruction -- the generate_* functions generate additional MOVs
236 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
241 switch (inst
->opcode
) {
242 case SHADER_OPCODE_RCP
:
243 case SHADER_OPCODE_RSQ
:
244 case SHADER_OPCODE_SQRT
:
245 case SHADER_OPCODE_EXP2
:
246 case SHADER_OPCODE_LOG2
:
247 case SHADER_OPCODE_SIN
:
248 case SHADER_OPCODE_COS
:
250 case SHADER_OPCODE_INT_QUOTIENT
:
251 case SHADER_OPCODE_INT_REMAINDER
:
252 case SHADER_OPCODE_POW
:
254 case VS_OPCODE_URB_WRITE
:
256 case VS_OPCODE_PULL_CONSTANT_LOAD
:
258 case VS_OPCODE_SCRATCH_READ
:
260 case VS_OPCODE_SCRATCH_WRITE
:
262 case GS_OPCODE_URB_WRITE
:
263 case GS_OPCODE_THREAD_END
:
265 case SHADER_OPCODE_SHADER_TIME_ADD
:
267 case SHADER_OPCODE_TEX
:
268 case SHADER_OPCODE_TXL
:
269 case SHADER_OPCODE_TXD
:
270 case SHADER_OPCODE_TXF
:
271 case SHADER_OPCODE_TXF_MS
:
272 case SHADER_OPCODE_TXS
:
273 return inst
->header_present
? 1 : 0;
275 assert(!"not reached");
281 src_reg::equals(src_reg
*r
)
283 return (file
== r
->file
&&
285 reg_offset
== r
->reg_offset
&&
287 negate
== r
->negate
&&
289 swizzle
== r
->swizzle
&&
290 !reladdr
&& !r
->reladdr
&&
291 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
292 sizeof(fixed_hw_reg
)) == 0 &&
297 * Must be called after calculate_live_intervales() to remove unused
298 * writes to registers -- register allocation will fail otherwise
299 * because something deffed but not used won't be considered to
300 * interfere with other regs.
303 vec4_visitor::dead_code_eliminate()
305 bool progress
= false;
308 calculate_live_intervals();
310 foreach_list_safe(node
, &this->instructions
) {
311 vec4_instruction
*inst
= (vec4_instruction
*)node
;
313 if (inst
->dst
.file
== GRF
) {
314 assert(this->virtual_grf_end
[inst
->dst
.reg
] >= pc
);
315 if (this->virtual_grf_end
[inst
->dst
.reg
] == pc
) {
325 live_intervals_valid
= false;
331 vec4_visitor::split_uniform_registers()
333 /* Prior to this, uniforms have been in an array sized according to
334 * the number of vector uniforms present, sparsely filled (so an
335 * aggregate results in reg indices being skipped over). Now we're
336 * going to cut those aggregates up so each .reg index is one
337 * vector. The goal is to make elimination of unused uniform
338 * components easier later.
340 foreach_list(node
, &this->instructions
) {
341 vec4_instruction
*inst
= (vec4_instruction
*)node
;
343 for (int i
= 0 ; i
< 3; i
++) {
344 if (inst
->src
[i
].file
!= UNIFORM
)
347 assert(!inst
->src
[i
].reladdr
);
349 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
350 inst
->src
[i
].reg_offset
= 0;
354 /* Update that everything is now vector-sized. */
355 for (int i
= 0; i
< this->uniforms
; i
++) {
356 this->uniform_size
[i
] = 1;
361 vec4_visitor::pack_uniform_registers()
363 bool uniform_used
[this->uniforms
];
364 int new_loc
[this->uniforms
];
365 int new_chan
[this->uniforms
];
367 memset(uniform_used
, 0, sizeof(uniform_used
));
368 memset(new_loc
, 0, sizeof(new_loc
));
369 memset(new_chan
, 0, sizeof(new_chan
));
371 /* Find which uniform vectors are actually used by the program. We
372 * expect unused vector elements when we've moved array access out
373 * to pull constants, and from some GLSL code generators like wine.
375 foreach_list(node
, &this->instructions
) {
376 vec4_instruction
*inst
= (vec4_instruction
*)node
;
378 for (int i
= 0 ; i
< 3; i
++) {
379 if (inst
->src
[i
].file
!= UNIFORM
)
382 uniform_used
[inst
->src
[i
].reg
] = true;
386 int new_uniform_count
= 0;
388 /* Now, figure out a packing of the live uniform vectors into our
391 for (int src
= 0; src
< uniforms
; src
++) {
392 int size
= this->uniform_vector_size
[src
];
394 if (!uniform_used
[src
]) {
395 this->uniform_vector_size
[src
] = 0;
400 /* Find the lowest place we can slot this uniform in. */
401 for (dst
= 0; dst
< src
; dst
++) {
402 if (this->uniform_vector_size
[dst
] + size
<= 4)
411 new_chan
[src
] = this->uniform_vector_size
[dst
];
413 /* Move the references to the data */
414 for (int j
= 0; j
< size
; j
++) {
415 prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
416 prog_data
->param
[src
* 4 + j
];
419 this->uniform_vector_size
[dst
] += size
;
420 this->uniform_vector_size
[src
] = 0;
423 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
426 this->uniforms
= new_uniform_count
;
428 /* Now, update the instructions for our repacked uniforms. */
429 foreach_list(node
, &this->instructions
) {
430 vec4_instruction
*inst
= (vec4_instruction
*)node
;
432 for (int i
= 0 ; i
< 3; i
++) {
433 int src
= inst
->src
[i
].reg
;
435 if (inst
->src
[i
].file
!= UNIFORM
)
438 inst
->src
[i
].reg
= new_loc
[src
];
440 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
441 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
442 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
443 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
444 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
450 src_reg::is_zero() const
455 if (type
== BRW_REGISTER_TYPE_F
) {
463 src_reg::is_one() const
468 if (type
== BRW_REGISTER_TYPE_F
) {
476 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
478 * While GLSL IR also performs this optimization, we end up with it in
479 * our instruction stream for a couple of reasons. One is that we
480 * sometimes generate silly instructions, for example in array access
481 * where we'll generate "ADD offset, index, base" even if base is 0.
482 * The other is that GLSL IR's constant propagation doesn't track the
483 * components of aggregates, so some VS patterns (initialize matrix to
484 * 0, accumulate in vertex blending factors) end up breaking down to
485 * instructions involving 0.
488 vec4_visitor::opt_algebraic()
490 bool progress
= false;
492 foreach_list(node
, &this->instructions
) {
493 vec4_instruction
*inst
= (vec4_instruction
*)node
;
495 switch (inst
->opcode
) {
497 if (inst
->src
[1].is_zero()) {
498 inst
->opcode
= BRW_OPCODE_MOV
;
499 inst
->src
[1] = src_reg();
505 if (inst
->src
[1].is_zero()) {
506 inst
->opcode
= BRW_OPCODE_MOV
;
507 switch (inst
->src
[0].type
) {
508 case BRW_REGISTER_TYPE_F
:
509 inst
->src
[0] = src_reg(0.0f
);
511 case BRW_REGISTER_TYPE_D
:
512 inst
->src
[0] = src_reg(0);
514 case BRW_REGISTER_TYPE_UD
:
515 inst
->src
[0] = src_reg(0u);
518 assert(!"not reached");
519 inst
->src
[0] = src_reg(0.0f
);
522 inst
->src
[1] = src_reg();
524 } else if (inst
->src
[1].is_one()) {
525 inst
->opcode
= BRW_OPCODE_MOV
;
526 inst
->src
[1] = src_reg();
536 this->live_intervals_valid
= false;
542 * Only a limited number of hardware registers may be used for push
543 * constants, so this turns access to the overflowed constants into
547 vec4_visitor::move_push_constants_to_pull_constants()
549 int pull_constant_loc
[this->uniforms
];
551 /* Only allow 32 registers (256 uniform components) as push constants,
552 * which is the limit on gen6.
554 int max_uniform_components
= 32 * 8;
555 if (this->uniforms
* 4 <= max_uniform_components
)
558 /* Make some sort of choice as to which uniforms get sent to pull
559 * constants. We could potentially do something clever here like
560 * look for the most infrequently used uniform vec4s, but leave
563 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
564 pull_constant_loc
[i
/ 4] = -1;
566 if (i
>= max_uniform_components
) {
567 const float **values
= &prog_data
->param
[i
];
569 /* Try to find an existing copy of this uniform in the pull
570 * constants if it was part of an array access already.
572 for (unsigned int j
= 0; j
< prog_data
->nr_pull_params
; j
+= 4) {
575 for (matches
= 0; matches
< 4; matches
++) {
576 if (prog_data
->pull_param
[j
+ matches
] != values
[matches
])
581 pull_constant_loc
[i
/ 4] = j
/ 4;
586 if (pull_constant_loc
[i
/ 4] == -1) {
587 assert(prog_data
->nr_pull_params
% 4 == 0);
588 pull_constant_loc
[i
/ 4] = prog_data
->nr_pull_params
/ 4;
590 for (int j
= 0; j
< 4; j
++) {
591 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
597 /* Now actually rewrite usage of the things we've moved to pull
600 foreach_list_safe(node
, &this->instructions
) {
601 vec4_instruction
*inst
= (vec4_instruction
*)node
;
603 for (int i
= 0 ; i
< 3; i
++) {
604 if (inst
->src
[i
].file
!= UNIFORM
||
605 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
608 int uniform
= inst
->src
[i
].reg
;
610 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
612 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
613 pull_constant_loc
[uniform
]);
615 inst
->src
[i
].file
= temp
.file
;
616 inst
->src
[i
].reg
= temp
.reg
;
617 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
618 inst
->src
[i
].reladdr
= NULL
;
622 /* Repack push constants to remove the now-unused ones. */
623 pack_uniform_registers();
627 * Sets the dependency control fields on instructions after register
628 * allocation and before the generator is run.
630 * When you have a sequence of instructions like:
632 * DP4 temp.x vertex uniform[0]
633 * DP4 temp.y vertex uniform[0]
634 * DP4 temp.z vertex uniform[0]
635 * DP4 temp.w vertex uniform[0]
637 * The hardware doesn't know that it can actually run the later instructions
638 * while the previous ones are in flight, producing stalls. However, we have
639 * manual fields we can set in the instructions that let it do so.
642 vec4_visitor::opt_set_dependency_control()
644 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
645 uint8_t grf_channels_written
[BRW_MAX_GRF
];
646 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
647 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
651 assert(prog_data
->total_grf
||
652 !"Must be called after register allocation");
654 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
655 bblock_t
*bblock
= cfg
.blocks
[i
];
656 vec4_instruction
*inst
;
658 memset(last_grf_write
, 0, sizeof(last_grf_write
));
659 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
661 for (inst
= (vec4_instruction
*)bblock
->start
;
662 inst
!= (vec4_instruction
*)bblock
->end
->next
;
663 inst
= (vec4_instruction
*)inst
->next
) {
664 /* If we read from a register that we were doing dependency control
665 * on, don't do dependency control across the read.
667 for (int i
= 0; i
< 3; i
++) {
668 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
669 if (inst
->src
[i
].file
== GRF
) {
670 last_grf_write
[reg
] = NULL
;
671 } else if (inst
->src
[i
].file
== HW_REG
) {
672 memset(last_grf_write
, 0, sizeof(last_grf_write
));
675 assert(inst
->src
[i
].file
!= MRF
);
678 /* In the presence of send messages, totally interrupt dependency
679 * control. They're long enough that the chance of dependency
680 * control around them just doesn't matter.
683 memset(last_grf_write
, 0, sizeof(last_grf_write
));
684 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
688 /* It looks like setting dependency control on a predicated
689 * instruction hangs the GPU.
691 if (inst
->predicate
) {
692 memset(last_grf_write
, 0, sizeof(last_grf_write
));
693 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
697 /* Now, see if we can do dependency control for this instruction
698 * against a previous one writing to its destination.
700 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
701 if (inst
->dst
.file
== GRF
) {
702 if (last_grf_write
[reg
] &&
703 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
704 last_grf_write
[reg
]->no_dd_clear
= true;
705 inst
->no_dd_check
= true;
707 grf_channels_written
[reg
] = 0;
710 last_grf_write
[reg
] = inst
;
711 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
712 } else if (inst
->dst
.file
== MRF
) {
713 if (last_mrf_write
[reg
] &&
714 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
715 last_mrf_write
[reg
]->no_dd_clear
= true;
716 inst
->no_dd_check
= true;
718 mrf_channels_written
[reg
] = 0;
721 last_mrf_write
[reg
] = inst
;
722 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
723 } else if (inst
->dst
.reg
== HW_REG
) {
724 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
725 memset(last_grf_write
, 0, sizeof(last_grf_write
));
726 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
727 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
734 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
738 /* If this instruction sets anything not referenced by swizzle, then we'd
739 * totally break it when we reswizzle.
741 if (dst
.writemask
& ~swizzle_mask
)
750 /* Check if there happens to be no reswizzling required. */
751 for (int c
= 0; c
< 4; c
++) {
752 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
753 /* Skip components of the swizzle not used by the dst. */
754 if (!(dst_writemask
& (1 << c
)))
757 /* We don't do the reswizzling yet, so just sanity check that we
768 * For any channels in the swizzle's source that were populated by this
769 * instruction, rewrite the instruction to put the appropriate result directly
772 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
775 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
777 int new_writemask
= 0;
783 for (int c
= 0; c
< 4; c
++) {
784 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
785 /* Skip components of the swizzle not used by the dst. */
786 if (!(dst_writemask
& (1 << c
)))
788 /* If we were populating this component, then populate the
789 * corresponding channel of the new dst.
791 if (dst
.writemask
& bit
)
792 new_writemask
|= (1 << c
);
794 dst
.writemask
= new_writemask
;
797 for (int c
= 0; c
< 4; c
++) {
798 /* Skip components of the swizzle not used by the dst. */
799 if (!(dst_writemask
& (1 << c
)))
802 /* We don't do the reswizzling yet, so just sanity check that we
805 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
812 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
813 * just written and then MOVed into another reg and making the original write
814 * of the GRF write directly to the final destination instead.
817 vec4_visitor::opt_register_coalesce()
819 bool progress
= false;
822 calculate_live_intervals();
824 foreach_list_safe(node
, &this->instructions
) {
825 vec4_instruction
*inst
= (vec4_instruction
*)node
;
830 if (inst
->opcode
!= BRW_OPCODE_MOV
||
831 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
833 inst
->src
[0].file
!= GRF
||
834 inst
->dst
.type
!= inst
->src
[0].type
||
835 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
838 bool to_mrf
= (inst
->dst
.file
== MRF
);
840 /* Can't coalesce this GRF if someone else was going to
843 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
846 /* We need to check interference with the final destination between this
847 * instruction and the earliest instruction involved in writing the GRF
848 * we're eliminating. To do that, keep track of which of our source
849 * channels we've seen initialized.
851 bool chans_needed
[4] = {false, false, false, false};
852 int chans_remaining
= 0;
853 int swizzle_mask
= 0;
854 for (int i
= 0; i
< 4; i
++) {
855 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
857 if (!(inst
->dst
.writemask
& (1 << i
)))
860 swizzle_mask
|= (1 << chan
);
862 if (!chans_needed
[chan
]) {
863 chans_needed
[chan
] = true;
868 /* Now walk up the instruction stream trying to see if we can rewrite
869 * everything writing to the temporary to write into the destination
872 vec4_instruction
*scan_inst
;
873 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
874 scan_inst
->prev
!= NULL
;
875 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
876 if (scan_inst
->dst
.file
== GRF
&&
877 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
878 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
879 /* Found something writing to the reg we want to coalesce away. */
881 /* SEND instructions can't have MRF as a destination. */
886 /* gen6 math instructions must have the destination be
887 * GRF, so no compute-to-MRF for them.
889 if (scan_inst
->is_math()) {
895 /* If we can't handle the swizzle, bail. */
896 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
897 inst
->src
[0].swizzle
,
902 /* Mark which channels we found unconditional writes for. */
903 if (!scan_inst
->predicate
) {
904 for (int i
= 0; i
< 4; i
++) {
905 if (scan_inst
->dst
.writemask
& (1 << i
) &&
907 chans_needed
[i
] = false;
913 if (chans_remaining
== 0)
917 /* We don't handle flow control here. Most computation of values
918 * that could be coalesced happens just before their use.
920 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
921 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
922 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
923 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
927 /* You can't read from an MRF, so if someone else reads our MRF's
928 * source GRF that we wanted to rewrite, that stops us. If it's a
929 * GRF we're trying to coalesce to, we don't actually handle
930 * rewriting sources so bail in that case as well.
932 bool interfered
= false;
933 for (int i
= 0; i
< 3; i
++) {
934 if (scan_inst
->src
[i
].file
== GRF
&&
935 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
936 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
943 /* If somebody else writes our destination here, we can't coalesce
946 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
947 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
951 /* Check for reads of the register we're trying to coalesce into. We
952 * can't go rewriting instructions above that to put some other value
953 * in the register instead.
955 if (to_mrf
&& scan_inst
->mlen
> 0) {
956 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
957 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
961 for (int i
= 0; i
< 3; i
++) {
962 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
963 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
964 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
973 if (chans_remaining
== 0) {
974 /* If we've made it here, we have an MOV we want to coalesce out, and
975 * a scan_inst pointing to the earliest instruction involved in
976 * computing the value. Now go rewrite the instruction stream
980 while (scan_inst
!= inst
) {
981 if (scan_inst
->dst
.file
== GRF
&&
982 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
983 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
984 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
985 inst
->src
[0].swizzle
);
986 scan_inst
->dst
.file
= inst
->dst
.file
;
987 scan_inst
->dst
.reg
= inst
->dst
.reg
;
988 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
989 scan_inst
->saturate
|= inst
->saturate
;
991 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
999 live_intervals_valid
= false;
1005 * Splits virtual GRFs requesting more than one contiguous physical register.
1007 * We initially create large virtual GRFs for temporary structures, arrays,
1008 * and matrices, so that the dereference visitor functions can add reg_offsets
1009 * to work their way down to the actual member being accessed. But when it
1010 * comes to optimization, we'd like to treat each register as individual
1011 * storage if possible.
1013 * So far, the only thing that might prevent splitting is a send message from
1017 vec4_visitor::split_virtual_grfs()
1019 int num_vars
= this->virtual_grf_count
;
1020 int new_virtual_grf
[num_vars
];
1021 bool split_grf
[num_vars
];
1023 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1025 /* Try to split anything > 0 sized. */
1026 for (int i
= 0; i
< num_vars
; i
++) {
1027 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1030 /* Check that the instructions are compatible with the registers we're trying
1033 foreach_list(node
, &this->instructions
) {
1034 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1036 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1039 if (inst
->is_send_from_grf()) {
1040 for (int i
= 0; i
< 3; i
++) {
1041 if (inst
->src
[i
].file
== GRF
) {
1042 split_grf
[inst
->src
[i
].reg
] = false;
1048 /* Allocate new space for split regs. Note that the virtual
1049 * numbers will be contiguous.
1051 for (int i
= 0; i
< num_vars
; i
++) {
1055 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1056 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1057 int reg
= virtual_grf_alloc(1);
1058 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1061 this->virtual_grf_sizes
[i
] = 1;
1064 foreach_list(node
, &this->instructions
) {
1065 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1067 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1068 inst
->dst
.reg_offset
!= 0) {
1069 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1070 inst
->dst
.reg_offset
- 1);
1071 inst
->dst
.reg_offset
= 0;
1073 for (int i
= 0; i
< 3; i
++) {
1074 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1075 inst
->src
[i
].reg_offset
!= 0) {
1076 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1077 inst
->src
[i
].reg_offset
- 1);
1078 inst
->src
[i
].reg_offset
= 0;
1082 this->live_intervals_valid
= false;
1086 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1088 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1090 printf("%s ", brw_instruction_name(inst
->opcode
));
1092 switch (inst
->dst
.file
) {
1094 printf("vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1097 printf("m%d", inst
->dst
.reg
);
1106 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1108 if (inst
->dst
.writemask
& 1)
1110 if (inst
->dst
.writemask
& 2)
1112 if (inst
->dst
.writemask
& 4)
1114 if (inst
->dst
.writemask
& 8)
1119 for (int i
= 0; i
< 3; i
++) {
1120 switch (inst
->src
[i
].file
) {
1122 printf("vgrf%d", inst
->src
[i
].reg
);
1125 printf("attr%d", inst
->src
[i
].reg
);
1128 printf("u%d", inst
->src
[i
].reg
);
1131 switch (inst
->src
[i
].type
) {
1132 case BRW_REGISTER_TYPE_F
:
1133 printf("%fF", inst
->src
[i
].imm
.f
);
1135 case BRW_REGISTER_TYPE_D
:
1136 printf("%dD", inst
->src
[i
].imm
.i
);
1138 case BRW_REGISTER_TYPE_UD
:
1139 printf("%uU", inst
->src
[i
].imm
.u
);
1154 if (inst
->src
[i
].reg_offset
)
1155 printf(".%d", inst
->src
[i
].reg_offset
);
1157 static const char *chans
[4] = {"x", "y", "z", "w"};
1159 for (int c
= 0; c
< 4; c
++) {
1160 printf("%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1171 * Replace each register of type ATTR in this->instructions with a reference
1172 * to a fixed HW register.
1175 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
)
1177 foreach_list(node
, &this->instructions
) {
1178 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1180 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1181 if (inst
->dst
.file
== ATTR
) {
1182 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1184 /* All attributes used in the shader need to have been assigned a
1185 * hardware register by the caller
1189 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1190 reg
.type
= inst
->dst
.type
;
1191 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1193 inst
->dst
.file
= HW_REG
;
1194 inst
->dst
.fixed_hw_reg
= reg
;
1197 for (int i
= 0; i
< 3; i
++) {
1198 if (inst
->src
[i
].file
!= ATTR
)
1201 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1203 /* All attributes used in the shader need to have been assigned a
1204 * hardware register by the caller
1208 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1209 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1210 reg
.type
= inst
->src
[i
].type
;
1211 if (inst
->src
[i
].abs
)
1213 if (inst
->src
[i
].negate
)
1216 inst
->src
[i
].file
= HW_REG
;
1217 inst
->src
[i
].fixed_hw_reg
= reg
;
1223 vec4_vs_visitor::setup_attributes(int payload_reg
)
1226 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1227 memset(attribute_map
, 0, sizeof(attribute_map
));
1230 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1231 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1232 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1237 /* VertexID is stored by the VF as the last vertex element, but we
1238 * don't represent it with a flag in inputs_read, so we call it
1241 if (vs_prog_data
->uses_vertexid
) {
1242 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1246 lower_attributes_to_hw_regs(attribute_map
);
1248 /* The BSpec says we always have to read at least one thing from
1249 * the VF, and it appears that the hardware wedges otherwise.
1251 if (nr_attributes
== 0)
1254 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1256 unsigned vue_entries
=
1257 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1260 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1262 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1264 return payload_reg
+ nr_attributes
;
1268 vec4_visitor::setup_uniforms(int reg
)
1270 prog_data
->dispatch_grf_start_reg
= reg
;
1272 /* The pre-gen6 VS requires that some push constants get loaded no
1273 * matter what, or the GPU would hang.
1275 if (brw
->gen
< 6 && this->uniforms
== 0) {
1276 this->uniform_vector_size
[this->uniforms
] = 1;
1278 prog_data
->param
= reralloc(NULL
, prog_data
->param
, const float *, 4);
1279 for (unsigned int i
= 0; i
< 4; i
++) {
1280 unsigned int slot
= this->uniforms
* 4 + i
;
1281 static float zero
= 0.0;
1282 prog_data
->param
[slot
] = &zero
;
1288 reg
+= ALIGN(uniforms
, 2) / 2;
1291 prog_data
->nr_params
= this->uniforms
* 4;
1293 prog_data
->curb_read_length
= reg
- prog_data
->dispatch_grf_start_reg
;
1299 vec4_vs_visitor::setup_payload(void)
1303 /* The payload always contains important data in g0, which contains
1304 * the URB handles that are passed on to the URB write at the end
1305 * of the thread. So, we always start push constants at g1.
1309 reg
= setup_uniforms(reg
);
1311 reg
= setup_attributes(reg
);
1313 this->first_non_payload_grf
= reg
;
1317 vec4_visitor::get_timestamp()
1319 assert(brw
->gen
>= 7);
1321 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1324 BRW_REGISTER_TYPE_UD
,
1325 BRW_VERTICAL_STRIDE_0
,
1327 BRW_HORIZONTAL_STRIDE_4
,
1331 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1333 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1334 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1335 * even if it's not enabled in the dispatch.
1337 mov
->force_writemask_all
= true;
1339 return src_reg(dst
);
1343 vec4_visitor::emit_shader_time_begin()
1345 current_annotation
= "shader time start";
1346 shader_start_time
= get_timestamp();
1350 vec4_visitor::emit_shader_time_end()
1352 current_annotation
= "shader time end";
1353 src_reg shader_end_time
= get_timestamp();
1356 /* Check that there weren't any timestamp reset events (assuming these
1357 * were the only two timestamp reads that happened).
1359 src_reg reset_end
= shader_end_time
;
1360 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1361 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1362 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1364 emit(IF(BRW_PREDICATE_NORMAL
));
1366 /* Take the current timestamp and get the delta. */
1367 shader_start_time
.negate
= true;
1368 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1369 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1371 /* If there were no instructions between the two timestamp gets, the diff
1372 * is 2 cycles. Remove that overhead, so I can forget about that when
1373 * trying to determine the time taken for single instructions.
1375 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1377 emit_shader_time_write(ST_VS
, src_reg(diff
));
1378 emit_shader_time_write(ST_VS_WRITTEN
, src_reg(1u));
1379 emit(BRW_OPCODE_ELSE
);
1380 emit_shader_time_write(ST_VS_RESET
, src_reg(1u));
1381 emit(BRW_OPCODE_ENDIF
);
1385 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1388 int shader_time_index
=
1389 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1392 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1394 dst_reg offset
= dst
;
1398 offset
.type
= BRW_REGISTER_TYPE_UD
;
1399 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1401 time
.type
= BRW_REGISTER_TYPE_UD
;
1402 emit(MOV(time
, src_reg(value
)));
1404 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1410 sanity_param_count
= prog
->Parameters
->NumParameters
;
1412 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1413 emit_shader_time_begin();
1417 /* Generate VS IR for main(). (the visitor only descends into
1418 * functions called "main").
1421 visit_instructions(shader
->ir
);
1423 emit_program_code();
1427 if (key
->userclip_active
&& !key
->uses_clip_distance
)
1428 setup_uniform_clipplane_values();
1432 /* Before any optimization, push array accesses out to scratch
1433 * space where we need them to be. This pass may allocate new
1434 * virtual GRFs, so we want to do it early. It also makes sure
1435 * that we have reladdr computations available for CSE, since we'll
1436 * often do repeated subexpressions for those.
1439 move_grf_array_access_to_scratch();
1440 move_uniform_array_access_to_pull_constants();
1442 /* The ARB_vertex_program frontend emits pull constant loads directly
1443 * rather than using reladdr, so we don't need to walk through all the
1444 * instructions looking for things to move. There isn't anything.
1446 * We do still need to split things to vec4 size.
1448 split_uniform_registers();
1450 pack_uniform_registers();
1451 move_push_constants_to_pull_constants();
1452 split_virtual_grfs();
1457 progress
= dead_code_eliminate() || progress
;
1458 progress
= opt_copy_propagation() || progress
;
1459 progress
= opt_algebraic() || progress
;
1460 progress
= opt_register_coalesce() || progress
;
1470 /* Debug of register spilling: Go spill everything. */
1471 const int grf_count
= virtual_grf_count
;
1472 float spill_costs
[virtual_grf_count
];
1473 bool no_spill
[virtual_grf_count
];
1474 evaluate_spill_costs(spill_costs
, no_spill
);
1475 for (int i
= 0; i
< grf_count
; i
++) {
1482 while (!reg_allocate()) {
1487 opt_schedule_instructions();
1489 opt_set_dependency_control();
1491 /* If any state parameters were appended, then ParameterValues could have
1492 * been realloced, in which case the driver uniform storage set up by
1493 * _mesa_associate_uniform_storage() would point to freed memory. Make
1494 * sure that didn't happen.
1496 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1501 } /* namespace brw */
1506 * Compile a vertex shader.
1508 * Returns the final assembly and the program's size.
1511 brw_vs_emit(struct brw_context
*brw
,
1512 struct gl_shader_program
*prog
,
1513 struct brw_vs_compile
*c
,
1514 struct brw_vs_prog_data
*prog_data
,
1516 unsigned *final_assembly_size
)
1518 bool start_busy
= false;
1519 float start_time
= 0;
1521 if (unlikely(brw
->perf_debug
)) {
1522 start_busy
= (brw
->batch
.last_bo
&&
1523 drm_intel_bo_busy(brw
->batch
.last_bo
));
1524 start_time
= get_time();
1527 struct brw_shader
*shader
= NULL
;
1529 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1531 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1533 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
1534 _mesa_print_ir(shader
->ir
, NULL
);
1537 printf("ARB_vertex_program %d for native vertex shader\n",
1538 c
->vp
->program
.Base
.Id
);
1539 _mesa_print_program(&c
->vp
->program
.Base
);
1543 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, shader
, mem_ctx
);
1546 prog
->LinkStatus
= false;
1547 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1550 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1556 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
, mem_ctx
,
1557 INTEL_DEBUG
& DEBUG_VS
);
1558 const unsigned *generated
=g
.generate_assembly(&v
.instructions
,
1559 final_assembly_size
);
1561 if (unlikely(brw
->perf_debug
) && shader
) {
1562 if (shader
->compiled_once
) {
1563 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1565 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1566 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1567 (get_time() - start_time
) * 1000);
1569 shader
->compiled_once
= true;
1577 brw_vec4_prog_data_compare(const struct brw_vec4_prog_data
*a
,
1578 const struct brw_vec4_prog_data
*b
)
1580 /* Compare all the struct up to the pointers. */
1581 if (memcmp(a
, b
, offsetof(struct brw_vec4_prog_data
, param
)))
1584 if (memcmp(a
->param
, b
->param
, a
->nr_params
* sizeof(void *)))
1587 if (memcmp(a
->pull_param
, b
->pull_param
, a
->nr_pull_params
* sizeof(void *)))
1595 brw_vec4_prog_data_free(const struct brw_vec4_prog_data
*prog_data
)
1597 ralloc_free((void *)prog_data
->param
);
1598 ralloc_free((void *)prog_data
->pull_param
);