2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_live_variables.h"
30 #include "brw_dead_control_flow.h"
33 #include "main/macros.h"
34 #include "main/shaderobj.h"
35 #include "program/prog_print.h"
36 #include "program/prog_parameter.h"
39 #define MAX_INSTRUCTION (1 << 30)
48 memset(this, 0, sizeof(*this));
50 this->file
= BAD_FILE
;
53 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
59 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
60 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
62 this->swizzle
= BRW_SWIZZLE_XYZW
;
65 /** Generic unset register constructor. */
71 src_reg::src_reg(float f
)
76 this->type
= BRW_REGISTER_TYPE_F
;
77 this->fixed_hw_reg
.dw1
.f
= f
;
80 src_reg::src_reg(uint32_t u
)
85 this->type
= BRW_REGISTER_TYPE_UD
;
86 this->fixed_hw_reg
.dw1
.ud
= u
;
89 src_reg::src_reg(int32_t i
)
94 this->type
= BRW_REGISTER_TYPE_D
;
95 this->fixed_hw_reg
.dw1
.d
= i
;
98 src_reg::src_reg(uint8_t vf
[4])
103 this->type
= BRW_REGISTER_TYPE_VF
;
104 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
107 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
112 this->type
= BRW_REGISTER_TYPE_VF
;
113 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
119 src_reg::src_reg(struct brw_reg reg
)
124 this->fixed_hw_reg
= reg
;
125 this->type
= reg
.type
;
128 src_reg::src_reg(const dst_reg
®
)
132 this->file
= reg
.file
;
134 this->reg_offset
= reg
.reg_offset
;
135 this->type
= reg
.type
;
136 this->reladdr
= reg
.reladdr
;
137 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
138 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
144 memset(this, 0, sizeof(*this));
145 this->file
= BAD_FILE
;
146 this->writemask
= WRITEMASK_XYZW
;
154 dst_reg::dst_reg(register_file file
, int reg
)
162 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
169 this->type
= brw_type_for_base_type(type
);
170 this->writemask
= writemask
;
173 dst_reg::dst_reg(struct brw_reg reg
)
178 this->fixed_hw_reg
= reg
;
179 this->type
= reg
.type
;
182 dst_reg::dst_reg(const src_reg
®
)
186 this->file
= reg
.file
;
188 this->reg_offset
= reg
.reg_offset
;
189 this->type
= reg
.type
;
190 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
191 this->reladdr
= reg
.reladdr
;
192 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
196 dst_reg::equals(const dst_reg
&r
) const
198 return (file
== r
.file
&&
200 reg_offset
== r
.reg_offset
&&
202 negate
== r
.negate
&&
204 writemask
== r
.writemask
&&
205 (reladdr
== r
.reladdr
||
206 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))) &&
207 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
208 sizeof(fixed_hw_reg
)) == 0);
212 vec4_instruction::is_send_from_grf()
215 case SHADER_OPCODE_SHADER_TIME_ADD
:
216 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
217 case SHADER_OPCODE_UNTYPED_ATOMIC
:
218 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
219 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
227 vec4_instruction::regs_read(unsigned arg
) const
229 if (src
[arg
].file
== BAD_FILE
)
233 case SHADER_OPCODE_SHADER_TIME_ADD
:
234 case SHADER_OPCODE_UNTYPED_ATOMIC
:
235 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
236 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
237 return arg
== 0 ? mlen
: 1;
239 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
240 return arg
== 1 ? mlen
: 1;
248 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
250 if (devinfo
->gen
== 6 && is_math())
253 if (is_send_from_grf())
256 if (!backend_instruction::can_do_source_mods())
263 * Returns how many MRFs an opcode will write over.
265 * Note that this is not the 0 or 1 implied writes in an actual gen
266 * instruction -- the generate_* functions generate additional MOVs
270 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
272 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
275 switch (inst
->opcode
) {
276 case SHADER_OPCODE_RCP
:
277 case SHADER_OPCODE_RSQ
:
278 case SHADER_OPCODE_SQRT
:
279 case SHADER_OPCODE_EXP2
:
280 case SHADER_OPCODE_LOG2
:
281 case SHADER_OPCODE_SIN
:
282 case SHADER_OPCODE_COS
:
284 case SHADER_OPCODE_INT_QUOTIENT
:
285 case SHADER_OPCODE_INT_REMAINDER
:
286 case SHADER_OPCODE_POW
:
288 case VS_OPCODE_URB_WRITE
:
290 case VS_OPCODE_PULL_CONSTANT_LOAD
:
292 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
294 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
296 case GS_OPCODE_URB_WRITE
:
297 case GS_OPCODE_URB_WRITE_ALLOCATE
:
298 case GS_OPCODE_THREAD_END
:
300 case GS_OPCODE_FF_SYNC
:
302 case SHADER_OPCODE_SHADER_TIME_ADD
:
304 case SHADER_OPCODE_TEX
:
305 case SHADER_OPCODE_TXL
:
306 case SHADER_OPCODE_TXD
:
307 case SHADER_OPCODE_TXF
:
308 case SHADER_OPCODE_TXF_CMS
:
309 case SHADER_OPCODE_TXF_MCS
:
310 case SHADER_OPCODE_TXS
:
311 case SHADER_OPCODE_TG4
:
312 case SHADER_OPCODE_TG4_OFFSET
:
313 return inst
->header_present
? 1 : 0;
315 unreachable("not reached");
320 src_reg::equals(const src_reg
&r
) const
322 return (file
== r
.file
&&
324 reg_offset
== r
.reg_offset
&&
326 negate
== r
.negate
&&
328 swizzle
== r
.swizzle
&&
329 !reladdr
&& !r
.reladdr
&&
330 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
331 sizeof(fixed_hw_reg
)) == 0);
335 vec4_visitor::opt_vector_float()
337 bool progress
= false;
339 int last_reg
= -1, last_reg_offset
= -1;
340 enum register_file last_reg_file
= BAD_FILE
;
342 int remaining_channels
= 0;
345 vec4_instruction
*imm_inst
[4];
347 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
348 if (last_reg
!= inst
->dst
.reg
||
349 last_reg_offset
!= inst
->dst
.reg_offset
||
350 last_reg_file
!= inst
->dst
.file
) {
351 last_reg
= inst
->dst
.reg
;
352 last_reg_offset
= inst
->dst
.reg_offset
;
353 last_reg_file
= inst
->dst
.file
;
354 remaining_channels
= WRITEMASK_XYZW
;
359 if (inst
->opcode
!= BRW_OPCODE_MOV
||
360 inst
->dst
.writemask
== WRITEMASK_XYZW
||
361 inst
->src
[0].file
!= IMM
)
364 int vf
= brw_float_to_vf(inst
->src
[0].fixed_hw_reg
.dw1
.f
);
368 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
370 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
372 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
374 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
377 imm_inst
[inst_count
++] = inst
;
379 remaining_channels
&= ~inst
->dst
.writemask
;
380 if (remaining_channels
== 0) {
381 vec4_instruction
*mov
= MOV(inst
->dst
, imm
);
382 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
383 mov
->dst
.writemask
= WRITEMASK_XYZW
;
384 inst
->insert_after(block
, mov
);
387 for (int i
= 0; i
< inst_count
; i
++) {
388 imm_inst
[i
]->remove(block
);
395 invalidate_live_intervals();
400 /* Replaces unused channels of a swizzle with channels that are used.
402 * For instance, this pass transforms
404 * mov vgrf4.yz, vgrf5.wxzy
408 * mov vgrf4.yz, vgrf5.xxzx
410 * This eliminates false uses of some channels, letting dead code elimination
411 * remove the instructions that wrote them.
414 vec4_visitor::opt_reduce_swizzle()
416 bool progress
= false;
418 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
419 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
||
420 inst
->is_send_from_grf())
425 /* Determine which channels of the sources are read. */
426 switch (inst
->opcode
) {
427 case VEC4_OPCODE_PACK_BYTES
:
429 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
430 * but all four of src1.
432 swizzle
= brw_swizzle_for_size(4);
435 swizzle
= brw_swizzle_for_size(3);
438 swizzle
= brw_swizzle_for_size(2);
441 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
445 /* Update sources' swizzles. */
446 for (int i
= 0; i
< 3; i
++) {
447 if (inst
->src
[i
].file
!= GRF
&&
448 inst
->src
[i
].file
!= ATTR
&&
449 inst
->src
[i
].file
!= UNIFORM
)
452 const unsigned new_swizzle
=
453 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
454 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
455 inst
->src
[i
].swizzle
= new_swizzle
;
462 invalidate_live_intervals();
468 vec4_visitor::split_uniform_registers()
470 /* Prior to this, uniforms have been in an array sized according to
471 * the number of vector uniforms present, sparsely filled (so an
472 * aggregate results in reg indices being skipped over). Now we're
473 * going to cut those aggregates up so each .reg index is one
474 * vector. The goal is to make elimination of unused uniform
475 * components easier later.
477 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
478 for (int i
= 0 ; i
< 3; i
++) {
479 if (inst
->src
[i
].file
!= UNIFORM
)
482 assert(!inst
->src
[i
].reladdr
);
484 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
485 inst
->src
[i
].reg_offset
= 0;
489 /* Update that everything is now vector-sized. */
490 for (int i
= 0; i
< this->uniforms
; i
++) {
491 this->uniform_size
[i
] = 1;
496 vec4_visitor::pack_uniform_registers()
498 bool uniform_used
[this->uniforms
];
499 int new_loc
[this->uniforms
];
500 int new_chan
[this->uniforms
];
502 memset(uniform_used
, 0, sizeof(uniform_used
));
503 memset(new_loc
, 0, sizeof(new_loc
));
504 memset(new_chan
, 0, sizeof(new_chan
));
506 /* Find which uniform vectors are actually used by the program. We
507 * expect unused vector elements when we've moved array access out
508 * to pull constants, and from some GLSL code generators like wine.
510 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
511 for (int i
= 0 ; i
< 3; i
++) {
512 if (inst
->src
[i
].file
!= UNIFORM
)
515 uniform_used
[inst
->src
[i
].reg
] = true;
519 int new_uniform_count
= 0;
521 /* Now, figure out a packing of the live uniform vectors into our
524 for (int src
= 0; src
< uniforms
; src
++) {
525 assert(src
< uniform_array_size
);
526 int size
= this->uniform_vector_size
[src
];
528 if (!uniform_used
[src
]) {
529 this->uniform_vector_size
[src
] = 0;
534 /* Find the lowest place we can slot this uniform in. */
535 for (dst
= 0; dst
< src
; dst
++) {
536 if (this->uniform_vector_size
[dst
] + size
<= 4)
545 new_chan
[src
] = this->uniform_vector_size
[dst
];
547 /* Move the references to the data */
548 for (int j
= 0; j
< size
; j
++) {
549 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
550 stage_prog_data
->param
[src
* 4 + j
];
553 this->uniform_vector_size
[dst
] += size
;
554 this->uniform_vector_size
[src
] = 0;
557 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
560 this->uniforms
= new_uniform_count
;
562 /* Now, update the instructions for our repacked uniforms. */
563 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
564 for (int i
= 0 ; i
< 3; i
++) {
565 int src
= inst
->src
[i
].reg
;
567 if (inst
->src
[i
].file
!= UNIFORM
)
570 inst
->src
[i
].reg
= new_loc
[src
];
571 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
572 new_chan
[src
], new_chan
[src
]);
578 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
580 * While GLSL IR also performs this optimization, we end up with it in
581 * our instruction stream for a couple of reasons. One is that we
582 * sometimes generate silly instructions, for example in array access
583 * where we'll generate "ADD offset, index, base" even if base is 0.
584 * The other is that GLSL IR's constant propagation doesn't track the
585 * components of aggregates, so some VS patterns (initialize matrix to
586 * 0, accumulate in vertex blending factors) end up breaking down to
587 * instructions involving 0.
590 vec4_visitor::opt_algebraic()
592 bool progress
= false;
594 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
595 switch (inst
->opcode
) {
597 if (inst
->src
[0].file
!= IMM
)
600 if (inst
->saturate
) {
601 if (inst
->dst
.type
!= inst
->src
[0].type
)
602 assert(!"unimplemented: saturate mixed types");
604 if (brw_saturate_immediate(inst
->dst
.type
,
605 &inst
->src
[0].fixed_hw_reg
)) {
606 inst
->saturate
= false;
612 case VEC4_OPCODE_UNPACK_UNIFORM
:
613 if (inst
->src
[0].file
!= UNIFORM
) {
614 inst
->opcode
= BRW_OPCODE_MOV
;
620 if (inst
->src
[1].is_zero()) {
621 inst
->opcode
= BRW_OPCODE_MOV
;
622 inst
->src
[1] = src_reg();
628 if (inst
->src
[1].is_zero()) {
629 inst
->opcode
= BRW_OPCODE_MOV
;
630 switch (inst
->src
[0].type
) {
631 case BRW_REGISTER_TYPE_F
:
632 inst
->src
[0] = src_reg(0.0f
);
634 case BRW_REGISTER_TYPE_D
:
635 inst
->src
[0] = src_reg(0);
637 case BRW_REGISTER_TYPE_UD
:
638 inst
->src
[0] = src_reg(0u);
641 unreachable("not reached");
643 inst
->src
[1] = src_reg();
645 } else if (inst
->src
[1].is_one()) {
646 inst
->opcode
= BRW_OPCODE_MOV
;
647 inst
->src
[1] = src_reg();
649 } else if (inst
->src
[1].is_negative_one()) {
650 inst
->opcode
= BRW_OPCODE_MOV
;
651 inst
->src
[0].negate
= !inst
->src
[0].negate
;
652 inst
->src
[1] = src_reg();
657 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
659 inst
->src
[0].negate
&&
660 inst
->src
[1].is_zero()) {
661 inst
->src
[0].abs
= false;
662 inst
->src
[0].negate
= false;
663 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
668 case SHADER_OPCODE_RCP
: {
669 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
670 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
671 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
672 inst
->opcode
= SHADER_OPCODE_RSQ
;
673 inst
->src
[0] = prev
->src
[0];
685 invalidate_live_intervals();
691 * Only a limited number of hardware registers may be used for push
692 * constants, so this turns access to the overflowed constants into
696 vec4_visitor::move_push_constants_to_pull_constants()
698 int pull_constant_loc
[this->uniforms
];
700 /* Only allow 32 registers (256 uniform components) as push constants,
701 * which is the limit on gen6.
703 * If changing this value, note the limitation about total_regs in
706 int max_uniform_components
= 32 * 8;
707 if (this->uniforms
* 4 <= max_uniform_components
)
710 /* Make some sort of choice as to which uniforms get sent to pull
711 * constants. We could potentially do something clever here like
712 * look for the most infrequently used uniform vec4s, but leave
715 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
716 pull_constant_loc
[i
/ 4] = -1;
718 if (i
>= max_uniform_components
) {
719 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
721 /* Try to find an existing copy of this uniform in the pull
722 * constants if it was part of an array access already.
724 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
727 for (matches
= 0; matches
< 4; matches
++) {
728 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
733 pull_constant_loc
[i
/ 4] = j
/ 4;
738 if (pull_constant_loc
[i
/ 4] == -1) {
739 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
740 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
742 for (int j
= 0; j
< 4; j
++) {
743 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
750 /* Now actually rewrite usage of the things we've moved to pull
753 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
754 for (int i
= 0 ; i
< 3; i
++) {
755 if (inst
->src
[i
].file
!= UNIFORM
||
756 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
759 int uniform
= inst
->src
[i
].reg
;
761 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
763 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
764 pull_constant_loc
[uniform
]);
766 inst
->src
[i
].file
= temp
.file
;
767 inst
->src
[i
].reg
= temp
.reg
;
768 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
769 inst
->src
[i
].reladdr
= NULL
;
773 /* Repack push constants to remove the now-unused ones. */
774 pack_uniform_registers();
777 /* Conditions for which we want to avoid setting the dependency control bits */
779 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
781 #define IS_DWORD(reg) \
782 (reg.type == BRW_REGISTER_TYPE_UD || \
783 reg.type == BRW_REGISTER_TYPE_D)
785 /* "When source or destination datatype is 64b or operation is integer DWord
786 * multiply, DepCtrl must not be used."
787 * May apply to future SoCs as well.
789 if (devinfo
->is_cherryview
) {
790 if (inst
->opcode
== BRW_OPCODE_MUL
&&
791 IS_DWORD(inst
->src
[0]) &&
792 IS_DWORD(inst
->src
[1]))
797 if (devinfo
->gen
>= 8) {
798 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
804 * In the presence of send messages, totally interrupt dependency
805 * control. They're long enough that the chance of dependency
806 * control around them just doesn't matter.
809 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
810 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
811 * completes the scoreboard clear must have a non-zero execution mask. This
812 * means, if any kind of predication can change the execution mask or channel
813 * enable of the last instruction, the optimization must be avoided. This is
814 * to avoid instructions being shot down the pipeline when no writes are
818 * Dependency control does not work well over math instructions.
819 * NB: Discovered empirically
821 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
825 * Sets the dependency control fields on instructions after register
826 * allocation and before the generator is run.
828 * When you have a sequence of instructions like:
830 * DP4 temp.x vertex uniform[0]
831 * DP4 temp.y vertex uniform[0]
832 * DP4 temp.z vertex uniform[0]
833 * DP4 temp.w vertex uniform[0]
835 * The hardware doesn't know that it can actually run the later instructions
836 * while the previous ones are in flight, producing stalls. However, we have
837 * manual fields we can set in the instructions that let it do so.
840 vec4_visitor::opt_set_dependency_control()
842 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
843 uint8_t grf_channels_written
[BRW_MAX_GRF
];
844 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
845 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
847 assert(prog_data
->total_grf
||
848 !"Must be called after register allocation");
850 foreach_block (block
, cfg
) {
851 memset(last_grf_write
, 0, sizeof(last_grf_write
));
852 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
854 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
855 /* If we read from a register that we were doing dependency control
856 * on, don't do dependency control across the read.
858 for (int i
= 0; i
< 3; i
++) {
859 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
860 if (inst
->src
[i
].file
== GRF
) {
861 last_grf_write
[reg
] = NULL
;
862 } else if (inst
->src
[i
].file
== HW_REG
) {
863 memset(last_grf_write
, 0, sizeof(last_grf_write
));
866 assert(inst
->src
[i
].file
!= MRF
);
869 if (is_dep_ctrl_unsafe(inst
)) {
870 memset(last_grf_write
, 0, sizeof(last_grf_write
));
871 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
875 /* Now, see if we can do dependency control for this instruction
876 * against a previous one writing to its destination.
878 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
879 if (inst
->dst
.file
== GRF
) {
880 if (last_grf_write
[reg
] &&
881 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
882 last_grf_write
[reg
]->no_dd_clear
= true;
883 inst
->no_dd_check
= true;
885 grf_channels_written
[reg
] = 0;
888 last_grf_write
[reg
] = inst
;
889 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
890 } else if (inst
->dst
.file
== MRF
) {
891 if (last_mrf_write
[reg
] &&
892 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
893 last_mrf_write
[reg
]->no_dd_clear
= true;
894 inst
->no_dd_check
= true;
896 mrf_channels_written
[reg
] = 0;
899 last_mrf_write
[reg
] = inst
;
900 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
901 } else if (inst
->dst
.reg
== HW_REG
) {
902 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
903 memset(last_grf_write
, 0, sizeof(last_grf_write
));
904 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
905 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
912 vec4_instruction::can_reswizzle(int dst_writemask
,
916 /* If this instruction sets anything not referenced by swizzle, then we'd
917 * totally break it when we reswizzle.
919 if (dst
.writemask
& ~swizzle_mask
)
929 * For any channels in the swizzle's source that were populated by this
930 * instruction, rewrite the instruction to put the appropriate result directly
933 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
936 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
938 /* Destination write mask doesn't correspond to source swizzle for the dot
939 * product and pack_bytes instructions.
941 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
942 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
943 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
944 for (int i
= 0; i
< 3; i
++) {
945 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
948 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
952 /* Apply the specified swizzle and writemask to the original mask of
953 * written components.
955 dst
.writemask
= dst_writemask
&
956 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
960 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
961 * just written and then MOVed into another reg and making the original write
962 * of the GRF write directly to the final destination instead.
965 vec4_visitor::opt_register_coalesce()
967 bool progress
= false;
970 calculate_live_intervals();
972 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
976 if (inst
->opcode
!= BRW_OPCODE_MOV
||
977 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
979 inst
->src
[0].file
!= GRF
||
980 inst
->dst
.type
!= inst
->src
[0].type
||
981 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
984 bool to_mrf
= (inst
->dst
.file
== MRF
);
986 /* Can't coalesce this GRF if someone else was going to
989 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
992 /* We need to check interference with the final destination between this
993 * instruction and the earliest instruction involved in writing the GRF
994 * we're eliminating. To do that, keep track of which of our source
995 * channels we've seen initialized.
997 const unsigned chans_needed
=
998 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
999 inst
->dst
.writemask
);
1000 unsigned chans_remaining
= chans_needed
;
1002 /* Now walk up the instruction stream trying to see if we can rewrite
1003 * everything writing to the temporary to write into the destination
1006 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1007 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1009 _scan_inst
= scan_inst
;
1011 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1012 /* Found something writing to the reg we want to coalesce away. */
1014 /* SEND instructions can't have MRF as a destination. */
1015 if (scan_inst
->mlen
)
1018 if (devinfo
->gen
== 6) {
1019 /* gen6 math instructions must have the destination be
1020 * GRF, so no compute-to-MRF for them.
1022 if (scan_inst
->is_math()) {
1028 /* If we can't handle the swizzle, bail. */
1029 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1030 inst
->src
[0].swizzle
,
1035 /* This doesn't handle coalescing of multiple registers. */
1036 if (scan_inst
->regs_written
> 1)
1039 /* Mark which channels we found unconditional writes for. */
1040 if (!scan_inst
->predicate
)
1041 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1043 if (chans_remaining
== 0)
1047 /* You can't read from an MRF, so if someone else reads our MRF's
1048 * source GRF that we wanted to rewrite, that stops us. If it's a
1049 * GRF we're trying to coalesce to, we don't actually handle
1050 * rewriting sources so bail in that case as well.
1052 bool interfered
= false;
1053 for (int i
= 0; i
< 3; i
++) {
1054 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1055 scan_inst
->regs_read(i
)))
1061 /* If somebody else writes our destination here, we can't coalesce
1064 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
))
1067 /* Check for reads of the register we're trying to coalesce into. We
1068 * can't go rewriting instructions above that to put some other value
1069 * in the register instead.
1071 if (to_mrf
&& scan_inst
->mlen
> 0) {
1072 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1073 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1077 for (int i
= 0; i
< 3; i
++) {
1078 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1079 scan_inst
->regs_read(i
)))
1087 if (chans_remaining
== 0) {
1088 /* If we've made it here, we have an MOV we want to coalesce out, and
1089 * a scan_inst pointing to the earliest instruction involved in
1090 * computing the value. Now go rewrite the instruction stream
1093 vec4_instruction
*scan_inst
= _scan_inst
;
1094 while (scan_inst
!= inst
) {
1095 if (scan_inst
->dst
.file
== GRF
&&
1096 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1097 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1098 scan_inst
->reswizzle(inst
->dst
.writemask
,
1099 inst
->src
[0].swizzle
);
1100 scan_inst
->dst
.file
= inst
->dst
.file
;
1101 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1102 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1103 scan_inst
->saturate
|= inst
->saturate
;
1105 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1107 inst
->remove(block
);
1113 invalidate_live_intervals();
1119 * Splits virtual GRFs requesting more than one contiguous physical register.
1121 * We initially create large virtual GRFs for temporary structures, arrays,
1122 * and matrices, so that the dereference visitor functions can add reg_offsets
1123 * to work their way down to the actual member being accessed. But when it
1124 * comes to optimization, we'd like to treat each register as individual
1125 * storage if possible.
1127 * So far, the only thing that might prevent splitting is a send message from
1131 vec4_visitor::split_virtual_grfs()
1133 int num_vars
= this->alloc
.count
;
1134 int new_virtual_grf
[num_vars
];
1135 bool split_grf
[num_vars
];
1137 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1139 /* Try to split anything > 0 sized. */
1140 for (int i
= 0; i
< num_vars
; i
++) {
1141 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1144 /* Check that the instructions are compatible with the registers we're trying
1147 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1148 if (inst
->dst
.file
== GRF
&& inst
->regs_written
> 1)
1149 split_grf
[inst
->dst
.reg
] = false;
1151 for (int i
= 0; i
< 3; i
++) {
1152 if (inst
->src
[i
].file
== GRF
&& inst
->regs_read(i
) > 1)
1153 split_grf
[inst
->src
[i
].reg
] = false;
1157 /* Allocate new space for split regs. Note that the virtual
1158 * numbers will be contiguous.
1160 for (int i
= 0; i
< num_vars
; i
++) {
1164 new_virtual_grf
[i
] = alloc
.allocate(1);
1165 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1166 unsigned reg
= alloc
.allocate(1);
1167 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1170 this->alloc
.sizes
[i
] = 1;
1173 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1174 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1175 inst
->dst
.reg_offset
!= 0) {
1176 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1177 inst
->dst
.reg_offset
- 1);
1178 inst
->dst
.reg_offset
= 0;
1180 for (int i
= 0; i
< 3; i
++) {
1181 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1182 inst
->src
[i
].reg_offset
!= 0) {
1183 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1184 inst
->src
[i
].reg_offset
- 1);
1185 inst
->src
[i
].reg_offset
= 0;
1189 invalidate_live_intervals();
1193 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1195 dump_instruction(be_inst
, stderr
);
1199 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1201 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1203 if (inst
->predicate
) {
1204 fprintf(file
, "(%cf0.%d) ",
1205 inst
->predicate_inverse
? '-' : '+',
1209 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1211 fprintf(file
, ".sat");
1212 if (inst
->conditional_mod
) {
1213 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1214 if (!inst
->predicate
&&
1215 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1216 inst
->opcode
!= BRW_OPCODE_IF
&&
1217 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1218 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1223 switch (inst
->dst
.file
) {
1225 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1228 fprintf(file
, "m%d", inst
->dst
.reg
);
1231 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1232 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1234 fprintf(file
, "null");
1236 case BRW_ARF_ADDRESS
:
1237 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1239 case BRW_ARF_ACCUMULATOR
:
1240 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1243 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1244 inst
->dst
.fixed_hw_reg
.subnr
);
1247 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1248 inst
->dst
.fixed_hw_reg
.subnr
);
1252 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1254 if (inst
->dst
.fixed_hw_reg
.subnr
)
1255 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1258 fprintf(file
, "(null)");
1261 fprintf(file
, "???");
1264 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1266 if (inst
->dst
.writemask
& 1)
1268 if (inst
->dst
.writemask
& 2)
1270 if (inst
->dst
.writemask
& 4)
1272 if (inst
->dst
.writemask
& 8)
1275 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1277 if (inst
->src
[0].file
!= BAD_FILE
)
1278 fprintf(file
, ", ");
1280 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1281 if (inst
->src
[i
].negate
)
1283 if (inst
->src
[i
].abs
)
1285 switch (inst
->src
[i
].file
) {
1287 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1290 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1293 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1296 switch (inst
->src
[i
].type
) {
1297 case BRW_REGISTER_TYPE_F
:
1298 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1300 case BRW_REGISTER_TYPE_D
:
1301 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1303 case BRW_REGISTER_TYPE_UD
:
1304 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1306 case BRW_REGISTER_TYPE_VF
:
1307 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1308 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1309 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1310 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1311 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1314 fprintf(file
, "???");
1319 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1321 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1323 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1324 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1326 fprintf(file
, "null");
1328 case BRW_ARF_ADDRESS
:
1329 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1331 case BRW_ARF_ACCUMULATOR
:
1332 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1335 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1336 inst
->src
[i
].fixed_hw_reg
.subnr
);
1339 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1340 inst
->src
[i
].fixed_hw_reg
.subnr
);
1344 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1346 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1347 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1348 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1352 fprintf(file
, "(null)");
1355 fprintf(file
, "???");
1359 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1360 if (inst
->src
[i
].reg_offset
!= 0 &&
1361 inst
->src
[i
].file
== GRF
&&
1362 alloc
.sizes
[inst
->src
[i
].reg
] != 1)
1363 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1365 if (inst
->src
[i
].file
!= IMM
) {
1366 static const char *chans
[4] = {"x", "y", "z", "w"};
1368 for (int c
= 0; c
< 4; c
++) {
1369 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1373 if (inst
->src
[i
].abs
)
1376 if (inst
->src
[i
].file
!= IMM
) {
1377 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1380 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1381 fprintf(file
, ", ");
1384 fprintf(file
, "\n");
1388 static inline struct brw_reg
1389 attribute_to_hw_reg(int attr
, bool interleaved
)
1392 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1394 return brw_vec8_grf(attr
, 0);
1399 * Replace each register of type ATTR in this->instructions with a reference
1400 * to a fixed HW register.
1402 * If interleaved is true, then each attribute takes up half a register, with
1403 * register N containing attribute 2*N in its first half and attribute 2*N+1
1404 * in its second half (this corresponds to the payload setup used by geometry
1405 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1406 * false, then each attribute takes up a whole register, with register N
1407 * containing attribute N (this corresponds to the payload setup used by
1408 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1411 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1414 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1415 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1416 if (inst
->dst
.file
== ATTR
) {
1417 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1419 /* All attributes used in the shader need to have been assigned a
1420 * hardware register by the caller
1424 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1425 reg
.type
= inst
->dst
.type
;
1426 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1428 inst
->dst
.file
= HW_REG
;
1429 inst
->dst
.fixed_hw_reg
= reg
;
1432 for (int i
= 0; i
< 3; i
++) {
1433 if (inst
->src
[i
].file
!= ATTR
)
1436 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1438 /* All attributes used in the shader need to have been assigned a
1439 * hardware register by the caller
1443 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1444 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1445 reg
.type
= inst
->src
[i
].type
;
1446 if (inst
->src
[i
].abs
)
1448 if (inst
->src
[i
].negate
)
1451 inst
->src
[i
].file
= HW_REG
;
1452 inst
->src
[i
].fixed_hw_reg
= reg
;
1458 vec4_vs_visitor::setup_attributes(int payload_reg
)
1461 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1462 memset(attribute_map
, 0, sizeof(attribute_map
));
1465 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1466 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1467 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1472 /* VertexID is stored by the VF as the last vertex element, but we
1473 * don't represent it with a flag in inputs_read, so we call it
1476 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1477 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1481 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1483 /* The BSpec says we always have to read at least one thing from
1484 * the VF, and it appears that the hardware wedges otherwise.
1486 if (nr_attributes
== 0)
1489 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1491 unsigned vue_entries
=
1492 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1494 if (devinfo
->gen
== 6)
1495 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1497 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1499 return payload_reg
+ nr_attributes
;
1503 vec4_visitor::setup_uniforms(int reg
)
1505 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1507 /* The pre-gen6 VS requires that some push constants get loaded no
1508 * matter what, or the GPU would hang.
1510 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1511 assert(this->uniforms
< this->uniform_array_size
);
1512 this->uniform_vector_size
[this->uniforms
] = 1;
1514 stage_prog_data
->param
=
1515 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1516 for (unsigned int i
= 0; i
< 4; i
++) {
1517 unsigned int slot
= this->uniforms
* 4 + i
;
1518 static gl_constant_value zero
= { 0.0 };
1519 stage_prog_data
->param
[slot
] = &zero
;
1525 reg
+= ALIGN(uniforms
, 2) / 2;
1528 stage_prog_data
->nr_params
= this->uniforms
* 4;
1530 prog_data
->base
.curb_read_length
=
1531 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1537 vec4_vs_visitor::setup_payload(void)
1541 /* The payload always contains important data in g0, which contains
1542 * the URB handles that are passed on to the URB write at the end
1543 * of the thread. So, we always start push constants at g1.
1547 reg
= setup_uniforms(reg
);
1549 reg
= setup_attributes(reg
);
1551 this->first_non_payload_grf
= reg
;
1555 vec4_visitor::assign_binding_table_offsets()
1557 assign_common_binding_table_offsets(0);
1561 vec4_visitor::get_timestamp()
1563 assert(devinfo
->gen
>= 7);
1565 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1570 BRW_REGISTER_TYPE_UD
,
1571 BRW_VERTICAL_STRIDE_0
,
1573 BRW_HORIZONTAL_STRIDE_4
,
1577 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1579 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1580 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1581 * even if it's not enabled in the dispatch.
1583 mov
->force_writemask_all
= true;
1585 return src_reg(dst
);
1589 vec4_visitor::emit_shader_time_begin()
1591 current_annotation
= "shader time start";
1592 shader_start_time
= get_timestamp();
1596 vec4_visitor::emit_shader_time_end()
1598 current_annotation
= "shader time end";
1599 src_reg shader_end_time
= get_timestamp();
1602 /* Check that there weren't any timestamp reset events (assuming these
1603 * were the only two timestamp reads that happened).
1605 src_reg reset_end
= shader_end_time
;
1606 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1607 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1608 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1610 emit(IF(BRW_PREDICATE_NORMAL
));
1612 /* Take the current timestamp and get the delta. */
1613 shader_start_time
.negate
= true;
1614 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1615 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1617 /* If there were no instructions between the two timestamp gets, the diff
1618 * is 2 cycles. Remove that overhead, so I can forget about that when
1619 * trying to determine the time taken for single instructions.
1621 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1623 emit_shader_time_write(st_base
, src_reg(diff
));
1624 emit_shader_time_write(st_written
, src_reg(1u));
1625 emit(BRW_OPCODE_ELSE
);
1626 emit_shader_time_write(st_reset
, src_reg(1u));
1627 emit(BRW_OPCODE_ENDIF
);
1631 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1634 int shader_time_index
=
1635 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1638 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1640 dst_reg offset
= dst
;
1644 offset
.type
= BRW_REGISTER_TYPE_UD
;
1645 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1647 time
.type
= BRW_REGISTER_TYPE_UD
;
1648 emit(MOV(time
, src_reg(value
)));
1650 vec4_instruction
*inst
=
1651 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1658 sanity_param_count
= prog
->Parameters
->NumParameters
;
1660 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1661 emit_shader_time_begin();
1663 assign_binding_table_offsets();
1667 /* Generate VS IR for main(). (the visitor only descends into
1668 * functions called "main").
1671 visit_instructions(shader
->base
.ir
);
1673 emit_program_code();
1677 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1678 setup_uniform_clipplane_values();
1684 /* Before any optimization, push array accesses out to scratch
1685 * space where we need them to be. This pass may allocate new
1686 * virtual GRFs, so we want to do it early. It also makes sure
1687 * that we have reladdr computations available for CSE, since we'll
1688 * often do repeated subexpressions for those.
1691 move_grf_array_access_to_scratch();
1692 move_uniform_array_access_to_pull_constants();
1694 /* The ARB_vertex_program frontend emits pull constant loads directly
1695 * rather than using reladdr, so we don't need to walk through all the
1696 * instructions looking for things to move. There isn't anything.
1698 * We do still need to split things to vec4 size.
1700 split_uniform_registers();
1702 pack_uniform_registers();
1703 move_push_constants_to_pull_constants();
1704 split_virtual_grfs();
1706 #define OPT(pass, args...) ({ \
1708 bool this_progress = pass(args); \
1710 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1711 char filename[64]; \
1712 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1713 stage_abbrev, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1715 backend_visitor::dump_instructions(filename); \
1718 progress = progress || this_progress; \
1723 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1725 snprintf(filename
, 64, "%s-%04d-00-start",
1726 stage_abbrev
, shader_prog
? shader_prog
->Name
: 0);
1728 backend_visitor::dump_instructions(filename
);
1739 OPT(opt_reduce_swizzle
);
1740 OPT(dead_code_eliminate
);
1741 OPT(dead_control_flow_eliminate
, this);
1742 OPT(opt_copy_propagation
);
1745 OPT(opt_register_coalesce
);
1750 if (OPT(opt_vector_float
)) {
1752 OPT(opt_copy_propagation
, false);
1753 OPT(opt_copy_propagation
, true);
1754 OPT(dead_code_eliminate
);
1763 /* Debug of register spilling: Go spill everything. */
1764 const int grf_count
= alloc
.count
;
1765 float spill_costs
[alloc
.count
];
1766 bool no_spill
[alloc
.count
];
1767 evaluate_spill_costs(spill_costs
, no_spill
);
1768 for (int i
= 0; i
< grf_count
; i
++) {
1775 while (!reg_allocate()) {
1780 opt_schedule_instructions();
1782 opt_set_dependency_control();
1784 /* If any state parameters were appended, then ParameterValues could have
1785 * been realloced, in which case the driver uniform storage set up by
1786 * _mesa_associate_uniform_storage() would point to freed memory. Make
1787 * sure that didn't happen.
1789 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1794 } /* namespace brw */
1799 * Compile a vertex shader.
1801 * Returns the final assembly and the program's size.
1804 brw_vs_emit(struct brw_context
*brw
,
1805 struct gl_shader_program
*prog
,
1806 struct brw_vs_compile
*c
,
1807 struct brw_vs_prog_data
*prog_data
,
1809 unsigned *final_assembly_size
)
1811 bool start_busy
= false;
1812 double start_time
= 0;
1813 const unsigned *assembly
= NULL
;
1815 brw
->ctx
.Const
.ShaderCompilerOptions
[MESA_SHADER_VERTEX
].NirOptions
!= NULL
;
1817 if (unlikely(brw
->perf_debug
)) {
1818 start_busy
= (brw
->batch
.last_bo
&&
1819 drm_intel_bo_busy(brw
->batch
.last_bo
));
1820 start_time
= get_time();
1823 struct brw_shader
*shader
= NULL
;
1825 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1827 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1828 brw_dump_ir("vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1830 if (use_nir
&& !c
->vp
->program
.Base
.nir
) {
1831 /* Normally we generate NIR in LinkShader() or ProgramStringNotify(), but
1832 * Mesa's fixed-function vertex program handling doesn't notify the driver
1833 * at all. Just do it here, at the last minute, even though it's lame.
1835 assert(c
->vp
->program
.Base
.Id
== 0 && prog
== NULL
);
1836 c
->vp
->program
.Base
.nir
=
1837 brw_create_nir(brw
, NULL
, &c
->vp
->program
.Base
, MESA_SHADER_VERTEX
);
1840 if (brw
->scalar_vs
&& (prog
|| use_nir
)) {
1841 fs_visitor
v(brw
, mem_ctx
, &c
->key
, prog_data
, prog
, &c
->vp
->program
, 8);
1844 prog
->LinkStatus
= false;
1845 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1848 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1854 fs_generator
g(brw
, mem_ctx
, (void *) &c
->key
, &prog_data
->base
.base
,
1855 &c
->vp
->program
.Base
, v
.promoted_constants
,
1856 v
.runtime_check_aads_emit
, "VS");
1857 if (INTEL_DEBUG
& DEBUG_VS
) {
1860 name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
1861 prog
->Label
? prog
->Label
: "unnamed",
1864 name
= ralloc_asprintf(mem_ctx
, "vertex program %d",
1865 c
->vp
->program
.Base
.Id
);
1867 g
.enable_debug(name
);
1869 g
.generate_code(v
.cfg
, 8);
1870 assembly
= g
.get_assembly(final_assembly_size
);
1872 prog_data
->base
.simd8
= true;
1873 c
->base
.last_scratch
= v
.last_scratch
;
1877 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1880 prog
->LinkStatus
= false;
1881 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1884 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1890 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1891 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
, "vertex", "VS");
1892 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1895 if (unlikely(brw
->perf_debug
) && shader
) {
1896 if (shader
->compiled_once
) {
1897 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1899 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1900 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1901 (get_time() - start_time
) * 1000);
1903 shader
->compiled_once
= true;
1911 brw_vue_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1912 struct brw_vue_prog_key
*key
,
1913 GLuint id
, struct gl_program
*prog
)
1915 struct brw_context
*brw
= brw_context(ctx
);
1916 key
->program_string_id
= id
;
1918 brw_setup_tex_for_precompile(brw
, &key
->tex
, prog
);