2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "main/macros.h"
30 #include "main/shaderobj.h"
31 #include "program/prog_print.h"
32 #include "program/prog_parameter.h"
35 #define MAX_INSTRUCTION (1 << 30)
42 * Common helper for constructing swizzles. When only a subset of
43 * channels of a vec4 are used, we don't want to reference the other
44 * channels, as that will tell optimization passes that those other
48 swizzle_for_size(int size
)
50 static const unsigned size_swizzles
[4] = {
51 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
57 assert((size
>= 1) && (size
<= 4));
58 return size_swizzles
[size
- 1];
64 memset(this, 0, sizeof(*this));
66 this->file
= BAD_FILE
;
69 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
75 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
76 this->swizzle
= swizzle_for_size(type
->vector_elements
);
78 this->swizzle
= SWIZZLE_XYZW
;
81 /** Generic unset register constructor. */
87 src_reg::src_reg(float f
)
92 this->type
= BRW_REGISTER_TYPE_F
;
96 src_reg::src_reg(uint32_t u
)
101 this->type
= BRW_REGISTER_TYPE_UD
;
105 src_reg::src_reg(int32_t i
)
110 this->type
= BRW_REGISTER_TYPE_D
;
114 src_reg::src_reg(dst_reg reg
)
118 this->file
= reg
.file
;
120 this->reg_offset
= reg
.reg_offset
;
121 this->type
= reg
.type
;
122 this->reladdr
= reg
.reladdr
;
123 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
129 for (int i
= 0; i
< 4; i
++) {
130 if (!(reg
.writemask
& (1 << i
)))
133 swizzles
[next_chan
++] = last
= i
;
136 for (; next_chan
< 4; next_chan
++) {
137 swizzles
[next_chan
] = last
;
140 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
141 swizzles
[2], swizzles
[3]);
147 memset(this, 0, sizeof(*this));
148 this->file
= BAD_FILE
;
149 this->writemask
= WRITEMASK_XYZW
;
157 dst_reg::dst_reg(register_file file
, int reg
)
165 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
172 this->type
= brw_type_for_base_type(type
);
173 this->writemask
= writemask
;
176 dst_reg::dst_reg(struct brw_reg reg
)
181 this->fixed_hw_reg
= reg
;
184 dst_reg::dst_reg(src_reg reg
)
188 this->file
= reg
.file
;
190 this->reg_offset
= reg
.reg_offset
;
191 this->type
= reg
.type
;
192 /* How should we do writemasking when converting from a src_reg? It seems
193 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
194 * what about for src.wx? Just special-case src.xxxx for now.
196 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
197 this->writemask
= WRITEMASK_X
;
199 this->writemask
= WRITEMASK_XYZW
;
200 this->reladdr
= reg
.reladdr
;
201 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
205 vec4_instruction::is_send_from_grf()
208 case SHADER_OPCODE_SHADER_TIME_ADD
:
209 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
217 vec4_visitor::can_do_source_mods(vec4_instruction
*inst
)
219 if (brw
->gen
== 6 && inst
->is_math())
222 if (inst
->is_send_from_grf())
225 if (!inst
->can_do_source_mods())
232 * Returns how many MRFs an opcode will write over.
234 * Note that this is not the 0 or 1 implied writes in an actual gen
235 * instruction -- the generate_* functions generate additional MOVs
239 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
244 switch (inst
->opcode
) {
245 case SHADER_OPCODE_RCP
:
246 case SHADER_OPCODE_RSQ
:
247 case SHADER_OPCODE_SQRT
:
248 case SHADER_OPCODE_EXP2
:
249 case SHADER_OPCODE_LOG2
:
250 case SHADER_OPCODE_SIN
:
251 case SHADER_OPCODE_COS
:
253 case SHADER_OPCODE_INT_QUOTIENT
:
254 case SHADER_OPCODE_INT_REMAINDER
:
255 case SHADER_OPCODE_POW
:
257 case VS_OPCODE_URB_WRITE
:
259 case VS_OPCODE_PULL_CONSTANT_LOAD
:
261 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
263 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
265 case GS_OPCODE_URB_WRITE
:
266 case GS_OPCODE_THREAD_END
:
268 case SHADER_OPCODE_SHADER_TIME_ADD
:
270 case SHADER_OPCODE_TEX
:
271 case SHADER_OPCODE_TXL
:
272 case SHADER_OPCODE_TXD
:
273 case SHADER_OPCODE_TXF
:
274 case SHADER_OPCODE_TXF_MS
:
275 case SHADER_OPCODE_TXS
:
276 case SHADER_OPCODE_TG4
:
277 case SHADER_OPCODE_TG4_OFFSET
:
278 return inst
->header_present
? 1 : 0;
279 case SHADER_OPCODE_UNTYPED_ATOMIC
:
280 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
283 assert(!"not reached");
289 src_reg::equals(src_reg
*r
)
291 return (file
== r
->file
&&
293 reg_offset
== r
->reg_offset
&&
295 negate
== r
->negate
&&
297 swizzle
== r
->swizzle
&&
298 !reladdr
&& !r
->reladdr
&&
299 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
300 sizeof(fixed_hw_reg
)) == 0 &&
305 * Must be called after calculate_live_intervales() to remove unused
306 * writes to registers -- register allocation will fail otherwise
307 * because something deffed but not used won't be considered to
308 * interfere with other regs.
311 vec4_visitor::dead_code_eliminate()
313 bool progress
= false;
316 calculate_live_intervals();
318 foreach_list_safe(node
, &this->instructions
) {
319 vec4_instruction
*inst
= (vec4_instruction
*)node
;
321 if (inst
->dst
.file
== GRF
) {
322 assert(this->virtual_grf_end
[inst
->dst
.reg
] >= pc
);
323 if (this->virtual_grf_end
[inst
->dst
.reg
] == pc
) {
324 /* Don't dead code eliminate instructions that write to the
325 * accumulator as a side-effect. Instead just set the destination
326 * to the null register to free it.
328 switch (inst
->opcode
) {
329 case BRW_OPCODE_ADDC
:
330 case BRW_OPCODE_SUBB
:
331 case BRW_OPCODE_MACH
:
332 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
346 live_intervals_valid
= false;
352 vec4_visitor::split_uniform_registers()
354 /* Prior to this, uniforms have been in an array sized according to
355 * the number of vector uniforms present, sparsely filled (so an
356 * aggregate results in reg indices being skipped over). Now we're
357 * going to cut those aggregates up so each .reg index is one
358 * vector. The goal is to make elimination of unused uniform
359 * components easier later.
361 foreach_list(node
, &this->instructions
) {
362 vec4_instruction
*inst
= (vec4_instruction
*)node
;
364 for (int i
= 0 ; i
< 3; i
++) {
365 if (inst
->src
[i
].file
!= UNIFORM
)
368 assert(!inst
->src
[i
].reladdr
);
370 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
371 inst
->src
[i
].reg_offset
= 0;
375 /* Update that everything is now vector-sized. */
376 for (int i
= 0; i
< this->uniforms
; i
++) {
377 this->uniform_size
[i
] = 1;
382 vec4_visitor::pack_uniform_registers()
384 bool uniform_used
[this->uniforms
];
385 int new_loc
[this->uniforms
];
386 int new_chan
[this->uniforms
];
388 memset(uniform_used
, 0, sizeof(uniform_used
));
389 memset(new_loc
, 0, sizeof(new_loc
));
390 memset(new_chan
, 0, sizeof(new_chan
));
392 /* Find which uniform vectors are actually used by the program. We
393 * expect unused vector elements when we've moved array access out
394 * to pull constants, and from some GLSL code generators like wine.
396 foreach_list(node
, &this->instructions
) {
397 vec4_instruction
*inst
= (vec4_instruction
*)node
;
399 for (int i
= 0 ; i
< 3; i
++) {
400 if (inst
->src
[i
].file
!= UNIFORM
)
403 uniform_used
[inst
->src
[i
].reg
] = true;
407 int new_uniform_count
= 0;
409 /* Now, figure out a packing of the live uniform vectors into our
412 for (int src
= 0; src
< uniforms
; src
++) {
413 int size
= this->uniform_vector_size
[src
];
415 if (!uniform_used
[src
]) {
416 this->uniform_vector_size
[src
] = 0;
421 /* Find the lowest place we can slot this uniform in. */
422 for (dst
= 0; dst
< src
; dst
++) {
423 if (this->uniform_vector_size
[dst
] + size
<= 4)
432 new_chan
[src
] = this->uniform_vector_size
[dst
];
434 /* Move the references to the data */
435 for (int j
= 0; j
< size
; j
++) {
436 prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
437 prog_data
->param
[src
* 4 + j
];
440 this->uniform_vector_size
[dst
] += size
;
441 this->uniform_vector_size
[src
] = 0;
444 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
447 this->uniforms
= new_uniform_count
;
449 /* Now, update the instructions for our repacked uniforms. */
450 foreach_list(node
, &this->instructions
) {
451 vec4_instruction
*inst
= (vec4_instruction
*)node
;
453 for (int i
= 0 ; i
< 3; i
++) {
454 int src
= inst
->src
[i
].reg
;
456 if (inst
->src
[i
].file
!= UNIFORM
)
459 inst
->src
[i
].reg
= new_loc
[src
];
461 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
462 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
463 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
464 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
465 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
471 src_reg::is_zero() const
476 if (type
== BRW_REGISTER_TYPE_F
) {
484 src_reg::is_one() const
489 if (type
== BRW_REGISTER_TYPE_F
) {
497 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
499 * While GLSL IR also performs this optimization, we end up with it in
500 * our instruction stream for a couple of reasons. One is that we
501 * sometimes generate silly instructions, for example in array access
502 * where we'll generate "ADD offset, index, base" even if base is 0.
503 * The other is that GLSL IR's constant propagation doesn't track the
504 * components of aggregates, so some VS patterns (initialize matrix to
505 * 0, accumulate in vertex blending factors) end up breaking down to
506 * instructions involving 0.
509 vec4_visitor::opt_algebraic()
511 bool progress
= false;
513 foreach_list(node
, &this->instructions
) {
514 vec4_instruction
*inst
= (vec4_instruction
*)node
;
516 switch (inst
->opcode
) {
518 if (inst
->src
[1].is_zero()) {
519 inst
->opcode
= BRW_OPCODE_MOV
;
520 inst
->src
[1] = src_reg();
526 if (inst
->src
[1].is_zero()) {
527 inst
->opcode
= BRW_OPCODE_MOV
;
528 switch (inst
->src
[0].type
) {
529 case BRW_REGISTER_TYPE_F
:
530 inst
->src
[0] = src_reg(0.0f
);
532 case BRW_REGISTER_TYPE_D
:
533 inst
->src
[0] = src_reg(0);
535 case BRW_REGISTER_TYPE_UD
:
536 inst
->src
[0] = src_reg(0u);
539 assert(!"not reached");
540 inst
->src
[0] = src_reg(0.0f
);
543 inst
->src
[1] = src_reg();
545 } else if (inst
->src
[1].is_one()) {
546 inst
->opcode
= BRW_OPCODE_MOV
;
547 inst
->src
[1] = src_reg();
557 this->live_intervals_valid
= false;
563 * Only a limited number of hardware registers may be used for push
564 * constants, so this turns access to the overflowed constants into
568 vec4_visitor::move_push_constants_to_pull_constants()
570 int pull_constant_loc
[this->uniforms
];
572 /* Only allow 32 registers (256 uniform components) as push constants,
573 * which is the limit on gen6.
575 int max_uniform_components
= 32 * 8;
576 if (this->uniforms
* 4 <= max_uniform_components
)
579 /* Make some sort of choice as to which uniforms get sent to pull
580 * constants. We could potentially do something clever here like
581 * look for the most infrequently used uniform vec4s, but leave
584 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
585 pull_constant_loc
[i
/ 4] = -1;
587 if (i
>= max_uniform_components
) {
588 const float **values
= &prog_data
->param
[i
];
590 /* Try to find an existing copy of this uniform in the pull
591 * constants if it was part of an array access already.
593 for (unsigned int j
= 0; j
< prog_data
->nr_pull_params
; j
+= 4) {
596 for (matches
= 0; matches
< 4; matches
++) {
597 if (prog_data
->pull_param
[j
+ matches
] != values
[matches
])
602 pull_constant_loc
[i
/ 4] = j
/ 4;
607 if (pull_constant_loc
[i
/ 4] == -1) {
608 assert(prog_data
->nr_pull_params
% 4 == 0);
609 pull_constant_loc
[i
/ 4] = prog_data
->nr_pull_params
/ 4;
611 for (int j
= 0; j
< 4; j
++) {
612 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
618 /* Now actually rewrite usage of the things we've moved to pull
621 foreach_list_safe(node
, &this->instructions
) {
622 vec4_instruction
*inst
= (vec4_instruction
*)node
;
624 for (int i
= 0 ; i
< 3; i
++) {
625 if (inst
->src
[i
].file
!= UNIFORM
||
626 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
629 int uniform
= inst
->src
[i
].reg
;
631 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
633 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
634 pull_constant_loc
[uniform
]);
636 inst
->src
[i
].file
= temp
.file
;
637 inst
->src
[i
].reg
= temp
.reg
;
638 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
639 inst
->src
[i
].reladdr
= NULL
;
643 /* Repack push constants to remove the now-unused ones. */
644 pack_uniform_registers();
648 * Sets the dependency control fields on instructions after register
649 * allocation and before the generator is run.
651 * When you have a sequence of instructions like:
653 * DP4 temp.x vertex uniform[0]
654 * DP4 temp.y vertex uniform[0]
655 * DP4 temp.z vertex uniform[0]
656 * DP4 temp.w vertex uniform[0]
658 * The hardware doesn't know that it can actually run the later instructions
659 * while the previous ones are in flight, producing stalls. However, we have
660 * manual fields we can set in the instructions that let it do so.
663 vec4_visitor::opt_set_dependency_control()
665 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
666 uint8_t grf_channels_written
[BRW_MAX_GRF
];
667 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
668 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
672 assert(prog_data
->total_grf
||
673 !"Must be called after register allocation");
675 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
676 bblock_t
*bblock
= cfg
.blocks
[i
];
677 vec4_instruction
*inst
;
679 memset(last_grf_write
, 0, sizeof(last_grf_write
));
680 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
682 for (inst
= (vec4_instruction
*)bblock
->start
;
683 inst
!= (vec4_instruction
*)bblock
->end
->next
;
684 inst
= (vec4_instruction
*)inst
->next
) {
685 /* If we read from a register that we were doing dependency control
686 * on, don't do dependency control across the read.
688 for (int i
= 0; i
< 3; i
++) {
689 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
690 if (inst
->src
[i
].file
== GRF
) {
691 last_grf_write
[reg
] = NULL
;
692 } else if (inst
->src
[i
].file
== HW_REG
) {
693 memset(last_grf_write
, 0, sizeof(last_grf_write
));
696 assert(inst
->src
[i
].file
!= MRF
);
699 /* In the presence of send messages, totally interrupt dependency
700 * control. They're long enough that the chance of dependency
701 * control around them just doesn't matter.
704 memset(last_grf_write
, 0, sizeof(last_grf_write
));
705 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
709 /* It looks like setting dependency control on a predicated
710 * instruction hangs the GPU.
712 if (inst
->predicate
) {
713 memset(last_grf_write
, 0, sizeof(last_grf_write
));
714 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
718 /* Now, see if we can do dependency control for this instruction
719 * against a previous one writing to its destination.
721 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
722 if (inst
->dst
.file
== GRF
) {
723 if (last_grf_write
[reg
] &&
724 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
725 last_grf_write
[reg
]->no_dd_clear
= true;
726 inst
->no_dd_check
= true;
728 grf_channels_written
[reg
] = 0;
731 last_grf_write
[reg
] = inst
;
732 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
733 } else if (inst
->dst
.file
== MRF
) {
734 if (last_mrf_write
[reg
] &&
735 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
736 last_mrf_write
[reg
]->no_dd_clear
= true;
737 inst
->no_dd_check
= true;
739 mrf_channels_written
[reg
] = 0;
742 last_mrf_write
[reg
] = inst
;
743 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
744 } else if (inst
->dst
.reg
== HW_REG
) {
745 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
746 memset(last_grf_write
, 0, sizeof(last_grf_write
));
747 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
748 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
755 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
759 /* If this instruction sets anything not referenced by swizzle, then we'd
760 * totally break it when we reswizzle.
762 if (dst
.writemask
& ~swizzle_mask
)
771 /* Check if there happens to be no reswizzling required. */
772 for (int c
= 0; c
< 4; c
++) {
773 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
774 /* Skip components of the swizzle not used by the dst. */
775 if (!(dst_writemask
& (1 << c
)))
778 /* We don't do the reswizzling yet, so just sanity check that we
789 * For any channels in the swizzle's source that were populated by this
790 * instruction, rewrite the instruction to put the appropriate result directly
793 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
796 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
798 int new_writemask
= 0;
804 for (int c
= 0; c
< 4; c
++) {
805 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
806 /* Skip components of the swizzle not used by the dst. */
807 if (!(dst_writemask
& (1 << c
)))
809 /* If we were populating this component, then populate the
810 * corresponding channel of the new dst.
812 if (dst
.writemask
& bit
)
813 new_writemask
|= (1 << c
);
815 dst
.writemask
= new_writemask
;
818 for (int c
= 0; c
< 4; c
++) {
819 /* Skip components of the swizzle not used by the dst. */
820 if (!(dst_writemask
& (1 << c
)))
823 /* We don't do the reswizzling yet, so just sanity check that we
826 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
833 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
834 * just written and then MOVed into another reg and making the original write
835 * of the GRF write directly to the final destination instead.
838 vec4_visitor::opt_register_coalesce()
840 bool progress
= false;
843 calculate_live_intervals();
845 foreach_list_safe(node
, &this->instructions
) {
846 vec4_instruction
*inst
= (vec4_instruction
*)node
;
851 if (inst
->opcode
!= BRW_OPCODE_MOV
||
852 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
854 inst
->src
[0].file
!= GRF
||
855 inst
->dst
.type
!= inst
->src
[0].type
||
856 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
859 bool to_mrf
= (inst
->dst
.file
== MRF
);
861 /* Can't coalesce this GRF if someone else was going to
864 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
867 /* We need to check interference with the final destination between this
868 * instruction and the earliest instruction involved in writing the GRF
869 * we're eliminating. To do that, keep track of which of our source
870 * channels we've seen initialized.
872 bool chans_needed
[4] = {false, false, false, false};
873 int chans_remaining
= 0;
874 int swizzle_mask
= 0;
875 for (int i
= 0; i
< 4; i
++) {
876 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
878 if (!(inst
->dst
.writemask
& (1 << i
)))
881 swizzle_mask
|= (1 << chan
);
883 if (!chans_needed
[chan
]) {
884 chans_needed
[chan
] = true;
889 /* Now walk up the instruction stream trying to see if we can rewrite
890 * everything writing to the temporary to write into the destination
893 vec4_instruction
*scan_inst
;
894 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
895 scan_inst
->prev
!= NULL
;
896 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
897 if (scan_inst
->dst
.file
== GRF
&&
898 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
899 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
900 /* Found something writing to the reg we want to coalesce away. */
902 /* SEND instructions can't have MRF as a destination. */
907 /* gen6 math instructions must have the destination be
908 * GRF, so no compute-to-MRF for them.
910 if (scan_inst
->is_math()) {
916 /* If we can't handle the swizzle, bail. */
917 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
918 inst
->src
[0].swizzle
,
923 /* Mark which channels we found unconditional writes for. */
924 if (!scan_inst
->predicate
) {
925 for (int i
= 0; i
< 4; i
++) {
926 if (scan_inst
->dst
.writemask
& (1 << i
) &&
928 chans_needed
[i
] = false;
934 if (chans_remaining
== 0)
938 /* We don't handle flow control here. Most computation of values
939 * that could be coalesced happens just before their use.
941 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
942 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
943 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
944 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
948 /* You can't read from an MRF, so if someone else reads our MRF's
949 * source GRF that we wanted to rewrite, that stops us. If it's a
950 * GRF we're trying to coalesce to, we don't actually handle
951 * rewriting sources so bail in that case as well.
953 bool interfered
= false;
954 for (int i
= 0; i
< 3; i
++) {
955 if (scan_inst
->src
[i
].file
== GRF
&&
956 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
957 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
964 /* If somebody else writes our destination here, we can't coalesce
967 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
968 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
972 /* Check for reads of the register we're trying to coalesce into. We
973 * can't go rewriting instructions above that to put some other value
974 * in the register instead.
976 if (to_mrf
&& scan_inst
->mlen
> 0) {
977 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
978 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
982 for (int i
= 0; i
< 3; i
++) {
983 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
984 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
985 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
994 if (chans_remaining
== 0) {
995 /* If we've made it here, we have an MOV we want to coalesce out, and
996 * a scan_inst pointing to the earliest instruction involved in
997 * computing the value. Now go rewrite the instruction stream
1001 while (scan_inst
!= inst
) {
1002 if (scan_inst
->dst
.file
== GRF
&&
1003 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1004 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1005 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
1006 inst
->src
[0].swizzle
);
1007 scan_inst
->dst
.file
= inst
->dst
.file
;
1008 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1009 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1010 scan_inst
->saturate
|= inst
->saturate
;
1012 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1020 live_intervals_valid
= false;
1026 * Splits virtual GRFs requesting more than one contiguous physical register.
1028 * We initially create large virtual GRFs for temporary structures, arrays,
1029 * and matrices, so that the dereference visitor functions can add reg_offsets
1030 * to work their way down to the actual member being accessed. But when it
1031 * comes to optimization, we'd like to treat each register as individual
1032 * storage if possible.
1034 * So far, the only thing that might prevent splitting is a send message from
1038 vec4_visitor::split_virtual_grfs()
1040 int num_vars
= this->virtual_grf_count
;
1041 int new_virtual_grf
[num_vars
];
1042 bool split_grf
[num_vars
];
1044 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1046 /* Try to split anything > 0 sized. */
1047 for (int i
= 0; i
< num_vars
; i
++) {
1048 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1051 /* Check that the instructions are compatible with the registers we're trying
1054 foreach_list(node
, &this->instructions
) {
1055 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1057 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1060 if (inst
->is_send_from_grf()) {
1061 for (int i
= 0; i
< 3; i
++) {
1062 if (inst
->src
[i
].file
== GRF
) {
1063 split_grf
[inst
->src
[i
].reg
] = false;
1069 /* Allocate new space for split regs. Note that the virtual
1070 * numbers will be contiguous.
1072 for (int i
= 0; i
< num_vars
; i
++) {
1076 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1077 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1078 int reg
= virtual_grf_alloc(1);
1079 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1082 this->virtual_grf_sizes
[i
] = 1;
1085 foreach_list(node
, &this->instructions
) {
1086 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1088 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1089 inst
->dst
.reg_offset
!= 0) {
1090 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1091 inst
->dst
.reg_offset
- 1);
1092 inst
->dst
.reg_offset
= 0;
1094 for (int i
= 0; i
< 3; i
++) {
1095 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1096 inst
->src
[i
].reg_offset
!= 0) {
1097 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1098 inst
->src
[i
].reg_offset
- 1);
1099 inst
->src
[i
].reg_offset
= 0;
1103 this->live_intervals_valid
= false;
1107 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1109 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1111 printf("%s ", brw_instruction_name(inst
->opcode
));
1113 switch (inst
->dst
.file
) {
1115 printf("vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1118 printf("m%d", inst
->dst
.reg
);
1127 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1129 if (inst
->dst
.writemask
& 1)
1131 if (inst
->dst
.writemask
& 2)
1133 if (inst
->dst
.writemask
& 4)
1135 if (inst
->dst
.writemask
& 8)
1140 for (int i
= 0; i
< 3; i
++) {
1141 switch (inst
->src
[i
].file
) {
1143 printf("vgrf%d", inst
->src
[i
].reg
);
1146 printf("attr%d", inst
->src
[i
].reg
);
1149 printf("u%d", inst
->src
[i
].reg
);
1152 switch (inst
->src
[i
].type
) {
1153 case BRW_REGISTER_TYPE_F
:
1154 printf("%fF", inst
->src
[i
].imm
.f
);
1156 case BRW_REGISTER_TYPE_D
:
1157 printf("%dD", inst
->src
[i
].imm
.i
);
1159 case BRW_REGISTER_TYPE_UD
:
1160 printf("%uU", inst
->src
[i
].imm
.u
);
1175 if (inst
->src
[i
].reg_offset
)
1176 printf(".%d", inst
->src
[i
].reg_offset
);
1178 static const char *chans
[4] = {"x", "y", "z", "w"};
1180 for (int c
= 0; c
< 4; c
++) {
1181 printf("%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1192 static inline struct brw_reg
1193 attribute_to_hw_reg(int attr
, bool interleaved
)
1196 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1198 return brw_vec8_grf(attr
, 0);
1203 * Replace each register of type ATTR in this->instructions with a reference
1204 * to a fixed HW register.
1206 * If interleaved is true, then each attribute takes up half a register, with
1207 * register N containing attribute 2*N in its first half and attribute 2*N+1
1208 * in its second half (this corresponds to the payload setup used by geometry
1209 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1210 * false, then each attribute takes up a whole register, with register N
1211 * containing attribute N (this corresponds to the payload setup used by
1212 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1215 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1218 foreach_list(node
, &this->instructions
) {
1219 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1221 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1222 if (inst
->dst
.file
== ATTR
) {
1223 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1225 /* All attributes used in the shader need to have been assigned a
1226 * hardware register by the caller
1230 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1231 reg
.type
= inst
->dst
.type
;
1232 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1234 inst
->dst
.file
= HW_REG
;
1235 inst
->dst
.fixed_hw_reg
= reg
;
1238 for (int i
= 0; i
< 3; i
++) {
1239 if (inst
->src
[i
].file
!= ATTR
)
1242 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1244 /* All attributes used in the shader need to have been assigned a
1245 * hardware register by the caller
1249 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1250 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1251 reg
.type
= inst
->src
[i
].type
;
1252 if (inst
->src
[i
].abs
)
1254 if (inst
->src
[i
].negate
)
1257 inst
->src
[i
].file
= HW_REG
;
1258 inst
->src
[i
].fixed_hw_reg
= reg
;
1264 vec4_vs_visitor::setup_attributes(int payload_reg
)
1267 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1268 memset(attribute_map
, 0, sizeof(attribute_map
));
1271 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1272 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1273 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1278 /* VertexID is stored by the VF as the last vertex element, but we
1279 * don't represent it with a flag in inputs_read, so we call it
1282 if (vs_prog_data
->uses_vertexid
) {
1283 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1287 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1289 /* The BSpec says we always have to read at least one thing from
1290 * the VF, and it appears that the hardware wedges otherwise.
1292 if (nr_attributes
== 0)
1295 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1297 unsigned vue_entries
=
1298 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1301 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1303 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1305 return payload_reg
+ nr_attributes
;
1309 vec4_visitor::setup_uniforms(int reg
)
1311 prog_data
->dispatch_grf_start_reg
= reg
;
1313 /* The pre-gen6 VS requires that some push constants get loaded no
1314 * matter what, or the GPU would hang.
1316 if (brw
->gen
< 6 && this->uniforms
== 0) {
1317 this->uniform_vector_size
[this->uniforms
] = 1;
1319 prog_data
->param
= reralloc(NULL
, prog_data
->param
, const float *, 4);
1320 for (unsigned int i
= 0; i
< 4; i
++) {
1321 unsigned int slot
= this->uniforms
* 4 + i
;
1322 static float zero
= 0.0;
1323 prog_data
->param
[slot
] = &zero
;
1329 reg
+= ALIGN(uniforms
, 2) / 2;
1332 prog_data
->nr_params
= this->uniforms
* 4;
1334 prog_data
->curb_read_length
= reg
- prog_data
->dispatch_grf_start_reg
;
1340 vec4_vs_visitor::setup_payload(void)
1344 /* The payload always contains important data in g0, which contains
1345 * the URB handles that are passed on to the URB write at the end
1346 * of the thread. So, we always start push constants at g1.
1350 reg
= setup_uniforms(reg
);
1352 reg
= setup_attributes(reg
);
1354 this->first_non_payload_grf
= reg
;
1358 vec4_visitor::get_timestamp()
1360 assert(brw
->gen
>= 7);
1362 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1365 BRW_REGISTER_TYPE_UD
,
1366 BRW_VERTICAL_STRIDE_0
,
1368 BRW_HORIZONTAL_STRIDE_4
,
1372 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1374 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1375 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1376 * even if it's not enabled in the dispatch.
1378 mov
->force_writemask_all
= true;
1380 return src_reg(dst
);
1384 vec4_visitor::emit_shader_time_begin()
1386 current_annotation
= "shader time start";
1387 shader_start_time
= get_timestamp();
1391 vec4_visitor::emit_shader_time_end()
1393 current_annotation
= "shader time end";
1394 src_reg shader_end_time
= get_timestamp();
1397 /* Check that there weren't any timestamp reset events (assuming these
1398 * were the only two timestamp reads that happened).
1400 src_reg reset_end
= shader_end_time
;
1401 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1402 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1403 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1405 emit(IF(BRW_PREDICATE_NORMAL
));
1407 /* Take the current timestamp and get the delta. */
1408 shader_start_time
.negate
= true;
1409 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1410 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1412 /* If there were no instructions between the two timestamp gets, the diff
1413 * is 2 cycles. Remove that overhead, so I can forget about that when
1414 * trying to determine the time taken for single instructions.
1416 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1418 emit_shader_time_write(ST_VS
, src_reg(diff
));
1419 emit_shader_time_write(ST_VS_WRITTEN
, src_reg(1u));
1420 emit(BRW_OPCODE_ELSE
);
1421 emit_shader_time_write(ST_VS_RESET
, src_reg(1u));
1422 emit(BRW_OPCODE_ENDIF
);
1426 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1429 int shader_time_index
=
1430 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1433 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1435 dst_reg offset
= dst
;
1439 offset
.type
= BRW_REGISTER_TYPE_UD
;
1440 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1442 time
.type
= BRW_REGISTER_TYPE_UD
;
1443 emit(MOV(time
, src_reg(value
)));
1445 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1451 sanity_param_count
= prog
->Parameters
->NumParameters
;
1453 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1454 emit_shader_time_begin();
1456 assign_common_binding_table_offsets(0);
1460 /* Generate VS IR for main(). (the visitor only descends into
1461 * functions called "main").
1464 visit_instructions(shader
->ir
);
1466 emit_program_code();
1470 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1471 setup_uniform_clipplane_values();
1475 /* Before any optimization, push array accesses out to scratch
1476 * space where we need them to be. This pass may allocate new
1477 * virtual GRFs, so we want to do it early. It also makes sure
1478 * that we have reladdr computations available for CSE, since we'll
1479 * often do repeated subexpressions for those.
1482 move_grf_array_access_to_scratch();
1483 move_uniform_array_access_to_pull_constants();
1485 /* The ARB_vertex_program frontend emits pull constant loads directly
1486 * rather than using reladdr, so we don't need to walk through all the
1487 * instructions looking for things to move. There isn't anything.
1489 * We do still need to split things to vec4 size.
1491 split_uniform_registers();
1493 pack_uniform_registers();
1494 move_push_constants_to_pull_constants();
1495 split_virtual_grfs();
1500 progress
= dead_code_eliminate() || progress
;
1501 progress
= opt_copy_propagation() || progress
;
1502 progress
= opt_algebraic() || progress
;
1503 progress
= opt_register_coalesce() || progress
;
1513 /* Debug of register spilling: Go spill everything. */
1514 const int grf_count
= virtual_grf_count
;
1515 float spill_costs
[virtual_grf_count
];
1516 bool no_spill
[virtual_grf_count
];
1517 evaluate_spill_costs(spill_costs
, no_spill
);
1518 for (int i
= 0; i
< grf_count
; i
++) {
1525 while (!reg_allocate()) {
1530 opt_schedule_instructions();
1532 opt_set_dependency_control();
1534 /* If any state parameters were appended, then ParameterValues could have
1535 * been realloced, in which case the driver uniform storage set up by
1536 * _mesa_associate_uniform_storage() would point to freed memory. Make
1537 * sure that didn't happen.
1539 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1544 } /* namespace brw */
1549 * Compile a vertex shader.
1551 * Returns the final assembly and the program's size.
1554 brw_vs_emit(struct brw_context
*brw
,
1555 struct gl_shader_program
*prog
,
1556 struct brw_vs_compile
*c
,
1557 struct brw_vs_prog_data
*prog_data
,
1559 unsigned *final_assembly_size
)
1561 bool start_busy
= false;
1562 float start_time
= 0;
1564 if (unlikely(brw
->perf_debug
)) {
1565 start_busy
= (brw
->batch
.last_bo
&&
1566 drm_intel_bo_busy(brw
->batch
.last_bo
));
1567 start_time
= get_time();
1570 struct brw_shader
*shader
= NULL
;
1572 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1574 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1576 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
1577 _mesa_print_ir(shader
->ir
, NULL
);
1580 printf("ARB_vertex_program %d for native vertex shader\n",
1581 c
->vp
->program
.Base
.Id
);
1582 _mesa_print_program(&c
->vp
->program
.Base
);
1586 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, shader
, mem_ctx
);
1589 prog
->LinkStatus
= false;
1590 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1593 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1599 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
, mem_ctx
,
1600 INTEL_DEBUG
& DEBUG_VS
);
1601 const unsigned *generated
=g
.generate_assembly(&v
.instructions
,
1602 final_assembly_size
);
1604 if (unlikely(brw
->perf_debug
) && shader
) {
1605 if (shader
->compiled_once
) {
1606 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1608 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1609 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1610 (get_time() - start_time
) * 1000);
1612 shader
->compiled_once
= true;
1620 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1621 struct brw_vec4_prog_key
*key
,
1622 GLuint id
, struct gl_program
*prog
)
1624 key
->program_string_id
= id
;
1625 key
->clamp_vertex_color
= ctx
->API
== API_OPENGL_COMPAT
;
1627 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1628 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1629 if (prog
->ShadowSamplers
& (1 << i
)) {
1630 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1631 key
->tex
.swizzles
[i
] =
1632 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1634 /* Color sampler: assume no swizzling. */
1635 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;
1642 brw_vec4_prog_data_compare(const struct brw_vec4_prog_data
*a
,
1643 const struct brw_vec4_prog_data
*b
)
1645 /* Compare all the struct (including the base) up to the pointers. */
1646 if (memcmp(a
, b
, offsetof(struct brw_vec4_prog_data
, param
)))
1649 if (memcmp(a
->param
, b
->param
, a
->nr_params
* sizeof(void *)))
1652 if (memcmp(a
->pull_param
, b
->pull_param
, a
->nr_pull_params
* sizeof(void *)))
1660 brw_vec4_prog_data_free(const struct brw_vec4_prog_data
*prog_data
)
1662 ralloc_free((void *)prog_data
->param
);
1663 ralloc_free((void *)prog_data
->pull_param
);