2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_dead_control_flow.h"
31 #include "main/macros.h"
32 #include "main/shaderobj.h"
33 #include "program/prog_print.h"
34 #include "program/prog_parameter.h"
37 #define MAX_INSTRUCTION (1 << 30)
44 * Common helper for constructing swizzles. When only a subset of
45 * channels of a vec4 are used, we don't want to reference the other
46 * channels, as that will tell optimization passes that those other
50 swizzle_for_size(int size
)
52 static const unsigned size_swizzles
[4] = {
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
54 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
55 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
56 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
59 assert((size
>= 1) && (size
<= 4));
60 return size_swizzles
[size
- 1];
66 memset(this, 0, sizeof(*this));
68 this->file
= BAD_FILE
;
71 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
77 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
78 this->swizzle
= swizzle_for_size(type
->vector_elements
);
80 this->swizzle
= BRW_SWIZZLE_XYZW
;
83 /** Generic unset register constructor. */
89 src_reg::src_reg(float f
)
94 this->type
= BRW_REGISTER_TYPE_F
;
95 this->fixed_hw_reg
.dw1
.f
= f
;
98 src_reg::src_reg(uint32_t u
)
103 this->type
= BRW_REGISTER_TYPE_UD
;
104 this->fixed_hw_reg
.dw1
.ud
= u
;
107 src_reg::src_reg(int32_t i
)
112 this->type
= BRW_REGISTER_TYPE_D
;
113 this->fixed_hw_reg
.dw1
.d
= i
;
116 src_reg::src_reg(uint8_t vf
[4])
121 this->type
= BRW_REGISTER_TYPE_VF
;
122 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
125 src_reg::src_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
130 this->type
= BRW_REGISTER_TYPE_VF
;
131 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
137 src_reg::src_reg(struct brw_reg reg
)
142 this->fixed_hw_reg
= reg
;
143 this->type
= reg
.type
;
146 src_reg::src_reg(dst_reg reg
)
150 this->file
= reg
.file
;
152 this->reg_offset
= reg
.reg_offset
;
153 this->type
= reg
.type
;
154 this->reladdr
= reg
.reladdr
;
155 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
161 for (int i
= 0; i
< 4; i
++) {
162 if (!(reg
.writemask
& (1 << i
)))
165 swizzles
[next_chan
++] = last
= i
;
168 for (; next_chan
< 4; next_chan
++) {
169 swizzles
[next_chan
] = last
;
172 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
173 swizzles
[2], swizzles
[3]);
179 memset(this, 0, sizeof(*this));
180 this->file
= BAD_FILE
;
181 this->writemask
= WRITEMASK_XYZW
;
189 dst_reg::dst_reg(register_file file
, int reg
)
197 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
204 this->type
= brw_type_for_base_type(type
);
205 this->writemask
= writemask
;
208 dst_reg::dst_reg(struct brw_reg reg
)
213 this->fixed_hw_reg
= reg
;
214 this->type
= reg
.type
;
217 dst_reg::dst_reg(src_reg reg
)
221 this->file
= reg
.file
;
223 this->reg_offset
= reg
.reg_offset
;
224 this->type
= reg
.type
;
225 /* How should we do writemasking when converting from a src_reg? It seems
226 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
227 * what about for src.wx? Just special-case src.xxxx for now.
229 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
230 this->writemask
= WRITEMASK_X
;
232 this->writemask
= WRITEMASK_XYZW
;
233 this->reladdr
= reg
.reladdr
;
234 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
238 vec4_instruction::is_send_from_grf()
241 case SHADER_OPCODE_SHADER_TIME_ADD
:
242 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
250 vec4_instruction::can_do_source_mods(struct brw_context
*brw
)
252 if (brw
->gen
== 6 && is_math())
255 if (is_send_from_grf())
258 if (!backend_instruction::can_do_source_mods())
265 * Returns how many MRFs an opcode will write over.
267 * Note that this is not the 0 or 1 implied writes in an actual gen
268 * instruction -- the generate_* functions generate additional MOVs
272 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
277 switch (inst
->opcode
) {
278 case SHADER_OPCODE_RCP
:
279 case SHADER_OPCODE_RSQ
:
280 case SHADER_OPCODE_SQRT
:
281 case SHADER_OPCODE_EXP2
:
282 case SHADER_OPCODE_LOG2
:
283 case SHADER_OPCODE_SIN
:
284 case SHADER_OPCODE_COS
:
286 case SHADER_OPCODE_INT_QUOTIENT
:
287 case SHADER_OPCODE_INT_REMAINDER
:
288 case SHADER_OPCODE_POW
:
290 case VS_OPCODE_URB_WRITE
:
292 case VS_OPCODE_PULL_CONSTANT_LOAD
:
294 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
296 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
298 case GS_OPCODE_URB_WRITE
:
299 case GS_OPCODE_URB_WRITE_ALLOCATE
:
300 case GS_OPCODE_THREAD_END
:
302 case GS_OPCODE_FF_SYNC
:
304 case SHADER_OPCODE_SHADER_TIME_ADD
:
306 case SHADER_OPCODE_TEX
:
307 case SHADER_OPCODE_TXL
:
308 case SHADER_OPCODE_TXD
:
309 case SHADER_OPCODE_TXF
:
310 case SHADER_OPCODE_TXF_CMS
:
311 case SHADER_OPCODE_TXF_MCS
:
312 case SHADER_OPCODE_TXS
:
313 case SHADER_OPCODE_TG4
:
314 case SHADER_OPCODE_TG4_OFFSET
:
315 return inst
->header_present
? 1 : 0;
316 case SHADER_OPCODE_UNTYPED_ATOMIC
:
317 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
320 unreachable("not reached");
325 src_reg::equals(const src_reg
&r
) const
327 return (file
== r
.file
&&
329 reg_offset
== r
.reg_offset
&&
331 negate
== r
.negate
&&
333 swizzle
== r
.swizzle
&&
334 !reladdr
&& !r
.reladdr
&&
335 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
336 sizeof(fixed_hw_reg
)) == 0);
339 /* Replaces unused channels of a swizzle with channels that are used.
341 * For instance, this pass transforms
343 * mov vgrf4.yz, vgrf5.wxzy
347 * mov vgrf4.yz, vgrf5.xxzx
349 * This eliminates false uses of some channels, letting dead code elimination
350 * remove the instructions that wrote them.
353 vec4_visitor::opt_reduce_swizzle()
355 bool progress
= false;
357 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
358 if (inst
->dst
.file
== BAD_FILE
|| inst
->dst
.file
== HW_REG
)
363 /* Determine which channels of the sources are read. */
364 switch (inst
->opcode
) {
365 case VEC4_OPCODE_PACK_BYTES
:
372 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
373 * but all four of src1.
393 swizzle
[0] = inst
->dst
.writemask
& WRITEMASK_X
? 0 : -1;
394 swizzle
[1] = inst
->dst
.writemask
& WRITEMASK_Y
? 1 : -1;
395 swizzle
[2] = inst
->dst
.writemask
& WRITEMASK_Z
? 2 : -1;
396 swizzle
[3] = inst
->dst
.writemask
& WRITEMASK_W
? 3 : -1;
400 /* Resolve unread channels (-1) by assigning them the swizzle of the
401 * first channel that is used.
403 int first_used_channel
= 0;
404 for (int i
= 0; i
< 4; i
++) {
405 if (swizzle
[i
] != -1) {
406 first_used_channel
= swizzle
[i
];
410 for (int i
= 0; i
< 4; i
++) {
411 if (swizzle
[i
] == -1) {
412 swizzle
[i
] = first_used_channel
;
416 /* Update sources' swizzles. */
417 for (int i
= 0; i
< 3; i
++) {
418 if (inst
->src
[i
].file
!= GRF
&&
419 inst
->src
[i
].file
!= ATTR
&&
420 inst
->src
[i
].file
!= UNIFORM
)
424 for (int j
= 0; j
< 4; j
++) {
425 swiz
[j
] = BRW_GET_SWZ(inst
->src
[i
].swizzle
, swizzle
[j
]);
428 unsigned new_swizzle
= BRW_SWIZZLE4(swiz
[0], swiz
[1], swiz
[2], swiz
[3]);
429 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
430 inst
->src
[i
].swizzle
= new_swizzle
;
437 invalidate_live_intervals();
443 vec4_visitor::split_uniform_registers()
445 /* Prior to this, uniforms have been in an array sized according to
446 * the number of vector uniforms present, sparsely filled (so an
447 * aggregate results in reg indices being skipped over). Now we're
448 * going to cut those aggregates up so each .reg index is one
449 * vector. The goal is to make elimination of unused uniform
450 * components easier later.
452 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
453 for (int i
= 0 ; i
< 3; i
++) {
454 if (inst
->src
[i
].file
!= UNIFORM
)
457 assert(!inst
->src
[i
].reladdr
);
459 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
460 inst
->src
[i
].reg_offset
= 0;
464 /* Update that everything is now vector-sized. */
465 for (int i
= 0; i
< this->uniforms
; i
++) {
466 this->uniform_size
[i
] = 1;
471 vec4_visitor::pack_uniform_registers()
473 bool uniform_used
[this->uniforms
];
474 int new_loc
[this->uniforms
];
475 int new_chan
[this->uniforms
];
477 memset(uniform_used
, 0, sizeof(uniform_used
));
478 memset(new_loc
, 0, sizeof(new_loc
));
479 memset(new_chan
, 0, sizeof(new_chan
));
481 /* Find which uniform vectors are actually used by the program. We
482 * expect unused vector elements when we've moved array access out
483 * to pull constants, and from some GLSL code generators like wine.
485 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
486 for (int i
= 0 ; i
< 3; i
++) {
487 if (inst
->src
[i
].file
!= UNIFORM
)
490 uniform_used
[inst
->src
[i
].reg
] = true;
494 int new_uniform_count
= 0;
496 /* Now, figure out a packing of the live uniform vectors into our
499 for (int src
= 0; src
< uniforms
; src
++) {
500 assert(src
< uniform_array_size
);
501 int size
= this->uniform_vector_size
[src
];
503 if (!uniform_used
[src
]) {
504 this->uniform_vector_size
[src
] = 0;
509 /* Find the lowest place we can slot this uniform in. */
510 for (dst
= 0; dst
< src
; dst
++) {
511 if (this->uniform_vector_size
[dst
] + size
<= 4)
520 new_chan
[src
] = this->uniform_vector_size
[dst
];
522 /* Move the references to the data */
523 for (int j
= 0; j
< size
; j
++) {
524 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
525 stage_prog_data
->param
[src
* 4 + j
];
528 this->uniform_vector_size
[dst
] += size
;
529 this->uniform_vector_size
[src
] = 0;
532 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
535 this->uniforms
= new_uniform_count
;
537 /* Now, update the instructions for our repacked uniforms. */
538 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
539 for (int i
= 0 ; i
< 3; i
++) {
540 int src
= inst
->src
[i
].reg
;
542 if (inst
->src
[i
].file
!= UNIFORM
)
545 inst
->src
[i
].reg
= new_loc
[src
];
547 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
548 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
549 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
550 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
551 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
557 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
559 * While GLSL IR also performs this optimization, we end up with it in
560 * our instruction stream for a couple of reasons. One is that we
561 * sometimes generate silly instructions, for example in array access
562 * where we'll generate "ADD offset, index, base" even if base is 0.
563 * The other is that GLSL IR's constant propagation doesn't track the
564 * components of aggregates, so some VS patterns (initialize matrix to
565 * 0, accumulate in vertex blending factors) end up breaking down to
566 * instructions involving 0.
569 vec4_visitor::opt_algebraic()
571 bool progress
= false;
573 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
574 switch (inst
->opcode
) {
576 if (inst
->src
[0].file
!= IMM
)
579 if (inst
->saturate
) {
580 if (inst
->dst
.type
!= inst
->src
[0].type
)
581 assert(!"unimplemented: saturate mixed types");
583 if (brw_saturate_immediate(inst
->dst
.type
,
584 &inst
->src
[0].fixed_hw_reg
)) {
585 inst
->saturate
= false;
591 case VEC4_OPCODE_UNPACK_UNIFORM
:
592 if (inst
->src
[0].file
!= UNIFORM
) {
593 inst
->opcode
= BRW_OPCODE_MOV
;
599 if (inst
->src
[1].is_zero()) {
600 inst
->opcode
= BRW_OPCODE_MOV
;
601 inst
->src
[1] = src_reg();
607 if (inst
->src
[1].is_zero()) {
608 inst
->opcode
= BRW_OPCODE_MOV
;
609 switch (inst
->src
[0].type
) {
610 case BRW_REGISTER_TYPE_F
:
611 inst
->src
[0] = src_reg(0.0f
);
613 case BRW_REGISTER_TYPE_D
:
614 inst
->src
[0] = src_reg(0);
616 case BRW_REGISTER_TYPE_UD
:
617 inst
->src
[0] = src_reg(0u);
620 unreachable("not reached");
622 inst
->src
[1] = src_reg();
624 } else if (inst
->src
[1].is_one()) {
625 inst
->opcode
= BRW_OPCODE_MOV
;
626 inst
->src
[1] = src_reg();
630 case SHADER_OPCODE_RCP
: {
631 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
632 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
633 if (inst
->src
[0].equals(src_reg(prev
->dst
))) {
634 inst
->opcode
= SHADER_OPCODE_RSQ
;
635 inst
->src
[0] = prev
->src
[0];
647 invalidate_live_intervals();
653 * Only a limited number of hardware registers may be used for push
654 * constants, so this turns access to the overflowed constants into
658 vec4_visitor::move_push_constants_to_pull_constants()
660 int pull_constant_loc
[this->uniforms
];
662 /* Only allow 32 registers (256 uniform components) as push constants,
663 * which is the limit on gen6.
665 * If changing this value, note the limitation about total_regs in
668 int max_uniform_components
= 32 * 8;
669 if (this->uniforms
* 4 <= max_uniform_components
)
672 /* Make some sort of choice as to which uniforms get sent to pull
673 * constants. We could potentially do something clever here like
674 * look for the most infrequently used uniform vec4s, but leave
677 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
678 pull_constant_loc
[i
/ 4] = -1;
680 if (i
>= max_uniform_components
) {
681 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
683 /* Try to find an existing copy of this uniform in the pull
684 * constants if it was part of an array access already.
686 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
689 for (matches
= 0; matches
< 4; matches
++) {
690 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
695 pull_constant_loc
[i
/ 4] = j
/ 4;
700 if (pull_constant_loc
[i
/ 4] == -1) {
701 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
702 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
704 for (int j
= 0; j
< 4; j
++) {
705 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
712 /* Now actually rewrite usage of the things we've moved to pull
715 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
716 for (int i
= 0 ; i
< 3; i
++) {
717 if (inst
->src
[i
].file
!= UNIFORM
||
718 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
721 int uniform
= inst
->src
[i
].reg
;
723 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
725 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
726 pull_constant_loc
[uniform
]);
728 inst
->src
[i
].file
= temp
.file
;
729 inst
->src
[i
].reg
= temp
.reg
;
730 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
731 inst
->src
[i
].reladdr
= NULL
;
735 /* Repack push constants to remove the now-unused ones. */
736 pack_uniform_registers();
739 /* Conditions for which we want to avoid setting the dependency control bits */
741 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
743 #define IS_DWORD(reg) \
744 (reg.type == BRW_REGISTER_TYPE_UD || \
745 reg.type == BRW_REGISTER_TYPE_D)
747 /* From the destination hazard section of the spec:
748 * > Instructions other than send, may use this control as long as operations
749 * > that have different pipeline latencies are not mixed.
752 if (inst
->opcode
== BRW_OPCODE_MUL
&&
753 IS_DWORD(inst
->src
[0]) &&
754 IS_DWORD(inst
->src
[1]))
761 * In the presence of send messages, totally interrupt dependency
762 * control. They're long enough that the chance of dependency
763 * control around them just doesn't matter.
766 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
767 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
768 * completes the scoreboard clear must have a non-zero execution mask. This
769 * means, if any kind of predication can change the execution mask or channel
770 * enable of the last instruction, the optimization must be avoided. This is
771 * to avoid instructions being shot down the pipeline when no writes are
775 * Dependency control does not work well over math instructions.
776 * NB: Discovered empirically
778 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
782 * Sets the dependency control fields on instructions after register
783 * allocation and before the generator is run.
785 * When you have a sequence of instructions like:
787 * DP4 temp.x vertex uniform[0]
788 * DP4 temp.y vertex uniform[0]
789 * DP4 temp.z vertex uniform[0]
790 * DP4 temp.w vertex uniform[0]
792 * The hardware doesn't know that it can actually run the later instructions
793 * while the previous ones are in flight, producing stalls. However, we have
794 * manual fields we can set in the instructions that let it do so.
797 vec4_visitor::opt_set_dependency_control()
799 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
800 uint8_t grf_channels_written
[BRW_MAX_GRF
];
801 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
802 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
804 assert(prog_data
->total_grf
||
805 !"Must be called after register allocation");
807 foreach_block (block
, cfg
) {
808 memset(last_grf_write
, 0, sizeof(last_grf_write
));
809 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
811 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
812 /* If we read from a register that we were doing dependency control
813 * on, don't do dependency control across the read.
815 for (int i
= 0; i
< 3; i
++) {
816 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
817 if (inst
->src
[i
].file
== GRF
) {
818 last_grf_write
[reg
] = NULL
;
819 } else if (inst
->src
[i
].file
== HW_REG
) {
820 memset(last_grf_write
, 0, sizeof(last_grf_write
));
823 assert(inst
->src
[i
].file
!= MRF
);
826 if (is_dep_ctrl_unsafe(inst
)) {
827 memset(last_grf_write
, 0, sizeof(last_grf_write
));
828 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
832 /* Now, see if we can do dependency control for this instruction
833 * against a previous one writing to its destination.
835 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
836 if (inst
->dst
.file
== GRF
) {
837 if (last_grf_write
[reg
] &&
838 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
839 last_grf_write
[reg
]->no_dd_clear
= true;
840 inst
->no_dd_check
= true;
842 grf_channels_written
[reg
] = 0;
845 last_grf_write
[reg
] = inst
;
846 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
847 } else if (inst
->dst
.file
== MRF
) {
848 if (last_mrf_write
[reg
] &&
849 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
850 last_mrf_write
[reg
]->no_dd_clear
= true;
851 inst
->no_dd_check
= true;
853 mrf_channels_written
[reg
] = 0;
856 last_mrf_write
[reg
] = inst
;
857 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
858 } else if (inst
->dst
.reg
== HW_REG
) {
859 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
860 memset(last_grf_write
, 0, sizeof(last_grf_write
));
861 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
862 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
869 vec4_instruction::can_reswizzle(int dst_writemask
,
873 /* If this instruction sets anything not referenced by swizzle, then we'd
874 * totally break it when we reswizzle.
876 if (dst
.writemask
& ~swizzle_mask
)
886 * For any channels in the swizzle's source that were populated by this
887 * instruction, rewrite the instruction to put the appropriate result directly
890 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
893 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
895 int new_writemask
= 0;
896 int new_swizzle
[4] = { 0 };
898 /* Dot product instructions write a single result into all channels. */
899 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
900 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
) {
901 for (int i
= 0; i
< 3; i
++) {
902 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
905 /* Destination write mask doesn't correspond to source swizzle for the
906 * pack_bytes instruction.
908 if (opcode
== VEC4_OPCODE_PACK_BYTES
)
911 for (int c
= 0; c
< 4; c
++) {
912 new_swizzle
[c
] = BRW_GET_SWZ(src
[i
].swizzle
, BRW_GET_SWZ(swizzle
, c
));
915 src
[i
].swizzle
= BRW_SWIZZLE4(new_swizzle
[0], new_swizzle
[1],
916 new_swizzle
[2], new_swizzle
[3]);
920 for (int c
= 0; c
< 4; c
++) {
921 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
922 /* Skip components of the swizzle not used by the dst. */
923 if (!(dst_writemask
& (1 << c
)))
925 /* If we were populating this component, then populate the
926 * corresponding channel of the new dst.
928 if (dst
.writemask
& bit
)
929 new_writemask
|= (1 << c
);
931 dst
.writemask
= new_writemask
;
935 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
936 * just written and then MOVed into another reg and making the original write
937 * of the GRF write directly to the final destination instead.
940 vec4_visitor::opt_register_coalesce()
942 bool progress
= false;
945 calculate_live_intervals();
947 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
951 if (inst
->opcode
!= BRW_OPCODE_MOV
||
952 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
954 inst
->src
[0].file
!= GRF
||
955 inst
->dst
.type
!= inst
->src
[0].type
||
956 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
959 bool to_mrf
= (inst
->dst
.file
== MRF
);
961 /* Can't coalesce this GRF if someone else was going to
964 if (this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 0] > ip
||
965 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 1] > ip
||
966 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 2] > ip
||
967 this->virtual_grf_end
[inst
->src
[0].reg
* 4 + 3] > ip
)
970 /* We need to check interference with the final destination between this
971 * instruction and the earliest instruction involved in writing the GRF
972 * we're eliminating. To do that, keep track of which of our source
973 * channels we've seen initialized.
975 bool chans_needed
[4] = {false, false, false, false};
976 int chans_remaining
= 0;
977 int swizzle_mask
= 0;
978 for (int i
= 0; i
< 4; i
++) {
979 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
981 if (!(inst
->dst
.writemask
& (1 << i
)))
984 swizzle_mask
|= (1 << chan
);
986 if (!chans_needed
[chan
]) {
987 chans_needed
[chan
] = true;
992 /* Now walk up the instruction stream trying to see if we can rewrite
993 * everything writing to the temporary to write into the destination
996 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
997 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
999 _scan_inst
= scan_inst
;
1001 if (scan_inst
->dst
.file
== GRF
&&
1002 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1003 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1004 /* Found something writing to the reg we want to coalesce away. */
1006 /* SEND instructions can't have MRF as a destination. */
1007 if (scan_inst
->mlen
)
1010 if (brw
->gen
== 6) {
1011 /* gen6 math instructions must have the destination be
1012 * GRF, so no compute-to-MRF for them.
1014 if (scan_inst
->is_math()) {
1020 /* If we can't handle the swizzle, bail. */
1021 if (!scan_inst
->can_reswizzle(inst
->dst
.writemask
,
1022 inst
->src
[0].swizzle
,
1027 /* Mark which channels we found unconditional writes for. */
1028 if (!scan_inst
->predicate
) {
1029 for (int i
= 0; i
< 4; i
++) {
1030 if (scan_inst
->dst
.writemask
& (1 << i
) &&
1032 chans_needed
[i
] = false;
1038 if (chans_remaining
== 0)
1042 /* You can't read from an MRF, so if someone else reads our MRF's
1043 * source GRF that we wanted to rewrite, that stops us. If it's a
1044 * GRF we're trying to coalesce to, we don't actually handle
1045 * rewriting sources so bail in that case as well.
1047 bool interfered
= false;
1048 for (int i
= 0; i
< 3; i
++) {
1049 if (scan_inst
->src
[i
].file
== GRF
&&
1050 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
1051 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1058 /* If somebody else writes our destination here, we can't coalesce
1061 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
1062 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
1066 /* Check for reads of the register we're trying to coalesce into. We
1067 * can't go rewriting instructions above that to put some other value
1068 * in the register instead.
1070 if (to_mrf
&& scan_inst
->mlen
> 0) {
1071 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
1072 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1076 for (int i
= 0; i
< 3; i
++) {
1077 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
1078 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
1079 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
1088 if (chans_remaining
== 0) {
1089 /* If we've made it here, we have an MOV we want to coalesce out, and
1090 * a scan_inst pointing to the earliest instruction involved in
1091 * computing the value. Now go rewrite the instruction stream
1094 vec4_instruction
*scan_inst
= _scan_inst
;
1095 while (scan_inst
!= inst
) {
1096 if (scan_inst
->dst
.file
== GRF
&&
1097 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
1098 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1099 scan_inst
->reswizzle(inst
->dst
.writemask
,
1100 inst
->src
[0].swizzle
);
1101 scan_inst
->dst
.file
= inst
->dst
.file
;
1102 scan_inst
->dst
.reg
= inst
->dst
.reg
;
1103 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1104 scan_inst
->saturate
|= inst
->saturate
;
1106 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1108 inst
->remove(block
);
1114 invalidate_live_intervals();
1120 * Splits virtual GRFs requesting more than one contiguous physical register.
1122 * We initially create large virtual GRFs for temporary structures, arrays,
1123 * and matrices, so that the dereference visitor functions can add reg_offsets
1124 * to work their way down to the actual member being accessed. But when it
1125 * comes to optimization, we'd like to treat each register as individual
1126 * storage if possible.
1128 * So far, the only thing that might prevent splitting is a send message from
1132 vec4_visitor::split_virtual_grfs()
1134 int num_vars
= this->virtual_grf_count
;
1135 int new_virtual_grf
[num_vars
];
1136 bool split_grf
[num_vars
];
1138 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1140 /* Try to split anything > 0 sized. */
1141 for (int i
= 0; i
< num_vars
; i
++) {
1142 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1145 /* Check that the instructions are compatible with the registers we're trying
1148 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1149 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1152 if (inst
->is_send_from_grf()) {
1153 for (int i
= 0; i
< 3; i
++) {
1154 if (inst
->src
[i
].file
== GRF
) {
1155 split_grf
[inst
->src
[i
].reg
] = false;
1161 /* Allocate new space for split regs. Note that the virtual
1162 * numbers will be contiguous.
1164 for (int i
= 0; i
< num_vars
; i
++) {
1168 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1169 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1170 int reg
= virtual_grf_alloc(1);
1171 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1174 this->virtual_grf_sizes
[i
] = 1;
1177 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1178 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1179 inst
->dst
.reg_offset
!= 0) {
1180 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1181 inst
->dst
.reg_offset
- 1);
1182 inst
->dst
.reg_offset
= 0;
1184 for (int i
= 0; i
< 3; i
++) {
1185 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1186 inst
->src
[i
].reg_offset
!= 0) {
1187 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1188 inst
->src
[i
].reg_offset
- 1);
1189 inst
->src
[i
].reg_offset
= 0;
1193 invalidate_live_intervals();
1197 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1199 dump_instruction(be_inst
, stderr
);
1203 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1205 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1207 if (inst
->predicate
) {
1208 fprintf(file
, "(%cf0) ",
1209 inst
->predicate_inverse
? '-' : '+');
1212 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1213 if (inst
->conditional_mod
) {
1214 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1218 switch (inst
->dst
.file
) {
1220 fprintf(file
, "vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1223 fprintf(file
, "m%d", inst
->dst
.reg
);
1226 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1227 switch (inst
->dst
.fixed_hw_reg
.nr
) {
1229 fprintf(file
, "null");
1231 case BRW_ARF_ADDRESS
:
1232 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
1234 case BRW_ARF_ACCUMULATOR
:
1235 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
1238 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1239 inst
->dst
.fixed_hw_reg
.subnr
);
1242 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
1243 inst
->dst
.fixed_hw_reg
.subnr
);
1247 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
1249 if (inst
->dst
.fixed_hw_reg
.subnr
)
1250 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
1253 fprintf(file
, "(null)");
1256 fprintf(file
, "???");
1259 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1261 if (inst
->dst
.writemask
& 1)
1263 if (inst
->dst
.writemask
& 2)
1265 if (inst
->dst
.writemask
& 4)
1267 if (inst
->dst
.writemask
& 8)
1270 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1272 if (inst
->src
[0].file
!= BAD_FILE
)
1273 fprintf(file
, ", ");
1275 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1276 if (inst
->src
[i
].negate
)
1278 if (inst
->src
[i
].abs
)
1280 switch (inst
->src
[i
].file
) {
1282 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
1285 fprintf(file
, "attr%d", inst
->src
[i
].reg
);
1288 fprintf(file
, "u%d", inst
->src
[i
].reg
);
1291 switch (inst
->src
[i
].type
) {
1292 case BRW_REGISTER_TYPE_F
:
1293 fprintf(file
, "%fF", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
1295 case BRW_REGISTER_TYPE_D
:
1296 fprintf(file
, "%dD", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
1298 case BRW_REGISTER_TYPE_UD
:
1299 fprintf(file
, "%uU", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
1301 case BRW_REGISTER_TYPE_VF
:
1302 fprintf(stderr
, "[%-gF, %-gF, %-gF, %-gF]",
1303 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
1304 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
1305 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
1306 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
1309 fprintf(file
, "???");
1314 if (inst
->src
[i
].fixed_hw_reg
.negate
)
1316 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1318 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1319 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
1321 fprintf(file
, "null");
1323 case BRW_ARF_ADDRESS
:
1324 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1326 case BRW_ARF_ACCUMULATOR
:
1327 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1330 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1331 inst
->src
[i
].fixed_hw_reg
.subnr
);
1334 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
1335 inst
->src
[i
].fixed_hw_reg
.subnr
);
1339 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
1341 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
1342 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
1343 if (inst
->src
[i
].fixed_hw_reg
.abs
)
1347 fprintf(file
, "(null)");
1350 fprintf(file
, "???");
1354 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1355 if (inst
->src
[i
].reg_offset
!= 0 &&
1356 inst
->src
[i
].file
== GRF
&&
1357 virtual_grf_sizes
[inst
->src
[i
].reg
] != 1)
1358 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1360 if (inst
->src
[i
].file
!= IMM
) {
1361 static const char *chans
[4] = {"x", "y", "z", "w"};
1363 for (int c
= 0; c
< 4; c
++) {
1364 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1368 if (inst
->src
[i
].abs
)
1371 if (inst
->src
[i
].file
!= IMM
) {
1372 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1375 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1376 fprintf(file
, ", ");
1379 fprintf(file
, "\n");
1383 static inline struct brw_reg
1384 attribute_to_hw_reg(int attr
, bool interleaved
)
1387 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1389 return brw_vec8_grf(attr
, 0);
1394 * Replace each register of type ATTR in this->instructions with a reference
1395 * to a fixed HW register.
1397 * If interleaved is true, then each attribute takes up half a register, with
1398 * register N containing attribute 2*N in its first half and attribute 2*N+1
1399 * in its second half (this corresponds to the payload setup used by geometry
1400 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1401 * false, then each attribute takes up a whole register, with register N
1402 * containing attribute N (this corresponds to the payload setup used by
1403 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1406 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1409 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1410 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1411 if (inst
->dst
.file
== ATTR
) {
1412 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1414 /* All attributes used in the shader need to have been assigned a
1415 * hardware register by the caller
1419 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1420 reg
.type
= inst
->dst
.type
;
1421 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1423 inst
->dst
.file
= HW_REG
;
1424 inst
->dst
.fixed_hw_reg
= reg
;
1427 for (int i
= 0; i
< 3; i
++) {
1428 if (inst
->src
[i
].file
!= ATTR
)
1431 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1433 /* All attributes used in the shader need to have been assigned a
1434 * hardware register by the caller
1438 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1439 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1440 reg
.type
= inst
->src
[i
].type
;
1441 if (inst
->src
[i
].abs
)
1443 if (inst
->src
[i
].negate
)
1446 inst
->src
[i
].file
= HW_REG
;
1447 inst
->src
[i
].fixed_hw_reg
= reg
;
1453 vec4_vs_visitor::setup_attributes(int payload_reg
)
1456 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1457 memset(attribute_map
, 0, sizeof(attribute_map
));
1460 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1461 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1462 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1467 /* VertexID is stored by the VF as the last vertex element, but we
1468 * don't represent it with a flag in inputs_read, so we call it
1471 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
) {
1472 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1476 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1478 /* The BSpec says we always have to read at least one thing from
1479 * the VF, and it appears that the hardware wedges otherwise.
1481 if (nr_attributes
== 0)
1484 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1486 unsigned vue_entries
=
1487 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1490 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1492 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1494 return payload_reg
+ nr_attributes
;
1498 vec4_visitor::setup_uniforms(int reg
)
1500 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1502 /* The pre-gen6 VS requires that some push constants get loaded no
1503 * matter what, or the GPU would hang.
1505 if (brw
->gen
< 6 && this->uniforms
== 0) {
1506 assert(this->uniforms
< this->uniform_array_size
);
1507 this->uniform_vector_size
[this->uniforms
] = 1;
1509 stage_prog_data
->param
=
1510 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1511 for (unsigned int i
= 0; i
< 4; i
++) {
1512 unsigned int slot
= this->uniforms
* 4 + i
;
1513 static gl_constant_value zero
= { 0.0 };
1514 stage_prog_data
->param
[slot
] = &zero
;
1520 reg
+= ALIGN(uniforms
, 2) / 2;
1523 stage_prog_data
->nr_params
= this->uniforms
* 4;
1525 prog_data
->base
.curb_read_length
=
1526 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1532 vec4_vs_visitor::setup_payload(void)
1536 /* The payload always contains important data in g0, which contains
1537 * the URB handles that are passed on to the URB write at the end
1538 * of the thread. So, we always start push constants at g1.
1542 reg
= setup_uniforms(reg
);
1544 reg
= setup_attributes(reg
);
1546 this->first_non_payload_grf
= reg
;
1550 vec4_visitor::assign_binding_table_offsets()
1552 assign_common_binding_table_offsets(0);
1556 vec4_visitor::get_timestamp()
1558 assert(brw
->gen
>= 7);
1560 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1565 BRW_REGISTER_TYPE_UD
,
1566 BRW_VERTICAL_STRIDE_0
,
1568 BRW_HORIZONTAL_STRIDE_4
,
1572 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1574 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1575 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1576 * even if it's not enabled in the dispatch.
1578 mov
->force_writemask_all
= true;
1580 return src_reg(dst
);
1584 vec4_visitor::emit_shader_time_begin()
1586 current_annotation
= "shader time start";
1587 shader_start_time
= get_timestamp();
1591 vec4_visitor::emit_shader_time_end()
1593 current_annotation
= "shader time end";
1594 src_reg shader_end_time
= get_timestamp();
1597 /* Check that there weren't any timestamp reset events (assuming these
1598 * were the only two timestamp reads that happened).
1600 src_reg reset_end
= shader_end_time
;
1601 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1602 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1603 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1605 emit(IF(BRW_PREDICATE_NORMAL
));
1607 /* Take the current timestamp and get the delta. */
1608 shader_start_time
.negate
= true;
1609 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1610 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1612 /* If there were no instructions between the two timestamp gets, the diff
1613 * is 2 cycles. Remove that overhead, so I can forget about that when
1614 * trying to determine the time taken for single instructions.
1616 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1618 emit_shader_time_write(st_base
, src_reg(diff
));
1619 emit_shader_time_write(st_written
, src_reg(1u));
1620 emit(BRW_OPCODE_ELSE
);
1621 emit_shader_time_write(st_reset
, src_reg(1u));
1622 emit(BRW_OPCODE_ENDIF
);
1626 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1629 int shader_time_index
=
1630 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1633 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1635 dst_reg offset
= dst
;
1639 offset
.type
= BRW_REGISTER_TYPE_UD
;
1640 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1642 time
.type
= BRW_REGISTER_TYPE_UD
;
1643 emit(MOV(time
, src_reg(value
)));
1645 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1651 sanity_param_count
= prog
->Parameters
->NumParameters
;
1653 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1654 emit_shader_time_begin();
1656 assign_binding_table_offsets();
1660 /* Generate VS IR for main(). (the visitor only descends into
1661 * functions called "main").
1664 visit_instructions(shader
->base
.ir
);
1666 emit_program_code();
1670 if (key
->userclip_active
&& !prog
->UsesClipDistanceOut
)
1671 setup_uniform_clipplane_values();
1677 /* Before any optimization, push array accesses out to scratch
1678 * space where we need them to be. This pass may allocate new
1679 * virtual GRFs, so we want to do it early. It also makes sure
1680 * that we have reladdr computations available for CSE, since we'll
1681 * often do repeated subexpressions for those.
1684 move_grf_array_access_to_scratch();
1685 move_uniform_array_access_to_pull_constants();
1687 /* The ARB_vertex_program frontend emits pull constant loads directly
1688 * rather than using reladdr, so we don't need to walk through all the
1689 * instructions looking for things to move. There isn't anything.
1691 * We do still need to split things to vec4 size.
1693 split_uniform_registers();
1695 pack_uniform_registers();
1696 move_push_constants_to_pull_constants();
1697 split_virtual_grfs();
1699 const char *stage_name
= stage
== MESA_SHADER_GEOMETRY
? "gs" : "vs";
1701 #define OPT(pass, args...) do { \
1703 bool this_progress = pass(args); \
1705 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1706 char filename[64]; \
1707 snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
1708 stage_name, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
1710 backend_visitor::dump_instructions(filename); \
1713 progress = progress || this_progress; \
1717 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1719 snprintf(filename
, 64, "%s-%04d-00-start",
1720 stage_name
, shader_prog
? shader_prog
->Name
: 0);
1722 backend_visitor::dump_instructions(filename
);
1732 OPT(opt_reduce_swizzle
);
1733 OPT(dead_code_eliminate
);
1734 OPT(dead_control_flow_eliminate
, this);
1735 OPT(opt_copy_propagation
);
1738 OPT(opt_register_coalesce
);
1748 /* Debug of register spilling: Go spill everything. */
1749 const int grf_count
= virtual_grf_count
;
1750 float spill_costs
[virtual_grf_count
];
1751 bool no_spill
[virtual_grf_count
];
1752 evaluate_spill_costs(spill_costs
, no_spill
);
1753 for (int i
= 0; i
< grf_count
; i
++) {
1760 while (!reg_allocate()) {
1765 opt_schedule_instructions();
1767 opt_set_dependency_control();
1769 /* If any state parameters were appended, then ParameterValues could have
1770 * been realloced, in which case the driver uniform storage set up by
1771 * _mesa_associate_uniform_storage() would point to freed memory. Make
1772 * sure that didn't happen.
1774 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1779 } /* namespace brw */
1784 * Compile a vertex shader.
1786 * Returns the final assembly and the program's size.
1789 brw_vs_emit(struct brw_context
*brw
,
1790 struct gl_shader_program
*prog
,
1791 struct brw_vs_compile
*c
,
1792 struct brw_vs_prog_data
*prog_data
,
1794 unsigned *final_assembly_size
)
1796 bool start_busy
= false;
1797 double start_time
= 0;
1798 const unsigned *assembly
= NULL
;
1800 if (unlikely(brw
->perf_debug
)) {
1801 start_busy
= (brw
->batch
.last_bo
&&
1802 drm_intel_bo_busy(brw
->batch
.last_bo
));
1803 start_time
= get_time();
1806 struct brw_shader
*shader
= NULL
;
1808 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1810 if (unlikely(INTEL_DEBUG
& DEBUG_VS
))
1811 brw_dump_ir("vertex", prog
, &shader
->base
, &c
->vp
->program
.Base
);
1813 if (prog
&& brw
->gen
>= 8 && brw
->scalar_vs
) {
1814 fs_visitor
v(brw
, mem_ctx
, &c
->key
, prog_data
, prog
, &c
->vp
->program
, 8);
1817 prog
->LinkStatus
= false;
1818 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1821 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1827 fs_generator
g(brw
, mem_ctx
, (void *) &c
->key
, &prog_data
->base
.base
,
1828 &c
->vp
->program
.Base
, v
.runtime_check_aads_emit
);
1829 if (INTEL_DEBUG
& DEBUG_VS
) {
1830 char *name
= ralloc_asprintf(mem_ctx
, "%s vertex shader %d",
1831 prog
->Label
? prog
->Label
: "unnamed",
1833 g
.enable_debug(name
);
1835 g
.generate_code(v
.cfg
, 8);
1836 assembly
= g
.get_assembly(final_assembly_size
);
1839 prog_data
->base
.simd8
= true;
1840 c
->base
.last_scratch
= v
.last_scratch
;
1844 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, mem_ctx
);
1847 prog
->LinkStatus
= false;
1848 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1851 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1857 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, &prog_data
->base
,
1858 mem_ctx
, INTEL_DEBUG
& DEBUG_VS
);
1859 assembly
= g
.generate_assembly(v
.cfg
, final_assembly_size
);
1862 if (unlikely(brw
->perf_debug
) && shader
) {
1863 if (shader
->compiled_once
) {
1864 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1866 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1867 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1868 (get_time() - start_time
) * 1000);
1870 shader
->compiled_once
= true;
1878 brw_vue_setup_prog_key_for_precompile(struct gl_context
*ctx
,
1879 struct brw_vue_prog_key
*key
,
1880 GLuint id
, struct gl_program
*prog
)
1882 key
->program_string_id
= id
;
1884 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
1885 for (unsigned i
= 0; i
< sampler_count
; i
++) {
1886 if (prog
->ShadowSamplers
& (1 << i
)) {
1887 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
1888 key
->tex
.swizzles
[i
] =
1889 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
1891 /* Color sampler: assume no swizzling. */
1892 key
->tex
.swizzles
[i
] = SWIZZLE_XYZW
;