2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_builder.h"
30 #include "brw_vec4_live_variables.h"
31 #include "brw_dead_control_flow.h"
32 #include "program/prog_parameter.h"
34 #define MAX_INSTRUCTION (1 << 30)
43 memset(this, 0, sizeof(*this));
45 this->file
= BAD_FILE
;
48 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
54 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
55 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
57 this->swizzle
= BRW_SWIZZLE_XYZW
;
59 this->type
= brw_type_for_base_type(type
);
62 /** Generic unset register constructor. */
68 src_reg::src_reg(struct ::brw_reg reg
) :
75 src_reg::src_reg(const dst_reg
®
) :
78 this->reladdr
= reg
.reladdr
;
79 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
85 memset(this, 0, sizeof(*this));
86 this->file
= BAD_FILE
;
87 this->writemask
= WRITEMASK_XYZW
;
95 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
103 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
110 this->type
= brw_type_for_base_type(type
);
111 this->writemask
= writemask
;
114 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
122 this->writemask
= writemask
;
125 dst_reg::dst_reg(struct ::brw_reg reg
) :
128 this->reg_offset
= 0;
129 this->reladdr
= NULL
;
132 dst_reg::dst_reg(const src_reg
®
) :
135 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
136 this->reladdr
= reg
.reladdr
;
140 dst_reg::equals(const dst_reg
&r
) const
142 return (this->backend_reg::equals(r
) &&
143 (reladdr
== r
.reladdr
||
144 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
148 vec4_instruction::is_send_from_grf()
151 case SHADER_OPCODE_SHADER_TIME_ADD
:
152 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
153 case SHADER_OPCODE_UNTYPED_ATOMIC
:
154 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
155 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
156 case SHADER_OPCODE_TYPED_ATOMIC
:
157 case SHADER_OPCODE_TYPED_SURFACE_READ
:
158 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
159 case VEC4_OPCODE_URB_READ
:
160 case TCS_OPCODE_URB_WRITE
:
161 case TCS_OPCODE_RELEASE_INPUT
:
162 case SHADER_OPCODE_BARRIER
:
170 * Returns true if this instruction's sources and destinations cannot
171 * safely be the same register.
173 * In most cases, a register can be written over safely by the same
174 * instruction that is its last use. For a single instruction, the
175 * sources are dereferenced before writing of the destination starts
178 * However, there are a few cases where this can be problematic:
180 * - Virtual opcodes that translate to multiple instructions in the
181 * code generator: if src == dst and one instruction writes the
182 * destination before a later instruction reads the source, then
183 * src will have been clobbered.
185 * The register allocator uses this information to set up conflicts between
186 * GRF sources and the destination.
189 vec4_instruction::has_source_and_destination_hazard() const
192 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
193 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
194 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
202 vec4_instruction::regs_read(unsigned arg
) const
204 if (src
[arg
].file
== BAD_FILE
)
208 case SHADER_OPCODE_SHADER_TIME_ADD
:
209 case SHADER_OPCODE_UNTYPED_ATOMIC
:
210 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
211 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
212 case SHADER_OPCODE_TYPED_ATOMIC
:
213 case SHADER_OPCODE_TYPED_SURFACE_READ
:
214 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
215 case TCS_OPCODE_URB_WRITE
:
216 return arg
== 0 ? mlen
: 1;
218 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
219 return arg
== 1 ? mlen
: 1;
227 vec4_instruction::can_do_source_mods(const struct brw_device_info
*devinfo
)
229 if (devinfo
->gen
== 6 && is_math())
232 if (is_send_from_grf())
235 if (!backend_instruction::can_do_source_mods())
242 vec4_instruction::can_do_writemask(const struct brw_device_info
*devinfo
)
245 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
246 case VS_OPCODE_PULL_CONSTANT_LOAD
:
247 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
248 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
249 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
250 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
251 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
252 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
253 case VEC4_OPCODE_URB_READ
:
256 /* The MATH instruction on Gen6 only executes in align1 mode, which does
257 * not support writemasking.
259 if (devinfo
->gen
== 6 && is_math())
270 vec4_instruction::can_change_types() const
272 return dst
.type
== src
[0].type
&&
273 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
274 (opcode
== BRW_OPCODE_MOV
||
275 (opcode
== BRW_OPCODE_SEL
&&
276 dst
.type
== src
[1].type
&&
277 predicate
!= BRW_PREDICATE_NONE
&&
278 !src
[1].abs
&& !src
[1].negate
));
282 * Returns how many MRFs an opcode will write over.
284 * Note that this is not the 0 or 1 implied writes in an actual gen
285 * instruction -- the generate_* functions generate additional MOVs
289 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
291 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
294 switch (inst
->opcode
) {
295 case SHADER_OPCODE_RCP
:
296 case SHADER_OPCODE_RSQ
:
297 case SHADER_OPCODE_SQRT
:
298 case SHADER_OPCODE_EXP2
:
299 case SHADER_OPCODE_LOG2
:
300 case SHADER_OPCODE_SIN
:
301 case SHADER_OPCODE_COS
:
303 case SHADER_OPCODE_INT_QUOTIENT
:
304 case SHADER_OPCODE_INT_REMAINDER
:
305 case SHADER_OPCODE_POW
:
306 case TCS_OPCODE_THREAD_END
:
308 case VS_OPCODE_URB_WRITE
:
310 case VS_OPCODE_PULL_CONSTANT_LOAD
:
312 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
314 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
316 case GS_OPCODE_URB_WRITE
:
317 case GS_OPCODE_URB_WRITE_ALLOCATE
:
318 case GS_OPCODE_THREAD_END
:
320 case GS_OPCODE_FF_SYNC
:
322 case TCS_OPCODE_URB_WRITE
:
324 case SHADER_OPCODE_SHADER_TIME_ADD
:
326 case SHADER_OPCODE_TEX
:
327 case SHADER_OPCODE_TXL
:
328 case SHADER_OPCODE_TXD
:
329 case SHADER_OPCODE_TXF
:
330 case SHADER_OPCODE_TXF_CMS
:
331 case SHADER_OPCODE_TXF_CMS_W
:
332 case SHADER_OPCODE_TXF_MCS
:
333 case SHADER_OPCODE_TXS
:
334 case SHADER_OPCODE_TG4
:
335 case SHADER_OPCODE_TG4_OFFSET
:
336 case SHADER_OPCODE_SAMPLEINFO
:
337 case VS_OPCODE_GET_BUFFER_SIZE
:
338 return inst
->header_size
;
340 unreachable("not reached");
345 src_reg::equals(const src_reg
&r
) const
347 return (this->backend_reg::equals(r
) &&
348 !reladdr
&& !r
.reladdr
);
352 vec4_visitor::vectorize_mov(bblock_t
*block
, vec4_instruction
*inst
,
353 uint8_t imm
[4], vec4_instruction
*imm_inst
[4],
354 int inst_count
, unsigned writemask
)
360 memcpy(&vf
, imm
, sizeof(vf
));
361 vec4_instruction
*mov
= MOV(imm_inst
[0]->dst
, brw_imm_vf(vf
));
362 mov
->dst
.type
= BRW_REGISTER_TYPE_F
;
363 mov
->dst
.writemask
= writemask
;
364 inst
->insert_before(block
, mov
);
366 for (int i
= 0; i
< inst_count
; i
++) {
367 imm_inst
[i
]->remove(block
);
374 vec4_visitor::opt_vector_float()
376 bool progress
= false;
378 int last_reg
= -1, last_reg_offset
= -1;
379 enum brw_reg_file last_reg_file
= BAD_FILE
;
381 uint8_t imm
[4] = { 0 };
383 vec4_instruction
*imm_inst
[4];
384 unsigned writemask
= 0;
386 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
387 if (last_reg
!= inst
->dst
.nr
||
388 last_reg_offset
!= inst
->dst
.reg_offset
||
389 last_reg_file
!= inst
->dst
.file
) {
390 progress
|= vectorize_mov(block
, inst
, imm
, imm_inst
, inst_count
,
394 last_reg
= inst
->dst
.nr
;
395 last_reg_offset
= inst
->dst
.reg_offset
;
396 last_reg_file
= inst
->dst
.file
;
398 for (int i
= 0; i
< 4; i
++) {
403 if (inst
->opcode
!= BRW_OPCODE_MOV
||
404 inst
->dst
.writemask
== WRITEMASK_XYZW
||
405 inst
->src
[0].file
!= IMM
||
406 inst
->predicate
!= BRW_PREDICATE_NONE
) {
407 progress
|= vectorize_mov(block
, inst
, imm
, imm_inst
, inst_count
,
414 int vf
= brw_float_to_vf(inst
->src
[0].f
);
418 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
420 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
422 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
424 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
427 writemask
|= inst
->dst
.writemask
;
428 imm_inst
[inst_count
++] = inst
;
432 invalidate_live_intervals();
437 /* Replaces unused channels of a swizzle with channels that are used.
439 * For instance, this pass transforms
441 * mov vgrf4.yz, vgrf5.wxzy
445 * mov vgrf4.yz, vgrf5.xxzx
447 * This eliminates false uses of some channels, letting dead code elimination
448 * remove the instructions that wrote them.
451 vec4_visitor::opt_reduce_swizzle()
453 bool progress
= false;
455 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
456 if (inst
->dst
.file
== BAD_FILE
||
457 inst
->dst
.file
== ARF
||
458 inst
->dst
.file
== FIXED_GRF
||
459 inst
->is_send_from_grf())
464 /* Determine which channels of the sources are read. */
465 switch (inst
->opcode
) {
466 case VEC4_OPCODE_PACK_BYTES
:
468 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
469 * but all four of src1.
471 swizzle
= brw_swizzle_for_size(4);
474 swizzle
= brw_swizzle_for_size(3);
477 swizzle
= brw_swizzle_for_size(2);
480 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
484 /* Update sources' swizzles. */
485 for (int i
= 0; i
< 3; i
++) {
486 if (inst
->src
[i
].file
!= VGRF
&&
487 inst
->src
[i
].file
!= ATTR
&&
488 inst
->src
[i
].file
!= UNIFORM
)
491 const unsigned new_swizzle
=
492 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
493 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
494 inst
->src
[i
].swizzle
= new_swizzle
;
501 invalidate_live_intervals();
507 vec4_visitor::split_uniform_registers()
509 /* Prior to this, uniforms have been in an array sized according to
510 * the number of vector uniforms present, sparsely filled (so an
511 * aggregate results in reg indices being skipped over). Now we're
512 * going to cut those aggregates up so each .nr index is one
513 * vector. The goal is to make elimination of unused uniform
514 * components easier later.
516 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
517 for (int i
= 0 ; i
< 3; i
++) {
518 if (inst
->src
[i
].file
!= UNIFORM
)
521 assert(!inst
->src
[i
].reladdr
);
523 inst
->src
[i
].nr
+= inst
->src
[i
].reg_offset
;
524 inst
->src
[i
].reg_offset
= 0;
530 vec4_visitor::pack_uniform_registers()
532 uint8_t chans_used
[this->uniforms
];
533 int new_loc
[this->uniforms
];
534 int new_chan
[this->uniforms
];
536 memset(chans_used
, 0, sizeof(chans_used
));
537 memset(new_loc
, 0, sizeof(new_loc
));
538 memset(new_chan
, 0, sizeof(new_chan
));
540 /* Find which uniform vectors are actually used by the program. We
541 * expect unused vector elements when we've moved array access out
542 * to pull constants, and from some GLSL code generators like wine.
544 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
546 switch (inst
->opcode
) {
547 case VEC4_OPCODE_PACK_BYTES
:
559 readmask
= inst
->dst
.writemask
;
563 for (int i
= 0 ; i
< 3; i
++) {
564 if (inst
->src
[i
].file
!= UNIFORM
)
567 int reg
= inst
->src
[i
].nr
;
568 for (int c
= 0; c
< 4; c
++) {
569 if (!(readmask
& (1 << c
)))
572 chans_used
[reg
] = MAX2(chans_used
[reg
],
573 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
578 int new_uniform_count
= 0;
580 /* Now, figure out a packing of the live uniform vectors into our
583 for (int src
= 0; src
< uniforms
; src
++) {
584 int size
= chans_used
[src
];
590 /* Find the lowest place we can slot this uniform in. */
591 for (dst
= 0; dst
< src
; dst
++) {
592 if (chans_used
[dst
] + size
<= 4)
601 new_chan
[src
] = chans_used
[dst
];
603 /* Move the references to the data */
604 for (int j
= 0; j
< size
; j
++) {
605 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
606 stage_prog_data
->param
[src
* 4 + j
];
609 chans_used
[dst
] += size
;
613 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
616 this->uniforms
= new_uniform_count
;
618 /* Now, update the instructions for our repacked uniforms. */
619 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
620 for (int i
= 0 ; i
< 3; i
++) {
621 int src
= inst
->src
[i
].nr
;
623 if (inst
->src
[i
].file
!= UNIFORM
)
626 inst
->src
[i
].nr
= new_loc
[src
];
627 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
628 new_chan
[src
], new_chan
[src
]);
634 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
636 * While GLSL IR also performs this optimization, we end up with it in
637 * our instruction stream for a couple of reasons. One is that we
638 * sometimes generate silly instructions, for example in array access
639 * where we'll generate "ADD offset, index, base" even if base is 0.
640 * The other is that GLSL IR's constant propagation doesn't track the
641 * components of aggregates, so some VS patterns (initialize matrix to
642 * 0, accumulate in vertex blending factors) end up breaking down to
643 * instructions involving 0.
646 vec4_visitor::opt_algebraic()
648 bool progress
= false;
650 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
651 switch (inst
->opcode
) {
653 if (inst
->src
[0].file
!= IMM
)
656 if (inst
->saturate
) {
657 if (inst
->dst
.type
!= inst
->src
[0].type
)
658 assert(!"unimplemented: saturate mixed types");
660 if (brw_saturate_immediate(inst
->dst
.type
,
661 &inst
->src
[0].as_brw_reg())) {
662 inst
->saturate
= false;
668 case VEC4_OPCODE_UNPACK_UNIFORM
:
669 if (inst
->src
[0].file
!= UNIFORM
) {
670 inst
->opcode
= BRW_OPCODE_MOV
;
676 if (inst
->src
[1].is_zero()) {
677 inst
->opcode
= BRW_OPCODE_MOV
;
678 inst
->src
[1] = src_reg();
684 if (inst
->src
[1].is_zero()) {
685 inst
->opcode
= BRW_OPCODE_MOV
;
686 switch (inst
->src
[0].type
) {
687 case BRW_REGISTER_TYPE_F
:
688 inst
->src
[0] = brw_imm_f(0.0f
);
690 case BRW_REGISTER_TYPE_D
:
691 inst
->src
[0] = brw_imm_d(0);
693 case BRW_REGISTER_TYPE_UD
:
694 inst
->src
[0] = brw_imm_ud(0u);
697 unreachable("not reached");
699 inst
->src
[1] = src_reg();
701 } else if (inst
->src
[1].is_one()) {
702 inst
->opcode
= BRW_OPCODE_MOV
;
703 inst
->src
[1] = src_reg();
705 } else if (inst
->src
[1].is_negative_one()) {
706 inst
->opcode
= BRW_OPCODE_MOV
;
707 inst
->src
[0].negate
= !inst
->src
[0].negate
;
708 inst
->src
[1] = src_reg();
713 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
715 inst
->src
[0].negate
&&
716 inst
->src
[1].is_zero()) {
717 inst
->src
[0].abs
= false;
718 inst
->src
[0].negate
= false;
719 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
724 case SHADER_OPCODE_BROADCAST
:
725 if (is_uniform(inst
->src
[0]) ||
726 inst
->src
[1].is_zero()) {
727 inst
->opcode
= BRW_OPCODE_MOV
;
728 inst
->src
[1] = src_reg();
729 inst
->force_writemask_all
= true;
740 invalidate_live_intervals();
746 * Only a limited number of hardware registers may be used for push
747 * constants, so this turns access to the overflowed constants into
751 vec4_visitor::move_push_constants_to_pull_constants()
753 int pull_constant_loc
[this->uniforms
];
755 /* Only allow 32 registers (256 uniform components) as push constants,
756 * which is the limit on gen6.
758 * If changing this value, note the limitation about total_regs in
761 int max_uniform_components
= 32 * 8;
762 if (this->uniforms
* 4 <= max_uniform_components
)
765 /* Make some sort of choice as to which uniforms get sent to pull
766 * constants. We could potentially do something clever here like
767 * look for the most infrequently used uniform vec4s, but leave
770 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
771 pull_constant_loc
[i
/ 4] = -1;
773 if (i
>= max_uniform_components
) {
774 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
776 /* Try to find an existing copy of this uniform in the pull
777 * constants if it was part of an array access already.
779 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
782 for (matches
= 0; matches
< 4; matches
++) {
783 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
788 pull_constant_loc
[i
/ 4] = j
/ 4;
793 if (pull_constant_loc
[i
/ 4] == -1) {
794 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
795 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
797 for (int j
= 0; j
< 4; j
++) {
798 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
805 /* Now actually rewrite usage of the things we've moved to pull
808 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
809 for (int i
= 0 ; i
< 3; i
++) {
810 if (inst
->src
[i
].file
!= UNIFORM
||
811 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
814 int uniform
= inst
->src
[i
].nr
;
816 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
818 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
819 pull_constant_loc
[uniform
], src_reg());
821 inst
->src
[i
].file
= temp
.file
;
822 inst
->src
[i
].nr
= temp
.nr
;
823 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
824 inst
->src
[i
].reladdr
= NULL
;
828 /* Repack push constants to remove the now-unused ones. */
829 pack_uniform_registers();
832 /* Conditions for which we want to avoid setting the dependency control bits */
834 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
836 #define IS_DWORD(reg) \
837 (reg.type == BRW_REGISTER_TYPE_UD || \
838 reg.type == BRW_REGISTER_TYPE_D)
840 /* "When source or destination datatype is 64b or operation is integer DWord
841 * multiply, DepCtrl must not be used."
842 * May apply to future SoCs as well.
844 if (devinfo
->is_cherryview
) {
845 if (inst
->opcode
== BRW_OPCODE_MUL
&&
846 IS_DWORD(inst
->src
[0]) &&
847 IS_DWORD(inst
->src
[1]))
852 if (devinfo
->gen
>= 8) {
853 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
859 * In the presence of send messages, totally interrupt dependency
860 * control. They're long enough that the chance of dependency
861 * control around them just doesn't matter.
864 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
865 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
866 * completes the scoreboard clear must have a non-zero execution mask. This
867 * means, if any kind of predication can change the execution mask or channel
868 * enable of the last instruction, the optimization must be avoided. This is
869 * to avoid instructions being shot down the pipeline when no writes are
873 * Dependency control does not work well over math instructions.
874 * NB: Discovered empirically
876 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
880 * Sets the dependency control fields on instructions after register
881 * allocation and before the generator is run.
883 * When you have a sequence of instructions like:
885 * DP4 temp.x vertex uniform[0]
886 * DP4 temp.y vertex uniform[0]
887 * DP4 temp.z vertex uniform[0]
888 * DP4 temp.w vertex uniform[0]
890 * The hardware doesn't know that it can actually run the later instructions
891 * while the previous ones are in flight, producing stalls. However, we have
892 * manual fields we can set in the instructions that let it do so.
895 vec4_visitor::opt_set_dependency_control()
897 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
898 uint8_t grf_channels_written
[BRW_MAX_GRF
];
899 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
900 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
902 assert(prog_data
->total_grf
||
903 !"Must be called after register allocation");
905 foreach_block (block
, cfg
) {
906 memset(last_grf_write
, 0, sizeof(last_grf_write
));
907 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
909 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
910 /* If we read from a register that we were doing dependency control
911 * on, don't do dependency control across the read.
913 for (int i
= 0; i
< 3; i
++) {
914 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
915 if (inst
->src
[i
].file
== VGRF
) {
916 last_grf_write
[reg
] = NULL
;
917 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
918 memset(last_grf_write
, 0, sizeof(last_grf_write
));
921 assert(inst
->src
[i
].file
!= MRF
);
924 if (is_dep_ctrl_unsafe(inst
)) {
925 memset(last_grf_write
, 0, sizeof(last_grf_write
));
926 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
930 /* Now, see if we can do dependency control for this instruction
931 * against a previous one writing to its destination.
933 int reg
= inst
->dst
.nr
+ inst
->dst
.reg_offset
;
934 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
935 if (last_grf_write
[reg
] &&
936 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
937 last_grf_write
[reg
]->no_dd_clear
= true;
938 inst
->no_dd_check
= true;
940 grf_channels_written
[reg
] = 0;
943 last_grf_write
[reg
] = inst
;
944 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
945 } else if (inst
->dst
.file
== MRF
) {
946 if (last_mrf_write
[reg
] &&
947 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
948 last_mrf_write
[reg
]->no_dd_clear
= true;
949 inst
->no_dd_check
= true;
951 mrf_channels_written
[reg
] = 0;
954 last_mrf_write
[reg
] = inst
;
955 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
962 vec4_instruction::can_reswizzle(const struct brw_device_info
*devinfo
,
967 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
968 * or writemasking are not allowed.
970 if (devinfo
->gen
== 6 && is_math() &&
971 (swizzle
!= BRW_SWIZZLE_XYZW
|| dst_writemask
!= WRITEMASK_XYZW
))
974 /* If this instruction sets anything not referenced by swizzle, then we'd
975 * totally break it when we reswizzle.
977 if (dst
.writemask
& ~swizzle_mask
)
983 for (int i
= 0; i
< 3; i
++) {
984 if (src
[i
].is_accumulator())
992 * For any channels in the swizzle's source that were populated by this
993 * instruction, rewrite the instruction to put the appropriate result directly
996 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
999 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1001 /* Destination write mask doesn't correspond to source swizzle for the dot
1002 * product and pack_bytes instructions.
1004 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1005 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1006 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1007 for (int i
= 0; i
< 3; i
++) {
1008 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1011 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1015 /* Apply the specified swizzle and writemask to the original mask of
1016 * written components.
1018 dst
.writemask
= dst_writemask
&
1019 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1023 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1024 * just written and then MOVed into another reg and making the original write
1025 * of the GRF write directly to the final destination instead.
1028 vec4_visitor::opt_register_coalesce()
1030 bool progress
= false;
1033 calculate_live_intervals();
1035 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1039 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1040 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1042 inst
->src
[0].file
!= VGRF
||
1043 inst
->dst
.type
!= inst
->src
[0].type
||
1044 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1047 /* Remove no-op MOVs */
1048 if (inst
->dst
.file
== inst
->src
[0].file
&&
1049 inst
->dst
.nr
== inst
->src
[0].nr
&&
1050 inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1051 bool is_nop_mov
= true;
1053 for (unsigned c
= 0; c
< 4; c
++) {
1054 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1057 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1064 inst
->remove(block
);
1070 bool to_mrf
= (inst
->dst
.file
== MRF
);
1072 /* Can't coalesce this GRF if someone else was going to
1075 if (var_range_end(var_from_reg(alloc
, inst
->src
[0]), 4) > ip
)
1078 /* We need to check interference with the final destination between this
1079 * instruction and the earliest instruction involved in writing the GRF
1080 * we're eliminating. To do that, keep track of which of our source
1081 * channels we've seen initialized.
1083 const unsigned chans_needed
=
1084 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1085 inst
->dst
.writemask
);
1086 unsigned chans_remaining
= chans_needed
;
1088 /* Now walk up the instruction stream trying to see if we can rewrite
1089 * everything writing to the temporary to write into the destination
1092 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1093 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1095 _scan_inst
= scan_inst
;
1097 if (inst
->src
[0].in_range(scan_inst
->dst
, scan_inst
->regs_written
)) {
1098 /* Found something writing to the reg we want to coalesce away. */
1100 /* SEND instructions can't have MRF as a destination. */
1101 if (scan_inst
->mlen
)
1104 if (devinfo
->gen
== 6) {
1105 /* gen6 math instructions must have the destination be
1106 * VGRF, so no compute-to-MRF for them.
1108 if (scan_inst
->is_math()) {
1114 /* This doesn't handle saturation on the instruction we
1115 * want to coalesce away if the register types do not match.
1116 * But if scan_inst is a non type-converting 'mov', we can fix
1119 if (inst
->saturate
&&
1120 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1121 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1122 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1125 /* If we can't handle the swizzle, bail. */
1126 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1127 inst
->src
[0].swizzle
,
1132 /* This doesn't handle coalescing of multiple registers. */
1133 if (scan_inst
->regs_written
> 1)
1136 /* Mark which channels we found unconditional writes for. */
1137 if (!scan_inst
->predicate
)
1138 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1140 if (chans_remaining
== 0)
1144 /* You can't read from an MRF, so if someone else reads our MRF's
1145 * source GRF that we wanted to rewrite, that stops us. If it's a
1146 * GRF we're trying to coalesce to, we don't actually handle
1147 * rewriting sources so bail in that case as well.
1149 bool interfered
= false;
1150 for (int i
= 0; i
< 3; i
++) {
1151 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1152 scan_inst
->regs_read(i
)))
1158 /* If somebody else writes the same channels of our destination here,
1159 * we can't coalesce before that.
1161 if (inst
->dst
.in_range(scan_inst
->dst
, scan_inst
->regs_written
) &&
1162 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1166 /* Check for reads of the register we're trying to coalesce into. We
1167 * can't go rewriting instructions above that to put some other value
1168 * in the register instead.
1170 if (to_mrf
&& scan_inst
->mlen
> 0) {
1171 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1172 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1176 for (int i
= 0; i
< 3; i
++) {
1177 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1178 scan_inst
->regs_read(i
)))
1186 if (chans_remaining
== 0) {
1187 /* If we've made it here, we have an MOV we want to coalesce out, and
1188 * a scan_inst pointing to the earliest instruction involved in
1189 * computing the value. Now go rewrite the instruction stream
1192 vec4_instruction
*scan_inst
= _scan_inst
;
1193 while (scan_inst
!= inst
) {
1194 if (scan_inst
->dst
.file
== VGRF
&&
1195 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1196 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
1197 scan_inst
->reswizzle(inst
->dst
.writemask
,
1198 inst
->src
[0].swizzle
);
1199 scan_inst
->dst
.file
= inst
->dst
.file
;
1200 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1201 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
1202 if (inst
->saturate
&&
1203 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1204 /* If we have reached this point, scan_inst is a non
1205 * type-converting 'mov' and we can modify its register types
1206 * to match the ones in inst. Otherwise, we could have an
1207 * incorrect saturation result.
1209 scan_inst
->dst
.type
= inst
->dst
.type
;
1210 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1212 scan_inst
->saturate
|= inst
->saturate
;
1214 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1216 inst
->remove(block
);
1222 invalidate_live_intervals();
1228 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1229 * flow. We could probably do better here with some form of divergence
1233 vec4_visitor::eliminate_find_live_channel()
1235 bool progress
= false;
1238 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1239 switch (inst
->opcode
) {
1245 case BRW_OPCODE_ENDIF
:
1246 case BRW_OPCODE_WHILE
:
1250 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1252 inst
->opcode
= BRW_OPCODE_MOV
;
1253 inst
->src
[0] = brw_imm_d(0);
1254 inst
->force_writemask_all
= true;
1268 * Splits virtual GRFs requesting more than one contiguous physical register.
1270 * We initially create large virtual GRFs for temporary structures, arrays,
1271 * and matrices, so that the dereference visitor functions can add reg_offsets
1272 * to work their way down to the actual member being accessed. But when it
1273 * comes to optimization, we'd like to treat each register as individual
1274 * storage if possible.
1276 * So far, the only thing that might prevent splitting is a send message from
1280 vec4_visitor::split_virtual_grfs()
1282 int num_vars
= this->alloc
.count
;
1283 int new_virtual_grf
[num_vars
];
1284 bool split_grf
[num_vars
];
1286 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1288 /* Try to split anything > 0 sized. */
1289 for (int i
= 0; i
< num_vars
; i
++) {
1290 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1293 /* Check that the instructions are compatible with the registers we're trying
1296 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1297 if (inst
->dst
.file
== VGRF
&& inst
->regs_written
> 1)
1298 split_grf
[inst
->dst
.nr
] = false;
1300 for (int i
= 0; i
< 3; i
++) {
1301 if (inst
->src
[i
].file
== VGRF
&& inst
->regs_read(i
) > 1)
1302 split_grf
[inst
->src
[i
].nr
] = false;
1306 /* Allocate new space for split regs. Note that the virtual
1307 * numbers will be contiguous.
1309 for (int i
= 0; i
< num_vars
; i
++) {
1313 new_virtual_grf
[i
] = alloc
.allocate(1);
1314 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1315 unsigned reg
= alloc
.allocate(1);
1316 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1319 this->alloc
.sizes
[i
] = 1;
1322 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1323 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1324 inst
->dst
.reg_offset
!= 0) {
1325 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1326 inst
->dst
.reg_offset
- 1);
1327 inst
->dst
.reg_offset
= 0;
1329 for (int i
= 0; i
< 3; i
++) {
1330 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1331 inst
->src
[i
].reg_offset
!= 0) {
1332 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1333 inst
->src
[i
].reg_offset
- 1);
1334 inst
->src
[i
].reg_offset
= 0;
1338 invalidate_live_intervals();
1342 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1344 dump_instruction(be_inst
, stderr
);
1348 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1350 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1352 if (inst
->predicate
) {
1353 fprintf(file
, "(%cf0.%d%s) ",
1354 inst
->predicate_inverse
? '-' : '+',
1356 pred_ctrl_align16
[inst
->predicate
]);
1359 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
1361 fprintf(file
, ".sat");
1362 if (inst
->conditional_mod
) {
1363 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1364 if (!inst
->predicate
&&
1365 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1366 inst
->opcode
!= BRW_OPCODE_IF
&&
1367 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1368 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1373 switch (inst
->dst
.file
) {
1375 fprintf(file
, "vgrf%d.%d", inst
->dst
.nr
, inst
->dst
.reg_offset
);
1378 fprintf(file
, "g%d", inst
->dst
.nr
);
1381 fprintf(file
, "m%d", inst
->dst
.nr
);
1384 switch (inst
->dst
.nr
) {
1386 fprintf(file
, "null");
1388 case BRW_ARF_ADDRESS
:
1389 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1391 case BRW_ARF_ACCUMULATOR
:
1392 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1395 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1398 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1401 if (inst
->dst
.subnr
)
1402 fprintf(file
, "+%d", inst
->dst
.subnr
);
1405 fprintf(file
, "(null)");
1410 unreachable("not reached");
1412 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1414 if (inst
->dst
.writemask
& 1)
1416 if (inst
->dst
.writemask
& 2)
1418 if (inst
->dst
.writemask
& 4)
1420 if (inst
->dst
.writemask
& 8)
1423 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1425 if (inst
->src
[0].file
!= BAD_FILE
)
1426 fprintf(file
, ", ");
1428 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1429 if (inst
->src
[i
].negate
)
1431 if (inst
->src
[i
].abs
)
1433 switch (inst
->src
[i
].file
) {
1435 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1438 fprintf(file
, "g%d", inst
->src
[i
].nr
);
1441 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1444 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1447 switch (inst
->src
[i
].type
) {
1448 case BRW_REGISTER_TYPE_F
:
1449 fprintf(file
, "%fF", inst
->src
[i
].f
);
1451 case BRW_REGISTER_TYPE_D
:
1452 fprintf(file
, "%dD", inst
->src
[i
].d
);
1454 case BRW_REGISTER_TYPE_UD
:
1455 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1457 case BRW_REGISTER_TYPE_VF
:
1458 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1459 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1460 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1461 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1462 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1465 fprintf(file
, "???");
1470 switch (inst
->src
[i
].nr
) {
1472 fprintf(file
, "null");
1474 case BRW_ARF_ADDRESS
:
1475 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1477 case BRW_ARF_ACCUMULATOR
:
1478 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1481 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1484 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1487 if (inst
->src
[i
].subnr
)
1488 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
1491 fprintf(file
, "(null)");
1494 unreachable("not reached");
1497 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1498 if (inst
->src
[i
].reg_offset
!= 0 &&
1499 inst
->src
[i
].file
== VGRF
&&
1500 alloc
.sizes
[inst
->src
[i
].nr
] != 1)
1501 fprintf(file
, ".%d", inst
->src
[i
].reg_offset
);
1503 if (inst
->src
[i
].file
!= IMM
) {
1504 static const char *chans
[4] = {"x", "y", "z", "w"};
1506 for (int c
= 0; c
< 4; c
++) {
1507 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1511 if (inst
->src
[i
].abs
)
1514 if (inst
->src
[i
].file
!= IMM
) {
1515 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1518 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1519 fprintf(file
, ", ");
1522 if (inst
->force_writemask_all
)
1523 fprintf(file
, " NoMask");
1525 fprintf(file
, "\n");
1529 static inline struct brw_reg
1530 attribute_to_hw_reg(int attr
, bool interleaved
)
1533 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1535 return brw_vec8_grf(attr
, 0);
1540 * Replace each register of type ATTR in this->instructions with a reference
1541 * to a fixed HW register.
1543 * If interleaved is true, then each attribute takes up half a register, with
1544 * register N containing attribute 2*N in its first half and attribute 2*N+1
1545 * in its second half (this corresponds to the payload setup used by geometry
1546 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1547 * false, then each attribute takes up a whole register, with register N
1548 * containing attribute N (this corresponds to the payload setup used by
1549 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1552 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1555 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1556 for (int i
= 0; i
< 3; i
++) {
1557 if (inst
->src
[i
].file
!= ATTR
)
1560 int grf
= attribute_map
[inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
];
1562 /* All attributes used in the shader need to have been assigned a
1563 * hardware register by the caller
1567 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1568 reg
.swizzle
= inst
->src
[i
].swizzle
;
1569 reg
.type
= inst
->src
[i
].type
;
1570 if (inst
->src
[i
].abs
)
1572 if (inst
->src
[i
].negate
)
1581 vec4_vs_visitor::setup_attributes(int payload_reg
)
1584 int attribute_map
[VERT_ATTRIB_MAX
+ 2];
1585 memset(attribute_map
, 0, sizeof(attribute_map
));
1588 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1589 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1590 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1595 /* VertexID is stored by the VF as the last vertex element, but we
1596 * don't represent it with a flag in inputs_read, so we call it
1599 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
1600 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
) {
1601 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1605 if (vs_prog_data
->uses_drawid
) {
1606 attribute_map
[VERT_ATTRIB_MAX
+ 1] = payload_reg
+ nr_attributes
;
1610 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1612 return payload_reg
+ vs_prog_data
->nr_attributes
;
1616 vec4_visitor::setup_uniforms(int reg
)
1618 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1620 /* The pre-gen6 VS requires that some push constants get loaded no
1621 * matter what, or the GPU would hang.
1623 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1624 stage_prog_data
->param
=
1625 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1626 for (unsigned int i
= 0; i
< 4; i
++) {
1627 unsigned int slot
= this->uniforms
* 4 + i
;
1628 static gl_constant_value zero
= { 0.0 };
1629 stage_prog_data
->param
[slot
] = &zero
;
1635 reg
+= ALIGN(uniforms
, 2) / 2;
1638 stage_prog_data
->nr_params
= this->uniforms
* 4;
1640 prog_data
->base
.curb_read_length
=
1641 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1647 vec4_vs_visitor::setup_payload(void)
1651 /* The payload always contains important data in g0, which contains
1652 * the URB handles that are passed on to the URB write at the end
1653 * of the thread. So, we always start push constants at g1.
1657 reg
= setup_uniforms(reg
);
1659 reg
= setup_attributes(reg
);
1661 this->first_non_payload_grf
= reg
;
1665 vec4_visitor::lower_minmax()
1667 assert(devinfo
->gen
< 6);
1669 bool progress
= false;
1671 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1672 const vec4_builder
ibld(this, block
, inst
);
1674 if (inst
->opcode
== BRW_OPCODE_SEL
&&
1675 inst
->predicate
== BRW_PREDICATE_NONE
) {
1676 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
1677 * the original SEL.L/GE instruction
1679 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
1680 inst
->conditional_mod
);
1681 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1682 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
1689 invalidate_live_intervals();
1695 vec4_visitor::get_timestamp()
1697 assert(devinfo
->gen
>= 7);
1699 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1704 BRW_REGISTER_TYPE_UD
,
1705 BRW_VERTICAL_STRIDE_0
,
1707 BRW_HORIZONTAL_STRIDE_4
,
1711 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1713 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1714 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1715 * even if it's not enabled in the dispatch.
1717 mov
->force_writemask_all
= true;
1719 return src_reg(dst
);
1723 vec4_visitor::emit_shader_time_begin()
1725 current_annotation
= "shader time start";
1726 shader_start_time
= get_timestamp();
1730 vec4_visitor::emit_shader_time_end()
1732 current_annotation
= "shader time end";
1733 src_reg shader_end_time
= get_timestamp();
1736 /* Check that there weren't any timestamp reset events (assuming these
1737 * were the only two timestamp reads that happened).
1739 src_reg reset_end
= shader_end_time
;
1740 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1741 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1742 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1744 emit(IF(BRW_PREDICATE_NORMAL
));
1746 /* Take the current timestamp and get the delta. */
1747 shader_start_time
.negate
= true;
1748 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1749 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1751 /* If there were no instructions between the two timestamp gets, the diff
1752 * is 2 cycles. Remove that overhead, so I can forget about that when
1753 * trying to determine the time taken for single instructions.
1755 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1757 emit_shader_time_write(0, src_reg(diff
));
1758 emit_shader_time_write(1, brw_imm_ud(1u));
1759 emit(BRW_OPCODE_ELSE
);
1760 emit_shader_time_write(2, brw_imm_ud(1u));
1761 emit(BRW_OPCODE_ENDIF
);
1765 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1768 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1770 dst_reg offset
= dst
;
1774 offset
.type
= BRW_REGISTER_TYPE_UD
;
1775 int index
= shader_time_index
* 3 + shader_time_subindex
;
1776 emit(MOV(offset
, brw_imm_d(index
* SHADER_TIME_STRIDE
)));
1778 time
.type
= BRW_REGISTER_TYPE_UD
;
1779 emit(MOV(time
, value
));
1781 vec4_instruction
*inst
=
1782 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1787 vec4_visitor::convert_to_hw_regs()
1789 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1790 for (int i
= 0; i
< 3; i
++) {
1791 struct src_reg
&src
= inst
->src
[i
];
1795 reg
= brw_vec8_grf(src
.nr
+ src
.reg_offset
, 0);
1796 reg
.type
= src
.type
;
1797 reg
.swizzle
= src
.swizzle
;
1799 reg
.negate
= src
.negate
;
1803 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1804 (src
.nr
+ src
.reg_offset
) / 2,
1805 ((src
.nr
+ src
.reg_offset
) % 2) * 4),
1807 reg
.type
= src
.type
;
1808 reg
.swizzle
= src
.swizzle
;
1810 reg
.negate
= src
.negate
;
1812 /* This should have been moved to pull constants. */
1813 assert(!src
.reladdr
);
1822 /* Probably unused. */
1823 reg
= brw_null_reg();
1828 unreachable("not reached");
1834 if (inst
->is_3src()) {
1835 /* 3-src instructions with scalar sources support arbitrary subnr,
1836 * but don't actually use swizzles. Convert swizzle into subnr.
1838 for (int i
= 0; i
< 3; i
++) {
1839 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
) {
1840 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
1841 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
1846 dst_reg
&dst
= inst
->dst
;
1849 switch (inst
->dst
.file
) {
1851 reg
= brw_vec8_grf(dst
.nr
+ dst
.reg_offset
, 0);
1852 reg
.type
= dst
.type
;
1853 reg
.writemask
= dst
.writemask
;
1857 assert(((dst
.nr
+ dst
.reg_offset
) & ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
1858 reg
= brw_message_reg(dst
.nr
+ dst
.reg_offset
);
1859 reg
.type
= dst
.type
;
1860 reg
.writemask
= dst
.writemask
;
1865 reg
= dst
.as_brw_reg();
1869 reg
= brw_null_reg();
1875 unreachable("not reached");
1885 if (shader_time_index
>= 0)
1886 emit_shader_time_begin();
1899 /* Before any optimization, push array accesses out to scratch
1900 * space where we need them to be. This pass may allocate new
1901 * virtual GRFs, so we want to do it early. It also makes sure
1902 * that we have reladdr computations available for CSE, since we'll
1903 * often do repeated subexpressions for those.
1905 move_grf_array_access_to_scratch();
1906 move_uniform_array_access_to_pull_constants();
1908 pack_uniform_registers();
1909 move_push_constants_to_pull_constants();
1910 split_virtual_grfs();
1912 #define OPT(pass, args...) ({ \
1914 bool this_progress = pass(args); \
1916 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1917 char filename[64]; \
1918 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1919 stage_abbrev, nir->info.name, iteration, pass_num); \
1921 backend_shader::dump_instructions(filename); \
1924 progress = progress || this_progress; \
1929 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1931 snprintf(filename
, 64, "%s-%s-00-00-start",
1932 stage_abbrev
, nir
->info
.name
);
1934 backend_shader::dump_instructions(filename
);
1945 OPT(opt_predicated_break
, this);
1946 OPT(opt_reduce_swizzle
);
1947 OPT(dead_code_eliminate
);
1948 OPT(dead_control_flow_eliminate
, this);
1949 OPT(opt_copy_propagation
);
1950 OPT(opt_cmod_propagation
);
1953 OPT(opt_register_coalesce
);
1954 OPT(eliminate_find_live_channel
);
1959 if (OPT(opt_vector_float
)) {
1961 OPT(opt_copy_propagation
, false);
1962 OPT(opt_copy_propagation
, true);
1963 OPT(dead_code_eliminate
);
1966 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
1967 OPT(opt_cmod_propagation
);
1969 OPT(opt_copy_propagation
);
1970 OPT(dead_code_eliminate
);
1978 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
1979 /* Debug of register spilling: Go spill everything. */
1980 const int grf_count
= alloc
.count
;
1981 float spill_costs
[alloc
.count
];
1982 bool no_spill
[alloc
.count
];
1983 evaluate_spill_costs(spill_costs
, no_spill
);
1984 for (int i
= 0; i
< grf_count
; i
++) {
1991 bool allocated_without_spills
= reg_allocate();
1993 if (!allocated_without_spills
) {
1994 compiler
->shader_perf_log(log_data
,
1995 "%s shader triggered register spilling. "
1996 "Try reducing the number of live vec4 values "
1997 "to improve performance.\n",
2000 while (!reg_allocate()) {
2006 opt_schedule_instructions();
2008 opt_set_dependency_control();
2010 convert_to_hw_regs();
2012 if (last_scratch
> 0) {
2013 prog_data
->base
.total_scratch
=
2014 brw_get_scratch_size(last_scratch
* REG_SIZE
);
2020 } /* namespace brw */
2025 * Compile a vertex shader.
2027 * Returns the final assembly and the program's size.
2030 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2032 const struct brw_vs_prog_key
*key
,
2033 struct brw_vs_prog_data
*prog_data
,
2034 const nir_shader
*src_shader
,
2035 gl_clip_plane
*clip_planes
,
2036 bool use_legacy_snorm_formula
,
2037 int shader_time_index
,
2038 unsigned *final_assembly_size
,
2041 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
2042 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
2043 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
2045 brw_nir_lower_vs_inputs(shader
, compiler
->devinfo
, is_scalar
,
2046 use_legacy_snorm_formula
, key
->gl_attrib_wa_flags
);
2047 brw_nir_lower_vue_outputs(shader
, is_scalar
);
2048 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, is_scalar
);
2050 const unsigned *assembly
= NULL
;
2052 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
2054 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2055 * incoming vertex attribute. So, add an extra slot.
2057 if (shader
->info
.system_values_read
&
2058 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
2059 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
2060 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2061 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2065 /* gl_DrawID has its very own vec4 */
2066 if (shader
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
)) {
2070 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2071 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2072 * vec4 mode, the hardware appears to wedge unless we read something.
2075 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(nr_attributes
, 2);
2077 prog_data
->base
.urb_read_length
= DIV_ROUND_UP(MAX2(nr_attributes
, 1), 2);
2079 prog_data
->nr_attributes
= nr_attributes
;
2081 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2082 * (overwriting the original contents), we need to make sure the size is
2083 * the larger of the two.
2085 const unsigned vue_entries
=
2086 MAX2(nr_attributes
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2088 if (compiler
->devinfo
->gen
== 6)
2089 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2091 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2094 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2096 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2097 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2098 shader
, 8, shader_time_index
);
2099 if (!v
.run_vs(clip_planes
)) {
2101 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2106 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2107 &prog_data
->base
.base
, v
.promoted_constants
,
2108 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2109 if (INTEL_DEBUG
& DEBUG_VS
) {
2110 const char *debug_name
=
2111 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2112 shader
->info
.label
? shader
->info
.label
: "unnamed",
2115 g
.enable_debug(debug_name
);
2117 g
.generate_code(v
.cfg
, 8);
2118 assembly
= g
.get_assembly(final_assembly_size
);
2122 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2124 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2125 shader
, clip_planes
, mem_ctx
,
2126 shader_time_index
, use_legacy_snorm_formula
);
2129 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2134 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2135 shader
, &prog_data
->base
, v
.cfg
,
2136 final_assembly_size
);